CN216049932U

CN216049932U - Novel wire-saving encoder circuit

Info

Publication number: CN216049932U
Application number: CN202122426500.XU
Authority: CN
Inventors: 梁岩; 于兆武
Original assignee: Changchun Shenghao Electronics Co ltd
Current assignee: Changchun Shenghao Electronics Co ltd
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2022-03-15
Anticipated expiration: 2031-10-09

Abstract

The utility model relates to a novel wire-saving encoder circuit, which comprises a photocell chip U1, a phase sequence selection circuit and an output selection circuit, wherein the output selection circuit comprises a main control chip U2, a differential drive chip U3 and three triode output selection branches with the same structure; the phase sequence selection circuit comprises three phase sequence selection branches with the same structure, each sub-branch of the three phase sequence selection branches is respectively connected with a corresponding pin of the photocell chip U1 and is also respectively connected with the three triode output selection branches in a one-to-one correspondence manner, and the output ends of the three triode output selection branches are respectively connected with the input ends of the differential drive chip U3 in a one-to-one correspondence manner; the main control chip U2 generates U, V, W signals through the phase sequence selection circuit, the triode output selection branch circuit and the differential drive chip U3, and then outputs A, B, Z signals to the servo motor driver. According to the utility model, U, V, W signals and A, B, Z signals can share the transmission cable, so that the transmission cable is saved.

Description

Novel wire-saving encoder circuit

Technical Field

The utility model relates to the technical field of encoders, in particular to a novel wire-saving encoder circuit.

Background

The control circuit of the servo motor needs to obtain U, V, W signals and A, B, Z signals of the servo motor when in work, and the process is one of the most important techniques for controlling the servo motor in terms of whether the servo motor can be controlled in high-precision operation. At present, the conventional incremental photoelectric rotary encoder or the incremental magnetoelectric rotary encoder outputs A, B, Z, U, V, W six paths of signals, so six pairs of (A +/A-, B +/B-, Z +/Z-, U +/U-, V +/V-, W +/W-) transmission cables are needed, the number of the needed transmission cables is large, the wiring is complex, the wrong connection is easy, and the cost is high. In the conventional encoder, a selection chip (e.g., SN74HC157) is usually added to select an output signal, which means that an additional chip is required, and is not favorable for miniaturization of the encoder. In addition, the delay time Ta and Tb of the encoder commonly used in the market at present generally change along with the change of the power-on voltage, so the encoder is easy to be interfered and the accuracy is influenced.

SUMMERY OF THE UTILITY MODEL

The utility model provides a novel wire-saving encoder circuit, which aims to solve the problems that the existing encoder needs more transmission cables, is easy to interfere and influences the precision.

In order to solve the problems, the utility model adopts the following technical scheme:

a novel wire-saving encoder circuit comprises a photocell chip U1, a phase sequence selection circuit and an output selection circuit, wherein the output selection circuit comprises a main control chip U2, a differential drive chip U3 and a triode output selection branch with the same three-way structure;

the phase sequence selection circuit comprises three phase sequence selection branches with the same structure, each phase sequence selection branch comprises six sub-branches which are respectively a PA/U sub-branch, a PB/V sub-branch, a PZ/W sub-branch, a U sub-branch, a V sub-branch and a W sub-branch, the PA/U sub-branch in the three phase sequence selection branches is respectively connected with a PA/U pin of the photocell chip U1, the PB/V sub-branch is respectively connected with a PB/V pin of the photocell chip U1, the PZ/W sub-branch is respectively connected with a PZ/W pin of the photocell chip U1, the U sub-branch in the three phase sequence selection branches is respectively connected with a U pin of the photocell chip U1, the V sub-branch is respectively connected with a V pin of the photocell chip U1, the W sub-branch is respectively connected with a W pin of the photocell chip U1, the three phase sequence selection branches are respectively connected with the three triode output selection branches IN A one-to-one correspondence manner, and the output ends of the three triode output selection branches are respectively connected with the input ends IN-A, IN-B and IN-C of the differential drive chip U3 IN A one-to-one correspondence manner;

an EN pin of the differential driving chip U3 is connected with A P3.3 pin of the main control chip U2, A P1.1 pin and A P1.2 pin of the main control chip U2 are respectively connected with an output selection branch of A triode corresponding to an input end IN-A, A P1.3 pin and A P1.4 pin of the main control chip U2 are respectively connected with an output selection branch of the triode corresponding to an input end IN-B, and A P1.0 pin and A P1.5 pin of the main control chip U2 are respectively connected with an output selection branch of the triode corresponding to an input end IN-C;

the IO port of the main control chip U2 is set to be in an open collector mode, after the encoder circuit is powered on to reach a threshold voltage Va, the main control chip U2 firstly maintains a section of Ta high-resistance time, then U, V, W three-way signals are generated through the phase sequence selection circuit, the three-way triode output selection branch and the differential drive chip U3, and after U, V, W three-way signals maintain Tb time, A, B, Z signals are finally output to the servo motor driver.

Compared with the prior art, the utility model has the following beneficial effects:

the U, V, W signal and A, B, Z signal of the novel wire-saving encoder circuit can share a transmission cable, and the ABZ and UVW phase sequence can be adjusted, so that the transmission cable is saved, the wiring operation is simplified, and the cost is reduced; the chip is replaced and selected through the triode, so that the cost is further reduced; the time delay Ta and Tb are calculated by the main control chip U2, and the method is more accurate and is anti-interference.

Drawings

FIG. 1 is a schematic circuit diagram of a novel wire-saving encoder circuit according to the present invention;

FIG. 2 is a schematic circuit diagram of a main control chip in the novel wire-saving encoder circuit according to the present invention;

fig. 3 is a schematic circuit diagram of a photocell chip in a novel wire-saving encoder circuit according to the present invention.

Detailed Description

The technical solution of the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.

The utility model discloses a novel wire-saving encoder circuit which comprises a photocell chip U1, a phase sequence selection circuit and an output selection circuit, wherein the output selection circuit comprises a main control chip U2, a differential drive chip U3 and three triode output selection branches with the same structure.

Specifically, the phase sequence selection circuit comprises three phase sequence selection branches with the same structure, each phase sequence selection branch comprises six sub-branches, namely a PA/U sub-branch, a PB/V sub-branch, a PZ/W sub-branch, a U sub-branch, a V sub-branch and a W sub-branch, the PA/U sub-branch in the three phase sequence selection branches is respectively connected with a PA/U pin of a photocell chip U1, the PB/V sub-branch in the three phase sequence selection branches is respectively connected with a PB/V pin of a photocell chip U1, the PZ/W sub-branch in the three phase sequence selection branches is respectively connected with a PZ/W pin of a photocell chip U1, the U sub-branches in the three phase sequence selection branches are respectively connected with a U pin of the photocell chip U1, the V sub-branch in the three phase sequence selection branches is respectively connected with a V pin of the photocell chip U1, and W sub-branches in the three phase sequence selection branches are respectively connected with a W pin of the photocell chip U1. As shown in fig. 1, the PA/U sub-branch of the first phase sequence selection branch includes a resistor R7, the PB/V sub-branch includes a resistor R10, the PZ/W sub-branch includes a resistor R58, the U sub-branch includes a resistor R11, the V sub-branch includes a resistor R16, and the W sub-branch includes a resistor R50; the PA/U sub-branch of the second phase sequence selection branch comprises a resistor R18, the PB/V sub-branch comprises a resistor R21, the PZ/W sub-branch comprises a resistor R59, the U sub-branch comprises a resistor R51, the V sub-branch comprises a resistor R51, and the W sub-branch comprises a resistor R53; the PA/U sub-branch of the third phase sequence selection branch comprises a resistor R55, the PB/V sub-branch comprises a resistor R56, the PZ/W sub-branch comprises a resistor R57, the U sub-branch comprises a resistor R28, the V sub-branch comprises a resistor R32, and the W sub-branch comprises a resistor R54. One end of each of the resistor R7, the resistor R18 and the resistor R55 is connected with a PA/U pin of the photocell chip U1, and the other end of each of the resistors R7, R18 and R55 is connected with a corresponding triode output selection branch; one ends of the resistor R10, the resistor R21 and the resistor R56 are connected with a PB/V pin of the photocell chip U1, and the other ends of the resistors R10, the resistor R21 and the resistor R56 are respectively connected with corresponding triode output selection branches; one end of each of the resistor R58, the resistor R59 and the resistor R57 is connected with the PZ/W pin of the photocell chip U1, and the other end of each of the resistors R58, R59 and R57 is connected with the corresponding triode output selection branch. One ends of the resistor R11, the resistor R51 and the resistor R28 are connected with a U pin of the photocell chip U1, and the other ends of the resistors are respectively connected with the corresponding triode output selection branches; one ends of the resistor R16, the resistor R52 and the resistor R32 are connected with a V pin of the photocell chip U1, and the other ends of the resistors are respectively connected with the corresponding triode output selection branches; one end of each of the resistor R50, the resistor R53 and the resistor R54 is connected with the W pin of the photocell chip U1, and the other end of each of the resistors R50, the resistor R53 and the resistor R54 is connected with the corresponding triode output selection branch.

The three phase sequence selection branches are respectively connected with the three triode output selection branches IN A one-to-one correspondence manner, and the output ends of the three triode output selection branches are respectively connected with the input ends IN-A, IN-B and IN-C of the differential drive chip U3 IN A one-to-one correspondence manner.

Furthermore, each triode output selection branch comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a triode; the other end of the third resistor is connected with the U branch circuit, the V branch circuit and the W branch circuit respectively, the other ends of the second resistor and the fourth resistor are connected with the base electrode of the triode respectively, one end of the fifth resistor is connected with the 5V power supply, the other end of the fifth resistor is connected with the collector electrode of the triode and the input end of the corresponding differential driving chip U3 respectively, one end of the sixth resistor is connected with the base electrode of the triode, and the other end of the sixth resistor and the emitter electrode of the triode are grounded. The resistance values of the first resistor, the third resistor and the fifth resistor are 4.7K, and the resistance values of the second resistor, the fourth resistor and the sixth resistor are 20K. Optionally, the triode is selected to be an NPN type triode with the model number of 2SD 596.

Still referring to fig. 1, the first triode output selection branch comprises a resistor R8, a resistor R9, a resistor R14, a resistor R15, and a resistor R6, the circuit comprises A resistor R12 and A triode Q1, wherein A resistor R8 is connected with A resistor R9 IN series, A resistor R14 is connected with A resistor R15 IN series, the other end of A resistor R8 is connected with A PA/U sub-branch, A PB/V sub-branch and A PZ/W sub-branch IN A first phase sequence selection branch respectively, the other end of the resistor R24 is connected with A U sub-branch, A V sub-branch and A W sub-branch IN the first phase sequence selection branch respectively, the other ends of the resistor R9 and A resistor R15 are connected with the base of the triode Q1 respectively, one end of the resistor R6 is connected with A5V power supply, the other end of the resistor R6 is connected with the collector of the triode Q1 and the input end IN-A of the differential driving chip U3 respectively, one end of the resistor R12 is connected with the base of the triode Q1, and the other end of the emitter of the triode Q1 are both grounded.

The second triode output selection branch comprises a resistor R19, a resistor R20, a resistor R23, a resistor R24, a resistor R17, a resistor R22 and a triode Q2, the resistor R19 is connected with the resistor R20 IN series, the resistor R23 is connected with the resistor R24 IN series, the other end of the resistor R19 is connected with the PA/U sub-branch, the PB/V sub-branch and the PZ/W sub-branch IN the second phase sequence selection branch respectively, the other end of the resistor R24 is connected with the U sub-branch, the V sub-branch and the W sub-branch IN the second phase sequence selection branch respectively, the other ends of the resistor R20 and the resistor R24 are connected with the base of the triode Q2 respectively, one end of the resistor R17 is connected with a 5V power supply, the other end of the resistor R22 is connected with the collector of the triode Q2 and the input end IN-B of the differential drive chip U3, one end of the resistor R22 is connected with the base of the triode Q2, and the emitter of the triode Q2 is grounded.

The third triode output selection branch comprises a resistor R26, a resistor R27, a resistor R30, a resistor R31 and a resistor R25, the circuit comprises a resistor R29 and a triode Q3, wherein a resistor R26 is connected with the resistor R27 IN series, a resistor R30 is connected with a resistor R31 IN series, the other end of a resistor R26 is connected with a PA/U sub-branch, a PB/V sub-branch and a PZ/W sub-branch IN a third phase sequence selection branch respectively, the other end of the resistor R24 is connected with a U sub-branch, a V sub-branch and a W sub-branch IN a first three phase sequence selection branch respectively, the other ends of the resistor R27 and a resistor R31 are connected with the base of the triode Q3 respectively, one end of the resistor R25 is connected with a 5V power supply, the other end of the resistor R25 is connected with the collector of the triode Q3 and the input end IN-C of the differential driving chip U3 respectively, one end of the resistor R29 is connected with the base of the triode Q3, and the other end of the emitter of the triode Q3 are grounded.

Referring to fig. 1 and 2, an EN pin (i.e., pin 12) of the differential driver chip U3 is connected to A pin P3.3 of the main controller chip U2, and A pin P1.1 and A pin P1.2 of the main controller chip U2 are respectively connected to A triode output selection branch corresponding to the input terminal IN-A, that is, the pin P1.1 is connected between the resistor R8 and the resistor R9, and the pin P1.2 is connected between the resistor R14 and the resistor R15; a pin P1.3 and a pin P1.4 of the main control chip U2 are respectively connected with the triode output selection branch corresponding to the input end IN-B, namely, the pin P1.3 is connected between the resistor R19 and the resistor R20, and the pin P1.4 is connected between the resistor R23 and the resistor R24; the pin P1.0 and the pin P1.5 of the main control chip U2 are respectively connected to the transistor output selection branch corresponding to the input terminal IN-C, that is, the pin P1.0 is connected between the resistor R26 and the resistor R27, and the pin P1.5 is connected between the resistor R30 and the resistor R31.

The VCC pin of the differential driver chip U3 is connected to the 5V power supply, one end of the resistor R33 and one end of the capacitor C5, the other end of the resistor R33 is connected to the EN pin (i.e., pin 12), and the other end of the capacitor C5 is grounded. The resistance of the resistor R33 is 4.7K, and the capacitance of the capacitor C5 is 0.1 uF. The other EN pin (i.e., pin 4) of the differential driver chip U3 is grounded.

The VCC pin of the main control chip U2 is connected with the 5V power supply and one end of the capacitor C2, and the other end of the capacitor C2 and the GND pin of the main control chip U2 are both grounded. The capacitance value of the capacitor C2 is 0.1 uF. The P3.0/RXD pin and the P3.1/TXD pin of the main control chip U2 are correspondingly connected with the 1 pin and the 2 pin of the Header 3P1 of the pin connector, and the 3 pin of the Header 3P1 of the pin connector and the EP pin of the main control chip U2 are grounded.

Referring to fig. 3, the SEL pin of the photocell chip U1 is connected to one end of a resistor R2 and one end of a resistor R4, respectively, the T1 pin is connected to one end of a resistor R3 and one end of a resistor R5, respectively, the other ends of a resistor R2 and a resistor R3 are connected to a 5V power supply, and the other ends of a resistor R4 and a resistor R5 are connected to AGND; the LED pin is connected with AGND through a light-emitting diode D1 and a resistor R1; the VCC pin is connected with a 5V power supply and one end of a capacitor C7, and the other end of the capacitor C7 is connected with the GND pin, the pins 25 to 32 and the pins 9 to 16 and is connected with the AGND.

The IO port of the main control chip U2 is set to be in an open collector mode, after the encoder circuit is powered on and reaches a threshold voltage Va, the main control chip U2 firstly maintains a section of high-impedance time of Ta, then U, V, W three signals are generated through the phase sequence selection circuit, the three triode output selection branch circuit and the differential drive chip U3, and after U, V, W three signals maintain the time of Tb, A, B, Z signals are finally output to the servo motor driver.

The IO port of U2 sets up to the open-circuit mode of collecting electrode, can pull down the voltage of ABZ or UVW looks at the low level, be the high impedance mode at the high level, do not influence the output of ABZ or UVW signal, can draw through calculating and be 0V at triode Q1, Q2, the base voltage low level of Q3, be 20/(4.7+20+20) × 5 is 2.237136465324385V at the high level, satisfy the triode condition of turning on, Ta, the delay time accessible main control chip U2 delay calculation of Tb, it is more accurate, anti-jamming.

After the power-on of the wire-saving encoder circuit reaches the threshold voltage Va, the high-impedance (or high-level) time of a section of Ta is maintained, then U, V, W three-path signals are generated, and after the time of Tb is maintained, A, B, Z signals are finally output, so that U, V, W and A, B, Z share the transmission cable, three pairs of (U +/U-, V +/V-, W +/W-) transmission cables can be saved, the transmission cable can be saved, the wiring operation is simplified, and the cost is reduced.

Optionally, the photovoltaic cell chip U1 in the present invention is CL 26130.

Optionally, the main control chip U2 in the present invention is STC8G1K 08.

Optionally, the differential driver chip U3 in the present invention is AM26LS 31.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A novel wire-saving encoder circuit is characterized by comprising a photocell chip U1, a phase sequence selection circuit and an output selection circuit, wherein the output selection circuit comprises a main control chip U2, a differential drive chip U3 and three triode output selection branches with the same structure;

2. The novel wire-saving encoder circuit according to claim 1, wherein each of the triode output selection branches comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a triode;

the differential driving circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a power supply and a triode, wherein the first resistor is connected with the second resistor in series, the third resistor is connected with the fourth resistor in series, the other end of the first resistor is respectively connected with a PA/U sub-branch, a PB/V sub-branch and a PZ/W sub-branch, the other end of the third resistor is respectively connected with a U sub-branch, a V sub-branch and a W sub-branch, the other ends of the second resistor and the fourth resistor are respectively connected with a base electrode of the triode, one end of the fifth resistor is connected with the 5V power supply, the other end of the fifth resistor is respectively connected with a collector electrode of the triode and the corresponding input end of a differential driving chip U3, one end of the sixth resistor is connected with the base electrode of the triode, and the other end of the emitter electrode of the triode are both grounded.

3. The novel wire-saving encoder circuit according to claim 2, wherein the transistor is 2SD 596.

4. The novel wire-saving encoder circuit as claimed in claim 1, wherein the photocell chip U1 is CL 26130.

5. The novel wire-saving encoder circuit as claimed in claim 1, wherein the main control chip U2 is STC8G1K 08.

6. The novel wire-saving encoder circuit as claimed in claim 1, wherein the differential driver chip U3 is AM26LS 31.