CN215954802U - Graphic signal generator - Google Patents

Abstract

The embodiment of the application discloses a graphic signal generator, which is used for increasing the use diversification of the graphic signal generator. The embodiment of the application comprises the following steps: the system comprises an FPGA main control board, a cell signal output transfer board, a module signal output transfer board, a cell signal power output interface, a cell signal data output interface, a module signal output interface, a trigger signal interface and a case shell; the FPGA main control board, the cell signal output rotating board and the module signal output rotating board are arranged in the case shell; the FPGA main control board is respectively coupled with the cell signal output transfer board, the module signal output transfer board, the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface; the chassis shell is provided with the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface.

Description

Graphic signal generator

Technical Field

The embodiment of the application relates to the field of display panel testing, in particular to a graphic signal generator.

Background

With the continuous development of information display technology, the display panel OLED basically replaces the conventional display panel LCD gradually by virtue of its advantages of self-luminescence, flexibility, wide viewing angle, fast response speed, simple manufacturing process, and the like, and is rapidly and deeply applied to various fields of modern society.

However, as the market demands higher and higher display quality of the display panel OLED, the appearance design requirements are more and more diversified, and the shipment volume and the appearance design requirements of electronic products such as mobile phones, tablet computers and the like are also higher and higher, for example: bang screen, water drop screen, curved screen, etc. Among them, there is a strong demand for a display panel having a curved surface with a large curvature, but due to the process level of the display panel OLED and the limitation of objective environmental factors, the display panel OLED may have various mura defects, and thus, the mura defect compensation technology before shipment is largely applied to the actual production of the display panel OLED. In the application process of the mura defect compensation technology, the main key links of the mura defect compensation technology are image capture and data processing of the display panel OLED, wherein shooting of the pixel brightness of the display panel OLED is an indispensable link and has a determining factor for the mura defect compensation quality. In the process of shooting the pixel brightness data of the display panel, firstly, a graphic signal generator is needed to perform screen dot operation on the display panel so that the display panel displays a corresponding gray scale picture, and then the shooting device shoots.

Currently, a pattern signal generator for generating a pattern signal includes a cell pattern signal generator and a module pattern signal generator, and only one of the cell pattern signal and the module pattern signal can be generated by an internal trigger signal. Because the pattern signal generator can not make the signal generator generate different pattern signals through different trigger signals, the use diversification of the pattern signal generator is reduced.

SUMMERY OF THE UTILITY MODEL

The embodiment of the present application provides a graphics signal generator, which includes:

the system comprises an FPGA main control board, a cell signal output transfer board, a module signal output transfer board, a cell signal power output interface, a cell signal data output interface, a module signal output interface, a trigger signal interface and a case shell;

the FPGA main control board is used for controlling the cell signal output rotating board and the module signal output rotating board to output a target graphic signal;

the FPGA main control board is respectively coupled with the cell signal output transfer board, the module signal output transfer board, the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface;

the chassis shell is provided with the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface, the cell signal power output interface, the cell signal data output interface and the module signal output interface are used for outputting the target graphic signal, and the trigger signal interface is used for receiving and transmitting a trigger signal.

Optionally, the FPGA master control board is provided with a trigger synchronization module, an internal trigger generation module, a trigger switching module, a power signal generation module, a data signal generation module, and a digital graphics signal generation module, so that the graphics signal generator generates multiple working modes.

Optionally, the graphic signal generator further comprises a power panel;

the power panel is arranged in the case shell;

the power panel is coupled with the FPGA main control panel and is used for providing power energy for the graphic signal generator.

Optionally, the graphics signal generator further includes an inter-board connector;

the power panel is coupled with the FPGA main control panel through the panel connector.

Optionally, the graphics signal generator further includes an external data storage module;

the external data storage module is arranged in the case shell;

the external data storage module is coupled with the FPGA main control board and is used for storing data, signals and instructions generated by the graphic signal generator in the operation process.

Optionally, the external data storage module is an external DDR chip.

Optionally, the external data storage module is an external SRAM chip.

Optionally, the graphics signal generator further comprises a communication interface;

the communication interface is arranged on the case shell;

the communication interface is coupled with the FPGA main control board and used for receiving instructions and data and transmitting the instructions and the data into the FPGA main control board.

Optionally, the graphic signal generator further comprises an upper computer;

the upper computer is connected with the communication interface and is used for transmitting instructions or data to the FPGA main control board through the communication interface.

Optionally, the graphics signal generator further includes a peripheral interface;

the peripheral interface is arranged on the case shell;

the peripheral interface is coupled with the FPGA main control board and used for outputting the instructions and data generated by the FPGA main control board.

According to the technical scheme, the embodiment of the application has the following advantages:

the system comprises an FPGA main control board, a cell signal output transfer board, a module signal output transfer board, a cell signal power output interface, a cell signal data output interface, a module signal output interface, a trigger signal interface and a case shell. An FPGA main control board, a cell signal output transfer board and a module signal output transfer board are arranged in the case shell, and the FPGA main control board is used for controlling the cell signal output transfer board and the module signal output transfer board to output target graphic signals. The power signal generation module, the data signal generation module and the digital graphic signal generation module are arranged on the FGPA main control board, and the signal output type required by the cell graphic signal generator can be realized through the power signal generation module and the data signal generation module. The power signal generation module and the digital graphic signal generation module can realize a video signal output function based on certain existing protocols (such as RGB, LVDS, MIPI and the like), namely, a signal output type meeting the requirements of the module graphic signal generator can be generated, namely, the FPGA main control board can generate various graphic signals, and the generated graphic signals are output through the cell signal power output interface, the cell signal data output interface and the module signal output interface. The mode enables the graphic signal generator to enable the signal generator to generate different graphic signals through different trigger signals, and the use diversification of the graphic signal generator is increased.

Drawings

FIG. 1 is a schematic diagram of an embodiment of a graphics signal generator according to the present application;

FIG. 2 is a schematic structural diagram of another embodiment of a graphics signal generator according to the present application.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application discloses a graphic signal generator, which is used for increasing the use diversification of the graphic signal generator.

The FPGA chip is a digital integrated circuit chip, which is called Field Programmable Gate Array in English and called Field Programmable Gate Array in Chinese. An FPGA chip is one of the physical implementations of digital circuits. Compared with another important implementation mode of a digital Circuit, an ASIC (Application Specific Integrated Circuit) chip, an important feature of the FPGA chip is its programmable property, that is, a user can specify the FPGA chip to implement a Specific digital Circuit through a program.

Referring to fig. 1, an embodiment of the present application provides a graphics signal generator, including:

1-a power panel; 2-FPGA main control board; 3-cell signal output transfer board; 4-module signal output transfer board; 5-cell signal power supply output interface; 6-cell signal data output interface; 7-module signal output interface; 8-a trigger signal interface; 9-board-to-board connectors; 10-case shell.

The system comprises an FPGA main control board, a cell signal output transfer board, a module signal output transfer board, a cell signal power output interface, a cell signal data output interface, a module signal output interface, a trigger signal interface and a case shell;

the FPGA main control board is used for controlling the cell signal output rotating board and the module signal output rotating board to output a target graphic signal;

the FPGA main control board is respectively coupled with the cell signal output transfer board, the module signal output transfer board, the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface;

the chassis shell is provided with the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface, the cell signal power output interface, the cell signal data output interface and the module signal output interface are used for outputting the target graphic signal, and the trigger signal interface is used for receiving and transmitting a trigger signal.

When the pattern signal generator is triggered by using an external trigger mode or a mixed mode, a trigger signal is connected to the trigger signal interface 8, and when the pattern signal generator is triggered by using an internal trigger mode, the trigger signal interface 8 is suspended.

When the graphic signal generator uses the cell signal output mode, only the interfaces of the cell signal power output interface 5 and the cell signal data output interface 6 are used, wherein the interface of the cell signal power output interface 5 provides power output, and the interface of the cell signal data output interface 6 provides data output.

When the graphic signal generator uses the module signal output mode, only the cell signal power output interface 5 and the module signal output interface 7 are used for outputting, wherein the cell signal power output interface 5 provides power output, and the module signal output interface 7 provides image signal output based on a specific protocol.

When the pattern signal generator uses a mixed signal output mode, the cell signal power output interface 5 and the module signal output interface 7 are mainly used for outputting power and pattern signals based on a protocol, and the cell signal data output interface 6 is matched with and outputs required data signals.

The graphic signal generator also comprises a communication interface, a peripheral interface, an upper computer, an external data storage module and other mechanisms.

The external data storage module is used for storing data, signals and instructions generated by the graphic signal generator in the operation process. Specifically, the external data storage module may be an external DDR chip and an external SRAM chip.

And the upper computer is used for transmitting instructions or data to the FPGA main control board through the communication interface.

And the peripheral interface is used for outputting the instructions and the data generated by the FPGA main control board.

In this embodiment, the FPGA main control board, the cell signal output conversion board, the module signal output conversion board, the cell signal power output interface, the cell signal data output interface, the module signal output interface, the trigger signal interface, and the chassis housing. An FPGA main control board, a cell signal output transfer board and a module signal output transfer board are arranged in the case shell, and the FPGA main control board is used for controlling the cell signal output transfer board and the module signal output transfer board to output target graphic signals. The power signal generation module, the data signal generation module and the digital graphic signal generation module are arranged on the FGPA main control board, and the signal output type required by the cell graphic signal generator can be realized through the power signal generation module and the data signal generation module. The power signal generation module and the digital graphic signal generation module can realize a video signal output function based on certain existing protocols (such as RGB, LVDS, MIPI and the like), namely, a signal output type meeting the requirements of the module graphic signal generator can be generated, namely, the FPGA main control board can generate various graphic signals, and the generated graphic signals are output through the cell signal power output interface, the cell signal data output interface and the module signal output interface. The mode enables the graphic signal generator to enable the signal generator to generate different graphic signals through different trigger signals, and the use diversification of the graphic signal generator is increased.

The structure of the graphic signal generator and the operation of the graphic signal generator are described above, and the function of the FPGA main control board of the graphic signal generator is described below:

referring to fig. 2, an embodiment of the present application provides a graphics signal generator, including:

the system comprises a trigger synchronization module 11, an internal trigger generation module 12, a trigger switching module 13, a power signal generation module 14, a data signal generation module 15 and a digital graphic signal generation module 16;

the trigger synchronization module 11, the internal trigger generation module 12, the trigger switching module 13, the power signal generation module 14, the data signal generation module 15 and the digital graphics signal generation module 16 are arranged on an FPGA chip 17, and the FPGA chip 17 is used for receiving instructions, signals and data and controlling each module;

the trigger switching module 13 is respectively connected to the trigger synchronization module 11, the internal trigger generation module 12, the power signal generation module 14, the data signal generation module 15, and the digital graphics signal generation module 16, the trigger synchronization module 11 is configured to receive an external trigger signal, the internal trigger generation module 12 is configured to generate an internal trigger signal, and the trigger switching module 13 is configured to control the power signal generation module 14, the data signal generation module 15, and the digital graphics signal generation module 16 to output a target graphics signal of a preset type when receiving the external trigger signal and/or the internal trigger signal.

In this embodiment, the FPGA chip 17 is provided with a trigger synchronization module 11, an internal trigger generation module 12, a trigger switching module 13, a power signal generation module 14, a data signal generation module 15, and a digital graphics signal generation module 16 by code compiling.

The various modules on the FPGA chip 17 are described below:

the trigger synchronization module 11 is configured to process an external trigger signal passing through a corresponding pin of the FPGA chip 17. The external trigger signal is a trigger signal sent externally, and can enable the FPGA chip 17 to output a pattern signal in a specific form. When the FPGA chip 17 determines that the current trigger mode is the external trigger mode, the trigger synchronization module 11 detects an external trigger signal entering the FPGA chip 17 through a specific pin of the FPGA chip 17, and performs corresponding synchronization and shaping output for a next-stage functional module to use, in this embodiment, the next-stage functional module of the trigger synchronization module 11 is the trigger switching module 13.

The trigger synchronization module 11 has various functions in addition to the above functions: a trigger judging function, a trigger waveform trimming function, a one-trigger to multi-trigger function, a trigger synchronizing function, etc., and is not limited herein. The following describes the function of the trigger synchronization module 11:

and triggering a detection function, wherein the function is mainly to trigger the synchronous module 11 to judge whether the level on the corresponding pin of the FPGA chip 17 generates sudden change, and if the level generates sudden change, the level is fed back to the FPGA chip 17 in time. Triggering a judgment function which eliminates some interference of peripheral circuits of the FPGA chip 17 by triggering the synchronization module 11. The trigger waveform trimming function is a function of the trigger synchronization module 11 to further perform trimming or reshaping (phase change, width adjustment) of the trigger waveform. The single-trigger to multi-trigger function can realize that one single trigger signal is changed into a plurality of even periodic trigger signals. The trigger synchronization function is a function of synchronizing a plurality of trigger signals to one signal output or outputting the signals while maintaining a set phase, in response to a plurality of external triggers.

The internal trigger generating module 12 is configured to independently generate an internal trigger signal, and perform corresponding synchronization and shaping output for use by a next-stage functional module, in this embodiment, the next-stage functional module of the trigger synchronizing module 11 is a trigger switching module 13.

The trigger switching module 13 is configured to set a subsequent output mode after receiving the trigger signals sent by the internal trigger generating module 12 and the trigger synchronizing module 11, and send a signal and an instruction to the back stage circuit, where in this embodiment, the back stage circuit includes a power signal generating module 14, a data signal generating module 15, and a digital graphics signal generating module 16.

The power signal generating module 14 and the digital graphics signal generating module 16 can implement a video signal output function based on some existing protocols (such as RGB, LVDS, MIPI, etc.), i.e., can generate a signal output type that meets the requirements of the modular graphics signal generator. The mode enables the graphic signal generator to enable the signal generator to generate different graphic signals through different trigger signals, and the use diversification of the graphic signal generator is increased.

Optionally, the graphics signal generator further comprises a communication interface 18;

the communication interface 18 is connected to the FPGA chip 17, and the communication interface 18 is configured to receive instructions and data and transmit the instructions and data to the FPGA chip 17.

Optionally, the graphic signal generator further includes an upper computer 19;

the upper computer 19 is connected with the communication interface 18, and the upper computer 19 is used for transmitting instructions or data to the FPGA chip 17 through the communication interface 18.

The upper computer 19 communicates with the graphic signal generator through the communication interface 18 to obtain the address of the connection device and establish connection. The upper computer 19 transmits an instruction to a module of the FPGA chip 17 through the communication interface 18, so that the FPGA chip 17 sets a working mode, wherein the working mode includes a trigger mode and an output mode. Further, the trigger mode includes an internal trigger mode, an external trigger mode and a hybrid trigger mode, and the output mode includes a cell signal output mode, a module signal mode and a hybrid mode.

Optionally, the graphics signal generator further comprises a peripheral interface 20;

the peripheral interface 20 is connected to the FPGA chip 17, and the peripheral interface 20 is configured to output the instruction and the data generated by the FPGA chip 17.

After the data and the trigger signal are prepared, the output function is started by using the instruction, and the corresponding pin of the display panel is connected to the peripheral interface 20 corresponding to the FPGA chip 17, so that the dot screen function of the display panel can be realized.

Optionally, the graphics signal generator further includes a data storage module 21;

the data storage module 21 is disposed on the FPGA chip 17, and the data storage module 21 is configured to store instructions, signals, and data generated in an operation process of the FPGA chip 17.

In addition, the data storage module 21 further includes an external DDR chip and/or an external SRAM chip.

Information such as signals, data, and pictures are stored in the data storage module 21. Furthermore, a corresponding register space is opened up inside the FPGA chip 17 for storing control instructions, signals and data, so as to achieve the requirements of high-speed and low-delay response output. The carrier of the data storage module 21 may be a resource space on the FPGA chip 17, which is called as the data storage module 21, or may be an external DDR chip and an external SRAM chip, which are called as the external data storage module 21, and the address spaces of the data storage module 21 are both mapped in the data storage module 21, so that the system can read and call at any time.

The operating mode of the FPGA chip 17 is described below:

when the operation mode is set to the hybrid output mode, the power signal generation module 14, the data signal generation module 15 and the digital graphics signal generation module 16 selectively cooperate with each other according to the actual configuration situation, so as to meet the requirement of outputting the required hybrid graphics signal.

The power signal generation module 14 may implement an instruction parsing function, a power waveform data reading function, a data stream generation function, a power voltage output calibration function, and a feedback adjustment function therein.

The data signal generating module 15 can internally realize a trigger response function, a data waveform data reading function, a data stream generating function, a data voltage output calibration function and a feedback regulation function.

The digital graphics signal generation module 16 has integrated within it instruction preload and execution logic, picture data access logic, peripheral interface 20 control logic, protocol timing generator logic, and a digital graphics generation engine.

After the working mode of the graphics signal generator is set, when a module graphics signal output or a mixed graphics signal output is generated, the instruction preloading and execution logic reads an instruction and a next instruction from a set address space, a digital graphics generation engine in the digital graphics signal generation module 16 is started, and a protocol time sequence generator is configured according to different protocols to generate time sequences such as corresponding line fields and the like. At the same time, the picture data storage logic reads the graphic data and parameters from the corresponding address space according to the address provided in the instruction, the graphic data and parameters are input to the digital graphic generation engine again in a data stream mode, the generated data is filled into the time sequence generation logic after being processed by the digital graphic generation engine, all signals required by the protocol are generated, and finally the signals are output through the peripheral interface 20 circuit.

When the operation mode of the FPGA chip 17 is set to the internal trigger mode, the internal trigger signal generation module generates a set trigger signal, and the upper computer 19 sets the signal phase, width, and other characteristics of the set trigger signal through the communication port.

Each module of the graphic signal generator is arranged in the FPGA chip 17 in a code editing mode, compared with other chips, the FPGA chip 17 can simultaneously acquire various trigger signals, and when a plurality of signals are simultaneously input into the FPGA chip 17 through different pins, the FPGA chip 17 can achieve parallel processing.

Secondly, the graph signal generator in the embodiment does not only rely on the internal trigger to realize the graph signal output, the trigger source can be flexibly configured by using the method and the signal generator, and a mixed trigger mode can be used in some special application occasions. The processing of the trigger is no longer purely responsive, but can be varied morphologically in phase and duration by commanding the triggering signal.

Meanwhile, the graphic signal generator in the embodiment can send out signals required by the cell and module graphic signal generators, and the function of independent output or mixed output of two modes can be realized through the flexibility of the FPGA chip 17, so that the blank of related industry tests is filled.

In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are used only for explaining relative positional relationships between the respective members or components, and do not particularly limit specific mounting orientations of the respective members or components.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "mounted," "disposed," "provided," "connected," and "connected" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In addition, the structures, the proportions, the sizes, and the like, which are illustrated in the accompanying drawings and described in the present application, are intended to be considered illustrative and not restrictive, and therefore, not limiting, since those skilled in the art will understand and read the present application, it is understood that any modifications of the structures, changes in the proportions, or adjustments in the sizes, which are not necessarily essential to the practice of the present application, are intended to be within the scope of the present disclosure without affecting the efficacy and attainment of the same.

Claims (10)

1. A graphics signal generator, comprising:

the system comprises an FPGA main control board, a cell signal output transfer board, a module signal output transfer board, a cell signal power output interface, a cell signal data output interface, a module signal output interface, a trigger signal interface and a case shell;

the FPGA main control board is used for controlling the cell signal output rotating board and the module signal output rotating board to output a target graphic signal;

the FPGA main control board is respectively coupled with the cell signal output transfer board, the module signal output transfer board, the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface;

the chassis shell is provided with the cell signal power output interface, the cell signal data output interface, the module signal output interface and the trigger signal interface, the cell signal power output interface, the cell signal data output interface and the module signal output interface are used for outputting the target graphic signal, and the trigger signal interface is used for receiving and transmitting a trigger signal.

2. The graphics signal generator of claim 1, wherein said FPGA master control board is configured with a trigger synchronization module, an internal trigger generation module, a trigger switching module, a power signal generation module, a data signal generation module, and a digital graphics signal generation module, such that said graphics signal generator generates multiple operating modes.

3. The graphics signal generator of claim 1, wherein said graphics signal generator further comprises a power strip;

the power panel is arranged in the case shell;

the power panel is coupled with the FPGA main control panel and is used for providing power energy for the graphic signal generator.

4. The graphics signal generator of claim 3, wherein the graphics signal generator further comprises an inter-board connector;

the power panel is coupled with the FPGA main control panel through the inter-board connector.

5. The graphics signal generator of any of claims 1 to 4, further comprising an external data storage module;

the external data storage module is arranged in the case shell;

the external data storage module is coupled with the FPGA main control board and is used for storing data, signals and instructions generated by the graphic signal generator in the operation process.

6. The graphics signal generator of claim 5 wherein said external data storage module is an external DDR chip.

7. The graphics signal generator of claim 5 wherein said external data storage module is an external SRAM chip.

8. The graphics signal generator of any of claims 1 to 4, further comprising a communication interface;

the communication interface is arranged on the case shell;

the communication interface is coupled with the FPGA main control board and used for receiving instructions and data and transmitting the instructions and the data into the FPGA main control board.

9. The graphics signal generator of claim 8, further comprising an upper computer;

the upper computer is connected with the communication interface and is used for transmitting instructions or data to the FPGA main control board through the communication interface.

10. The graphics signal generator of any of claims 1 to 4, further comprising a peripheral interface;

the peripheral interface is arranged on the case shell;

the peripheral interface is coupled with the FPGA main control board and used for outputting the instructions and data generated by the FPGA main control board.

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