CN215895421U - Display substrate and display device - Google Patents
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- CN215895421U CN215895421U CN202120663303.7U CN202120663303U CN215895421U CN 215895421 U CN215895421 U CN 215895421U CN 202120663303 U CN202120663303 U CN 202120663303U CN 215895421 U CN215895421 U CN 215895421U
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Abstract
The application relates to the technical field of display, discloses a display substrate and a display device, and aims to solve the problem that a TDDI display product is poor in display function. The display substrate includes: the substrate comprises a substrate base plate, a first conducting layer, a first insulating layer, a second conducting layer, a second insulating layer and a third conducting layer, wherein the first conducting layer, the first insulating layer, the second conducting layer, the second insulating layer and the third conducting layer are sequentially arranged on the substrate base plate; wherein: the first conductive layer includes a plurality of gate lines; the second conductive layer comprises a plurality of touch electrode routing lines; the orthographic projection of the touch electrode wiring on the substrate base plate and the orthographic projection of the grid line on the substrate base plate are arranged in a crossed mode; the second insulating layer is provided with a first through hole, and the third conducting layer is electrically connected with the touch electrode routing through the first through hole; the first via hole comprises an upper opening and a lower opening which are communicated with each other, the lower opening is close to the substrate base plate, and the upper opening is close to the third conducting layer; the orthographic projection of the lower opening on the substrate is not overlapped with the orthographic projection of the edge of the grid line on the substrate.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a display substrate and a display device.
Background
Touch and Display Driver Integration (TDDI) Display products are mostly characterized in that a Touch chip and a Display chip are integrated into a single chip, so as to realize a panel design with a slimmer appearance, brighter Display and a narrow frame. However, the display function of the existing TDDI products with small size is poor due to ESD at the client and market, ESD is a common and difficult-to-prevent defect affecting the picture quality, and this defect is progressive in many cases, and a lot of defects flow into the market, which seriously affects the picture quality and the brand image.
SUMMERY OF THE UTILITY MODEL
The application discloses a display substrate and a display device, and aims to solve the problem of poor display function of a TDDI display product.
In order to achieve the purpose, the application provides the following technical scheme:
a display substrate, comprising: the substrate comprises a substrate base plate, a first conducting layer, a first insulating layer, a second conducting layer, a second insulating layer and a third conducting layer, wherein the first conducting layer, the first insulating layer, the second conducting layer, the second insulating layer and the third conducting layer are sequentially arranged on the substrate base plate; wherein:
the first conductive layer includes a plurality of gate lines; the second conductive layer comprises a plurality of touch electrode routing lines; the orthographic projection of the touch electrode wiring on the substrate base plate and the orthographic projection of the grid line on the substrate base plate are arranged in a crossed mode;
the second insulating layer is provided with a first via hole, and the third conducting layer is electrically connected with the touch electrode routing through the first via hole;
the first via hole comprises an upper opening and a lower opening which are communicated with each other, the lower opening is close to the substrate base plate, and the upper opening is close to the third conducting layer; the orthographic projection of the lower opening on the substrate base plate is not overlapped with the orthographic projection of the edge of the grid line on the substrate base plate.
Optionally, the gate line includes a cross section, and an orthogonal projection of the cross section on the substrate intersects an orthogonal projection of the touch electrode trace on the substrate;
the orthographic projection of the edge of the cross section on the substrate base plate is arranged around the orthographic projection of the lower opening on the substrate base plate.
Optionally, in the extending direction of the touch electrode trace, the width of the cross section is greater than the width of the lower opening;
the orthographic projection of the lower opening on the substrate base plate is positioned in the orthographic projection of the cross section on the substrate base plate.
Optionally, an orthographic projection of the lower opening on the substrate base plate is located in an orthographic projection of the touch electrode trace on the substrate base plate.
Optionally, the touch electrode trace includes a boss and two segments of traces respectively located at two sides of the boss, and the width of the boss is greater than the width of the two segments of traces along an extending direction perpendicular to the touch electrode trace;
the orthographic projection of the lower opening on the substrate base plate is positioned in the orthographic projection of the boss on the substrate base plate.
Optionally, the crossing segment is a continuous whole-layer structure.
Optionally, in the extending direction of the touch electrode trace, the width of the cross section is smaller than the width of the boss.
Optionally, the cross section is provided with an avoidance opening; the orthographic projection of the lower opening on the substrate base plate is positioned in the orthographic projection of the avoiding opening on the substrate base plate.
Optionally, the avoidance opening is a closed opening.
Optionally, an orthographic projection of the boss on the substrate base plate is located in an orthographic projection of the avoidance opening on the substrate base plate.
Optionally, an orthographic projection of the lower opening on the substrate base plate is located on one side of an orthographic projection of the intersection section on the substrate base plate.
Optionally, an orthogonal projection of the edge of the intersection segment on the substrate base plate is located between an orthogonal projection of the edge of the upper opening on the substrate base plate and an orthogonal projection of the edge of the lower opening on the substrate base plate.
Optionally, an orthographic projection of the upper opening on the substrate base plate is located within an orthographic projection of the intersection section on the substrate base plate.
Optionally, the second conductive layer is a source-drain electrode layer, and further includes a data signal line, where the data signal line is in the same extension direction as the touch electrode trace;
the third conductive layer is a common electrode layer.
Optionally, the second insulating layer includes an inorganic passivation layer and an organic planarization layer; the organic planarization layer is positioned between the second conductive layer and the inorganic passivation layer;
the inorganic passivation layer is provided with a second through hole, the organic flat layer is provided with a third through hole, and the second through hole is communicated with the third through hole; the lower opening includes the second via and the third via.
Optionally, an orthographic projection of the second via hole on the substrate base plate is located in an orthographic projection of the third via hole on the substrate base plate.
Optionally, the material of the grid line comprises copper; the material of the touch electrode routing comprises copper.
A display device comprising a display substrate according to any one of the preceding claims.
Drawings
FIG. 1 is a schematic view of a portion of a display substrate in the related art;
FIG. 2 is a schematic view of a partial cross-sectional view of the substrate shown in FIG. 1 taken along the line A1-A2;
fig. 3 is a schematic partial structure diagram of a display substrate according to an embodiment of the present disclosure;
FIG. 4 is a schematic cross-sectional view of the substrate shown in FIG. 3 taken along the line B1-B2;
fig. 5 is a schematic partial structure diagram of a display substrate according to another embodiment of the present disclosure;
FIG. 6 is a schematic view of a partial cross-sectional view of the substrate shown in FIG. 5 taken along the direction C1-C2;
fig. 7 is a schematic partial structure diagram of a display substrate according to another embodiment of the present disclosure;
FIG. 8 is a schematic view of a partial cross-sectional view of the display substrate shown in FIG. 7 taken along the direction D1-D2;
fig. 9 is a schematic partial structure diagram of a display substrate according to another embodiment of the present disclosure;
FIG. 10 is a schematic view of a partial cross-sectional view of the substrate shown in FIG. 9 taken along the direction E1-E2;
fig. 11 is a schematic partial structure diagram of a display substrate according to another embodiment of the present disclosure;
fig. 12 is a schematic partial structure view of a display substrate according to another embodiment of the present disclosure;
fig. 13 is a schematic partial structure diagram of a display substrate according to another embodiment of the present disclosure.
Detailed Description
Specifically, referring to fig. 1 and fig. 2, in the TDDI display product in the related art, the touch electrode trace (Tx)4 and the data line (SD line) 7 are on the same layer and are arranged to cross the gate line 2 to form a sensing capacitor circuit, specifically, the Tx 4 is electrically connected to the common electrode layer 6 through the via hole 50 of the insulating layer 5, and in order to avoid affecting the aperture ratio of the display product, the via hole 50 is arranged at the intersection of the Tx 4 and the gate line 2. Static electricity is easy to accumulate in the etching process of the via hole 50, and static electricity discharge (ESD) is easy to occur due to the fact that the Tx 4 in the via hole 50 is an antistatic weak point at the climbing position of the edge of the grid line 2, so that the Tx 4 and the grid line 2 are short-circuited, and further line grids and/or cross striations are poor.
In view of the above research findings, the present application provides a design scheme of a display substrate to solve the problem of poor display function of TDDI display products due to ESD.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
An embodiment of the present application provides a display substrate, as shown in fig. 3 to 13, the display substrate includes: a substrate base plate 1, a first conductive layer, a first insulating layer 3, a second conductive layer, a second insulating layer 5 and a third conductive layer 6 which are arranged on the substrate base plate 1 in sequence; wherein:
the first conductive layer includes a plurality of gate lines 2; the second conductive layer comprises a plurality of touch electrode wires 4; the orthographic projection of the touch electrode wiring 4 on the substrate base plate 1 is crossed with the orthographic projection of the grid line 2 on the substrate base plate 1;
the second insulating layer 5 is provided with a first via hole 50, and the third conductive layer 6 is electrically connected with the touch electrode trace 4 through the first via hole 50;
the first via hole 50 includes an upper opening 501 and a lower opening 502 that are through to each other, the lower opening 502 is close to the substrate base plate 1, and the upper opening 501 is close to the third conductive layer 6; and the orthographic projection of the lower opening 502 on the substrate base plate 1 is not overlapped with the orthographic projection of the edge of the grid line 2 on the substrate base plate 1.
In the display substrate provided by the embodiment of the application, touch electrode wire 4 and gate line 2 are arranged in a crossing manner, a touch sensing capacitance circuit is formed, wherein touch electrode wire 4 is electrically connected with third conducting layer 6 through first via hole 50 to realize electric signal access, orthographic projection of lower opening 502 (opening near one side of substrate 1) of first via hole 50 is not overlapped with orthographic projection of edge of gate line 2, and further, no ladder or section difference caused by edge of gate line 2 exists in lower opening 502 of first via hole 50, therefore, electrostatic discharge is not easy to occur in first via hole 50, thereby occurrence of ESD at touch electrode connecting hole of TDDI product can be thoroughly improved, bad display caused by short circuit of touch electrode wire 4 and gate line 2 of TDDI product is effectively improved, and product yield is improved.
Specifically, in this embodiment of the application, the edge of the gate line refers to the edge of the gate line film layer pattern, and is not limited to the extending edges at two sides of the gate line, for example, if the gate line includes other patterns, the edge of the pattern also belongs to the edge of the gate line.
In a specific embodiment, as shown in fig. 3, fig. 5, fig. 7, fig. 9, fig. 11, fig. 12 and fig. 13, in the display substrate provided in the embodiment of the present application, the gate line 2 includes a cross section 20, and an orthogonal projection of the cross section 20 on the substrate intersects an orthogonal projection of the touch electrode trace 4 on the substrate.
Specifically, the orthographic projection of the edge of the cross section 20 on the substrate base plate is arranged around the orthographic projection of the lower opening 502 on the substrate base plate.
In the embodiment of the present application, the first via hole 50 is disposed at the intersection position of the gate line 2 and the touch electrode trace 4, the aperture opening ratio of the display substrate is not affected, and the edge orthographic projection of the cross section 20 of the gate line 2 surrounds the orthographic projection of the lower opening 502, that is, the edge of the gate line 2 avoids the position of the lower opening 502, and further, there is no step or section difference (refer to fig. 4 and the cross-sectional view of fig. 6) caused by the edge of the gate line 2 in the lower opening 502, and further, electrostatic discharge is not likely to occur in the lower opening 502, so that the occurrence of short circuit between the touch electrode trace 4 and the gate line 2 in the first via hole can be prevented, the display defect caused by ESD is thoroughly improved, and the product yield is improved.
In a specific embodiment, as shown in fig. 3, 5, 7, 9 and 11, an orthographic projection of the lower opening 502 on the substrate is located within an orthographic projection of the touch electrode trace 4 on the substrate.
For example, as shown in fig. 3, fig. 5, fig. 7, fig. 9 and fig. 11, the touch electrode trace 4 includes a boss 40 and two segments of traces respectively located on two sides of the boss 40, and along an extending direction perpendicular to the touch electrode trace 4, a width of the boss 40 is greater than widths of the two segments of traces; the orthographic projection of the lower opening 502 on the substrate base is located within the orthographic projection of the boss 40 on the substrate base.
Specifically, referring to fig. 4, 6, 8 and 10, the first via hole is used as an electrical connection hole between the third conductive layer 6 and the touch electrode trace 4, and needs to be disposed above the touch electrode trace 4, and an orthographic projection of a lower opening of the first via hole is disposed in the orthographic projection of the touch electrode trace 4, so that a connection yield of the third conductive layer 6 and the touch electrode trace 4 can be ensured. Referring to fig. 3, 5, 7, 9 and 11, a section of the touch electrode trace 4 at the position of the first via hole 50 is disposed to form a boss 40 with a larger width, and the orthographic projection of the lower opening 502 is disposed in the orthographic projection of the boss 40, so that the preparation process of the first via hole 50 can be simplified, the preparation yield of the first via hole 50 can be improved, and the connection yield of the third conductive layer 6 and the touch electrode trace 4 can be further improved.
In a specific embodiment, as shown in fig. 3, 5, 7 and 9, along the extending direction of the touch electrode trace 4, the width of the crossing segment 20 of the gate line 2 is greater than the width of the lower opening 502; the orthographic projection of the lower opening 502 on the substrate base is within the orthographic projection of the crossover section 20 on the substrate base.
For example, as shown in fig. 5, 7 and 9, the width of the crossing section 20 of the gate line 2 may be greater than the width of the gate line 2 of the left and right two sections connected thereto.
In addition to the above embodiment, in one embodiment, as shown in fig. 3, the crossing segment 20 of the gate line 2 is a continuous whole layer structure.
Specifically, as shown in fig. 3, 7 and 9, the cross section 20 is a continuous film layer, and along the extending direction of the touch electrode trace 4, the width of the film layer is greater than the width of the lower opening 502, and the edge of the film layer surrounds the lower opening 502, at this time, the film layer of the cross section 20 is equivalent to a platform, the entire lower opening 502 is located on the platform, there is no step or step difference in the lower opening 502 (refer to the cross-sectional views of fig. 4, 8 and 10), and then the electrostatic discharge is not easy to occur in the lower opening 502, so that the touch electrode trace 4 and the gate line 2 can be prevented from being short-circuited in the lower opening 502, the display defect caused by ESD is effectively improved, and the yield of the product is improved.
In addition, this configuration may increase the coupling capacitance of some touch electrode traces 4, but does not affect the characteristics of the capacitive circuit and the application of the touch function, and specifically, the design may be applied to a 10.3 inch and/or 10.1 inch copper trace product, for example.
For example, as shown in fig. 3, 7 and 9, the width of the crossing segment 20 of the gate line 2 may be smaller than the width of the bump 40 of the touch electrode trace 4 along the extending direction of the touch electrode trace 4.
Certainly, in practical applications, the width of the crossing section of the gate line may also be greater than the width of the boss of the touch electrode trace, and specifically, the width may be selected according to the requirement of the pixel aperture ratio and the process requirement.
In another embodiment, as shown in fig. 5, the crossing section 20 of the grid line 2 is provided with an avoidance opening 200; the orthographic projection of the lower opening 502 on the substrate base is located within the orthographic projection of the avoidance opening 200 on the substrate base.
Specifically, as shown in fig. 5, a pattern avoiding the opening 200 is provided in the film layer of the cross section 20, and then the film layer of the cross section 20 has both an outer edge and an inner edge (edge avoiding the opening 200), because the orthographic projection of the lower opening 502 is located in the orthographic projection avoiding the opening 200, the outer edge and the inner edge of the cross section 20 are both arranged around the lower opening 502, at this time, no step or step difference (refer to the cross-sectional view of fig. 6) is formed in the lower opening 502, and then electrostatic discharge is not easy to occur in the lower opening 502, so that the touch electrode trace 4 and the gate line 2 can be prevented from being short-circuited in the lower opening 502, display defects caused by ESD are effectively improved, and the product yield is improved.
Illustratively, as shown in FIG. 5, the bypass opening 200 is a closed opening. At this time, the outer edge and the inner edge of the cross section 20 are closed loops and surround the lower opening 502. At this time, the cross section 20 is divided into two branches a and B by the lower opening 502, and when a defect occurs in one branch, the other branch can maintain normal operation, so as to ensure the yield of products; for example, when ESD occurs at the overlapping position of the branch a of the cross section 20 and the touch electrode trace 4, the branch a can be cut off to eliminate the defect, and at this time, the branch B of the cross section 20 can maintain normal operation without affecting normal display.
Illustratively, the widths of the branch a and the branch B are smaller than the widths of two gate line traces connected to the left and right of the cross section 20. In this way, the influence of the cross segments 20 on the aperture ratio of the display substrate can be minimized.
Of course, the avoiding opening can also be a semi-closed opening similar to an inwards concave notch, and can be designed according to specific requirements in practical application.
Illustratively, as shown in fig. 5, an orthogonal projection of the projection 40 of the touch electrode trace 4 on the substrate base plate is located within an orthogonal projection of the avoidance opening 200 on the substrate base plate. At this time, the orthographic projections of the two branches a and B of the cross section 20 are not overlapped with the orthographic projection of the boss 40 of the touch electrode trace 4, so that the risk of short circuit between the touch electrode trace 4 and the grid line 2 can be reduced, and the yield of the touch circuit is ensured.
In a specific embodiment, the sizes of the upper and lower openings of the first via may be uniform or non-uniform.
Illustratively, as shown in fig. 9 and 10, the size of the upper opening 501 of the first via 50 may be equal to the size of the lower opening 502, and an orthogonal projection of the upper opening 501 on the substrate base 1 coincides with an orthogonal projection of the lower opening 502 on the substrate base 1.
Alternatively, as shown in fig. 3, 4, 7 and 8, the size of the upper opening 501 may be larger than the size of the lower opening 502, and the orthographic projection of the lower opening 502 on the substrate base 1 is located within the orthographic projection of the upper opening 501 on the substrate base 1.
Alternatively, the size of the upper opening may be smaller than that of the lower opening, and an orthogonal projection of the upper opening on the substrate base plate is located within an orthogonal projection of the lower opening on the substrate base plate.
In a specific embodiment, the orthographic projection of the upper opening 501 on the substrate base plate 1 can be located within the orthographic projection of the cross section 20 on the substrate base plate 1. For example, as shown in fig. 9 and 10, an orthogonal projection of the upper opening 501 on the substrate base 1 coincides with an orthogonal projection of the lower opening 502 on the substrate base 1, both of which are located within an orthogonal projection of the cross section 20 on the substrate base 1.
In another specific embodiment, as shown in fig. 7 and 8, an orthogonal projection of the edge of the cross section 20 on the substrate base plate 1 is located between an orthogonal projection of the edge of the upper opening 501 on the substrate base plate 1 and an orthogonal projection of the edge of the lower opening 502 on the substrate base plate 1. In other words, the edge of the cross section 20 surrounds the edge of the lower opening 502, and the edge of the upper opening 501 surrounds the edge of the cross section 20.
In a specific embodiment, as shown in fig. 11, 12 and 13, the orthographic projection of the lower opening 502 of the first via 50 on the substrate base is located on one side of the orthographic projection of the cross section 20 on the substrate base.
In other words, the orthographic projection of the whole cross section 20 bypasses the orthographic projection of the lower opening 502 of the first via hole 50, so that the step or the step difference formed in the lower opening 502 by the edge of the cross section 20 can be avoided, the ESD in the lower opening 502 can be prevented, the poor display caused by the ESD can be effectively improved, and the product yield can be improved.
For example, as shown in fig. 11, 12 and 13, the width of the crossing segment 20 of the gate line 2 is smaller than the width of the lower opening 502 along the extending direction of the touch electrode trace 4.
For example, as shown in fig. 11, the width of the crossing segment 20 of the gate line 2 may be substantially the same as the width of the gate line of the left and right segments connected thereto, and the edge of the crossing segment 20 is disposed around the lower opening 502.
Illustratively, as shown in fig. 12 and 13, the display substrate provided by the embodiment of the present application further includes a Thin Film Transistor (TFT)8, and a gate electrode 81 of the TFT 8 is connected to the gate line 2. Specifically, as shown in fig. 12, the cross section 20 may be located on a side of the first via 20 close to the TFT 8, so that the wiring may be concentrated, and the influence on the aperture ratio may be reduced; alternatively, as shown in fig. 13, the cross section 20 may be located on a side of the first via 20 away from the TFT 8, so that the wiring may be dispersed to avoid interference between the cross section 20 and the TFT 8, such as coupling capacitance and ESD.
Certainly, in the embodiment of the present application, the sizes, the orthogonal projection positions, and other designs of the cross sections of the bosses and the gate lines of the touch electrode traces are not limited to the above embodiment, and in practical applications, the sizes, the orthogonal projection positions, and the like can be adjusted according to requirements.
In a specific embodiment, as shown in fig. 3, 7 and 9, the second conductive layer is a source/drain electrode layer, and the display substrate further includes a data signal line 7, where the extending direction of the data signal line 7 is the same as the extending direction of the touch electrode trace 4.
Illustratively, as shown in fig. 4, 6, 8 and 10, the third conductive layer 6 is a common electrode layer.
Exemplarily, as shown in fig. 4, 6, 8 and 10, the second insulating layer 5 includes an inorganic passivation layer 52 and an organic planarization layer 51; the organic planarization layer 51 is located between the second conductive layer and the inorganic passivation layer 52.
Illustratively, as shown in fig. 4, 6, 8 and 10, the inorganic passivation layer 52 is provided with a second via hole, the organic planarization layer 51 is provided with a third via hole, and the second via hole and the third via hole are communicated; the first via 50 includes a second via and a third via. In other words, the third conductive layer 6 is electrically connected to the touch electrode trace 4 through the second via and the third via.
Illustratively, the orthographic projection of the second via on the substrate base is within the orthographic projection of the third via on the substrate base.
In a specific embodiment, in the display substrate provided by the present application, the gate line and the touch electrode trace are made of a metal material. Illustratively, the material of the gate line may include copper; the material of the touch electrode trace may also include copper.
In addition, the embodiment of the application also provides a display device, and the display device comprises the display substrate of any one of the above.
The Display device provided by the embodiment of the application adopts a Touch and Display Driver Integration (TDDI) design, is thin in appearance, bright in Display and narrow in frame, and is not easy to generate ESD (electro-static discharge), so that poor Display caused by short circuit of Touch electrode wiring and grid lines can be effectively improved, and the product yield is improved.
Specifically, the display device provided by the embodiment of the application can be applied to devices such as mobile phones, tablet computers, displays and the like.
It should be noted that, in some embodiments of the present disclosure, the display substrate and the display device may further include other structures, which may be determined according to practical needs, and the embodiments of the present disclosure are not limited thereto. In addition, the embodiments of the present disclosure are merely examples of specific embodiments, and the present invention is not limited to the embodiments.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (18)
1. A display substrate, comprising: the substrate comprises a substrate base plate, a first conducting layer, a first insulating layer, a second conducting layer, a second insulating layer and a third conducting layer, wherein the first conducting layer, the first insulating layer, the second conducting layer, the second insulating layer and the third conducting layer are sequentially arranged on the substrate base plate; wherein:
the first conductive layer includes a plurality of gate lines; the second conductive layer comprises a plurality of touch electrode routing lines; the orthographic projection of the touch electrode wiring on the substrate base plate and the orthographic projection of the grid line on the substrate base plate are arranged in a crossed mode;
the second insulating layer is provided with a first via hole, and the third conducting layer is electrically connected with the touch electrode routing through the first via hole;
the first via hole comprises an upper opening and a lower opening which are communicated with each other, the lower opening is close to the substrate base plate, and the upper opening is close to the third conducting layer; the orthographic projection of the lower opening on the substrate base plate is not overlapped with the orthographic projection of the edge of the grid line on the substrate base plate.
2. The display substrate of claim 1, wherein the gate line comprises a cross section, an orthographic projection of the cross section on the substrate intersects with an orthographic projection of the touch electrode trace on the substrate;
the orthographic projection of the edge of the cross section on the substrate base plate is arranged around the orthographic projection of the lower opening on the substrate base plate.
3. The display substrate according to claim 2, wherein the width of the cross section is greater than the width of the lower opening along the extending direction of the touch electrode trace;
the orthographic projection of the lower opening on the substrate base plate is positioned in the orthographic projection of the cross section on the substrate base plate.
4. The display substrate of claim 3, wherein an orthographic projection of the lower opening on the substrate is within an orthographic projection of the touch electrode trace on the substrate.
5. The display substrate according to claim 4, wherein the touch electrode trace comprises a boss and two segments of traces respectively located at two sides of the boss, and the width of the boss is greater than the width of the two segments of traces along an extending direction perpendicular to the touch electrode trace;
the orthographic projection of the lower opening on the substrate base plate is positioned in the orthographic projection of the boss on the substrate base plate.
6. The display substrate of claim 5, wherein the intersecting segments are a continuous, unitary layer structure.
7. The display substrate of claim 6, wherein the width of the cross section is smaller than the width of the projection along the extending direction of the touch electrode trace.
8. The display substrate of claim 5, wherein the cross-segments are provided with relief openings; the orthographic projection of the lower opening on the substrate base plate is positioned in the orthographic projection of the avoiding opening on the substrate base plate.
9. The display substrate of claim 8, wherein the relief opening is a closed opening.
10. The display substrate of claim 8, wherein an orthographic projection of the boss on the substrate is within an orthographic projection of the relief opening on the substrate.
11. The display substrate of claim 2,
the orthographic projection of the lower opening on the substrate base plate is positioned on one side of the orthographic projection of the cross section on the substrate base plate.
12. The display substrate of claim 2, wherein an orthographic projection of the edge of the intersection segment on the substrate is located between an orthographic projection of the edge of the upper opening on the substrate and an orthographic projection of the edge of the lower opening on the substrate.
13. The display substrate of claim 2, wherein an orthographic projection of the upper opening on the substrate is located within an orthographic projection of the intersection segment on the substrate.
14. The display substrate of any one of claims 1-13,
the second conducting layer is a source drain electrode layer and further comprises a data signal line, and the extending direction of the data signal line is consistent with the extending direction of the touch electrode wiring;
the third conductive layer is a common electrode layer.
15. The display substrate of claim 14, wherein the second insulating layer comprises an inorganic passivation layer and an organic planarization layer; the organic planarization layer is positioned between the second conductive layer and the inorganic passivation layer;
the inorganic passivation layer is provided with a second through hole, the organic flat layer is provided with a third through hole, and the second through hole is communicated with the third through hole; the first via includes the second via and the third via.
16. The display substrate of claim 15, wherein an orthographic projection of the second via on the substrate is within an orthographic projection of the third via on the substrate.
17. The display substrate of claim 14, wherein the material of the gate line is copper; the touch electrode wiring is made of copper.
18. A display device comprising the display substrate according to any one of claims 1 to 17.
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| CN202120663303.7U CN215895421U (en) | 2021-03-31 | 2021-03-31 | Display substrate and display device |
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| CN202120663303.7U CN215895421U (en) | 2021-03-31 | 2021-03-31 | Display substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115145418A (en) * | 2021-03-31 | 2022-10-04 | 京东方科技集团股份有限公司 | Display substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115145418A (en) * | 2021-03-31 | 2022-10-04 | 京东方科技集团股份有限公司 | Display substrate and display device |
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