CN215871672U - Receiving circuit and test equipment of polymorphic type signal - Google Patents

Abstract

The utility model discloses a receiving circuit and test equipment for multi-type signals. The circuit comprises a switch switching module, a signal decoding module, an LVDS-to-CML module and a control module, wherein the input end of the switch switching module is used for receiving any one of MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS and multi-bit parallel signals, the input end of the signal decoding module is electrically connected with the output end of the switch switching module, the output end of the signal decoding module is electrically connected with the input end of the LVDS-to-CML module, the output end of the LVDS-to-CML module is electrically connected with the control module, the output end of the signal decoding module is also electrically connected with the control module, and the control module is also electrically connected with the switch switching module. The utility model has the advantages of universality, low cost and small volume, and can receive various types of signals.

Description

Receiving circuit and test equipment of polymorphic type signal

Technical Field

The utility model belongs to the technical field of photoelectric testing, and particularly relates to a receiving circuit and testing equipment for multiple types of signals.

Background

Along with the popularization of devices such as mobile phones and the like, camera modules are more and more applied to scenes such as consumption and industry, the resolution ratio of the camera modules is higher and higher, and the requirement on the input bandwidth of detection equipment is higher and higher. But the module manufacturer can produce the different terminal equipment of camera module adaptation of multiple different grade type signal simultaneously, so module manufacturer can purchase multiple different grade type signal receiver equipment and detect the module of judgement module good or bad under the prevailing circumstances. But purchasing different devices increases the deployment cost for the vendor.

SUMMERY OF THE UTILITY MODEL

In view of at least one of the drawbacks and needs of the prior art, the present invention provides a multi-type signal receiving circuit and a testing device, which are versatile, capable of receiving multiple types of signals, small in size, and low in cost.

In order to achieve the above object, according to a first aspect of the present invention, a multi-type signal receiving circuit is provided, including a switch switching module, a signal decoding module, an LVDS to CML module and a control module, where an input end of the switch switching module is configured to receive any one of MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS and multi-bit parallel signals, an input end of the signal decoding module is electrically connected to an output end of the switch switching module, an output end of the signal decoding module is electrically connected to an input end of the LVDS to CML module, an output end of the LVDS to CML module is electrically connected to the control module, an output end of the signal decoding module is further electrically connected to the control module, and the control module is further electrically connected to the switch switching module.

Furthermore, the signal decoding module comprises decoding circuits corresponding to the MIPI D-PHY, the MIPI C-PHY, the high-speed SPI, the LVDS and the multi-bit parallel signals respectively, and the switch switching module is controlled by the control module to conduct the output of the switch switching module with one of the decoding circuits.

Furthermore, the signal decoding module includes a high-speed differential signal decoding module, a high-speed three-wire three-level decoding module, a first high-speed comparator module and a second high-speed comparator module, the LVDS-to-CML module includes a first LVDS-to-CML module and a second LVDS-to-CML module, input ends of the high-speed differential signal decoding module and the first high-speed comparator module are electrically connected to a first set of output ends of the switch switching module, input ends of the high-speed three-wire three-level decoding module and the second high-speed comparator module are electrically connected to a second set of output ends of the switch switching module, an input end of the first LVDS-to-CML module is electrically connected to an output end of the high-speed differential signal decoding module, an input end of the second LVDS-to-CML module is electrically connected to an output end of the high-speed three-wire three-level decoding module, and an input end of the first high-speed comparator module is electrically connected to an output end of the high-speed three-wire level decoding module, And the output ends of the second high-speed comparator module, the first LVDS-to-CML module and the second LVDS-to-CML module are electrically connected with the control module.

Further, the high-speed differential signal decoding module includes a first LVDS buffer, and the first high-speed comparator module includes a first comparator and a second comparator.

Further, the first group of output terminals of the switch switching module includes a first pin, a second pin, and a third pin, one input terminal of the first LVDS buffer and one input terminal of the first comparator are both electrically connected to the first pin of the switch switching module, the other input terminal of the first LVDS buffer and one input terminal of the second comparator are both electrically connected to the second pin of the switch switching module, and the third pin of the switch switching module is grounded.

Further, the high-speed three-wire three-level decoding module comprises a second LVDS buffer, a third LVDS buffer and a fourth LVDS buffer, and the second high-speed comparator module comprises a third comparator, a fourth comparator and a fifth comparator.

Further, the first group of output terminals of the switch switching module includes a fourth pin, a fifth pin, and a sixth pin, an input terminal of the second LVDS buffer and an input terminal of the third comparator are both electrically connected to the fourth pin of the switch switching module, an input terminal of the third LVDS buffer and an input terminal of the fourth comparator are both electrically connected to the fifth pin of the switch switching module, and an input terminal of the fourth LVDS buffer and an input terminal of the fifth comparator are both electrically connected to the sixth pin of the switch switching module.

Furthermore, the multi-type signal receiving circuit also comprises a DAC module, wherein the DAC module is controlled by the control module and outputs reference voltage signals to the first high-speed comparator module and the second high-speed comparator module.

Further, the switch switching module includes ten single-input dual-output switches, the number of the high-speed differential signal decoding modules is five, the number of the high-speed three-wire three-level decoding modules is three, the number of the first high-speed comparator modules is five, and the number of the second high-speed comparator modules is three.

According to a second aspect of the present invention there is provided test apparatus comprising a multi-type signal receiving circuit according to any one of the above.

In general, compared with the prior art, the utility model has the following beneficial effects:

(1) the application provides a receiving circuit of multi-type signal, to five types of signals of MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS, many parallel signal totally, inputs signal decoding module through switch module, has the commonality, can receive multi-type signal to small, with low costs.

(2) The interface circuit can reduce the use of pins of the FPGA by finally converting the five signals into the CML level signal and the LVCMOS level signal, thereby avoiding the use of the high-specification FPGA and reducing the circuit cost.

(3) By multiplexing different circuit sub-modules in the circuit, the use amount of chips for receiving various signals in the past is reduced, and the circuit cost is reduced.

(4) The camera modules with various different signal types can be adapted to one test system, and the deployment cost of the test system is reduced.

Drawings

FIG. 1 is a schematic diagram of a multi-type signal receiving circuit according to an embodiment of the utility model;

FIG. 2 is a schematic diagram of a resistor network according to another embodiment of the present invention;

FIG. 3 is a schematic diagram of a switch switching module according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of a signal decoding module and a control module according to another embodiment of the utility model;

fig. 5 is a schematic diagram of a switch switching module according to another embodiment of the utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

The MIPI C-PHY signal is a signal having a physical layer protocol dedicated to video transmission, an HS level type is used for each frame of image data packet transmission, an LP level type is used for inter-frame idle period to save power consumption, and an HS type high-speed data packet signal of C-PHY is a three-level signal, which is transmitted with A, B, C signals, respectively.

The MIPI D-PHY signal is an image signal suitable for the application of the portable display equipment, the signal is composed of an LP signal and an HS signal through time-sharing transmission, the LP signal is a low-speed single-ended control signal, and the HS signal is a high-speed image data signal and is transmitted through a P signal and an N signal respectively.

The most representative of the multi-bit parallel signals is the 8-bit parallel signal.

As shown in fig. 1, a multi-type signal receiving circuit according to an embodiment of the present invention includes a switch switching module, a signal decoding module, an LVDS-to-CML module, and a control module, where an input end of the switch switching module is used to receive any one of MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS, and multi-bit parallel signals, an input end of the signal decoding module is electrically connected to an output end of the switch switching module, an output end of the signal decoding module is electrically connected to an input end of the LVDS-to-CML module, an output end of the LVDS-to-CML module is electrically connected to the control module, an output end of the signal decoding module is further electrically connected to the control module, and the control module is further electrically connected to the switch switching module.

Five types of signals including MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS and multi-bit parallel signals are controlled by the control module to switch channels by the switch switching module, and the signals are input into the signal decoding module from different channels to be decoded. The control module is used for decoding the signals of the LP signal of the MIPI D-PHY, the high-speed SPI of the MIPI C-PHY, the LVDS and the multi-bit parallel signals and then directly outputting the signals to the control module, and for decoding the HS signal of the MIPI D-PHY and the HS signal of the MIPI C-PHY into LVDS signals, the signals are converted into CML signals through the LVDS-to-CML module and then output the CML signals to the control module.

Further, the control module is an FPGA chip.

Furthermore, the signal decoding module includes decoding circuits corresponding to the MIPI D-PHY, the MIPI C-PHY, the high-speed SPI, the LVDS, and the multi-bit parallel signal, and the switch switching module is controlled by the control module to conduct an output of the switch switching module with one of the decoding circuits, that is, the control module controls the switch switching module to switch to the corresponding decoding circuit according to a type of the input signal. Decoding circuits for different types of signals may share portions according to their signal characteristics.

Five signals, namely MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS and multi-bit parallel signals, can be divided into three types according to the characteristics of the signals: (1) the C-PHY signal is a three-wire three-level signal and LP mode exists; (2) D-PHYs and LVDSs are two-wire differential signals and D-PHYs also have single ended LP mode (3) high speed SPI and multi-bit parallel signals and the LP modes of D-PHYs and C-PHYs are both single ended signals.

Since the FPGA chip can only receive differential signals of the CML signal type and single-ended signals of the LVCMOS type in order to achieve the highest bandwidth, the circuit needs to convert the above three types of signals into CML and LVCMOS signals.

Furthermore, the signal decoding module comprises a high-speed differential signal decoding module, a high-speed three-wire three-level decoding module, a first high-speed comparator module and a second high-speed comparator module, the LVDS-to-CML module comprises a first LVDS-to-CML module and a second LVDS-to-CML module, the input ends of the high-speed differential signal decoding module and the first high-speed comparator module are electrically connected with the first group of output ends of the switch switching module, the high-speed three-wire three-level decoding module, the input end of the second high-speed comparator module is electrically connected with the second group of output ends of the switch switching module, the input end of the first LVDS-to-CML module is electrically connected with the output end of the high-speed differential signal decoding module, the input end of the second LVDS-to-CML module is electrically connected with the output end of the high-speed three-wire three-level decoding module, and the output ends of the first high-speed comparator module, the second high-speed comparator module, the first LVDS-to-CML module and the second LVDS-to-CML module are electrically connected with the control module.

The high-speed differential signal decoding module is used for receiving the D-PHY signals and the LVDS signals. The high-speed three-wire three-level decoding module is used for receiving the C-PHY signal. The first high speed comparator block functions to isolate the LP signal in the D-PHY. The second high speed comparator block functions to isolate the LP signal in the C-PHY. The first and second high speed comparator modules are also for receiving a multi-bit parallel signal and an SPI signal.

When the D-PHY/LVDS is accessed, the control module controls the switch switching module to connect the input signal to the high-speed differential signal decoding module. When the SPI/multi-bit parallel signal module is connected, the control module controls the switch switching module to connect the input signal to the first high-speed comparator module and the second high-speed comparator module. When the C-PHY signal is accessed, the control module controls the switch switching module to connect the input signal to the high-speed three-wire three-level decoding module.

Furthermore, the multi-type signal receiving circuit also comprises a DAC module, wherein the DAC module is controlled by the control module and outputs reference voltage signals to the first high-speed comparator module and the second high-speed comparator module.

Further, the high-speed differential signal decoding module includes a first LVDS buffer, and the first high-speed comparator module includes a first comparator and a second comparator.

Further, the first group of output terminals of the switch switching module includes a first pin, a second pin and a third pin, one input terminal of the first LVDS buffer and one input terminal of the first comparator are electrically connected to the first pin of the switch switching module, the other input terminal of the first LVDS buffer and one input terminal of the second comparator are electrically connected to the second pin of the switch switching module, and the third pin of the switch switching module is grounded. The other input ends of the first comparator and the second comparator are electrically connected with the DAC module. The other input end of the first comparator and the other input end of the second comparator are connected with a reference voltage.

The first LVDS BUFFER may employ an existing LVDS BUFFER chip.

After the D-PHY signal enters the high-speed differential signal decoding module, the first LVDS buffer can separate the HS signal from the D-PHY signal and output the HS signal at an LVDS level, the first high-speed comparator module can separate the LP signal from the D-PHY signal and output the LP signal at an LVCMOS level, and optionally, the DAC output voltage contained in the high-speed comparator submodule is required to be set to be 0.6V at the moment, so that the HS and the LP can be accurately separated.

When the LVDS signal is input to the high-speed differential decoding submodule, the control module controls the reference voltage output by the DAC module to the first high-speed comparator module to be 0 at this time, and the first LVDS buffer directly outputs the input LVDS signal.

Further, the high-speed three-wire three-level decoding module comprises a second LVDS buffer, a third LVDS buffer and a fourth LVDS buffer, and the second high-speed comparator module comprises a third comparator, a fourth comparator and a fifth comparator.

Further, the first group of output ends of the switch switching module includes a fourth pin, a fifth pin and a sixth pin, one input end of the second LVDS buffer and one input end of the third comparator are both electrically connected to the fourth pin of the switch switching module, one input end of the third LVDS buffer and one input end of the fourth comparator are both electrically connected to the fifth pin of the switch switching module, and one input end of the fourth LVDS buffer and one input end of the fifth comparator are both electrically connected to the sixth pin of the switch switching module. The other input end of the third comparator, the other input end of the fourth comparator and the other input end of the fifth comparator are connected with the reference voltage signal. In particular, the other input terminals of the third, fourth and fifth comparators may be electrically connected with the DAC module.

The second LVDS buffer, the third LVDS buffer and the fourth LVDS buffer respectively obtain an A-B signal, a B-C signal and a C-A signal in a single-group three-wire three-level HS signal separation process. Alternatively, the reference voltage output by the DAC block to the second high-speed comparator block is now set to 0.45V, which enables the LP signal to be isolated from the ABC three lines.

Furthermore, the LVDS-to-CML module converts the high-speed LVDS signals into CML signal levels by adopting a resistance network, so that the high-speed transceiver of the FPGA can receive and process the high-speed signals. The resistor network, as shown in fig. 2, includes resistors R1 and R2 for converting LVDS signals from the LVDS BUFFER to CML signals.

Furthermore, the LVDS to CML module includes a first resistor network, an input end of the first resistor network is electrically connected to an output end of the first LVDS buffer, and an output end of the first resistor network is electrically connected to the control module.

Furthermore, the LVDS to CML module includes a second resistance network, a third resistance network, and a fourth resistance network, an input end of the second resistance network is electrically connected to an output end of the second LVDS buffer, an input end of the third resistance network is electrically connected to an output end of the third LVDS buffer, an input end of the fourth resistance network is electrically connected to an output end of the fourth LVDS buffer, and output ends of the first resistance network, the third resistance network, and the fourth resistance network are electrically connected to the control module.

As shown in fig. 3, the switch switching module includes a single-input dual-output switch A, B, C, the first group of outputs of the switch switching module are pins 1, 2, and 3, and the second group of outputs of the switch switching module are pins 4, 5, and 6.

As shown in fig. 4, the high-speed differential signal decoding module includes BUFFER1, the high-speed three-wire three-level decoding module includes BUFFER2, BUFFER3, BUFFER4 and 3 resistors R, the first high-speed comparator module includes a comparator 1 and a comparator 2, the second high-speed comparator module includes a comparator 3, a comparator 4 and a comparator 5, the first LVDS-to-CML module includes a resistor network 1, and the second LVDS-to-CML module includes a resistor network 2, a resistor network 3 and a resistor network 4. The control module adopts FPGA.

The input signals of BUFFER1 are MIPI D-PHY P signal and MIPI D-PHY N signal. The output signals HS P and HS N of the resistor network 1.

The input signals of the BUFFER2 are MIPI C-PHY A signals and MIPI C-PHY B signals. The output signals of the resistor network 2 are a-B P signal and a-B N signal.

Input signals of the BUFFER3 are MIPI C-PHY B signals and MIPI C-PHY C signals. The output signals of the resistor network 1 are a B-C P signal and a B-C N signal.

The input signals of the BUFFER4 are MIPI C-PHY C signal and MIPI C-PHY A signal. The output signals of the resistor network 1 are a C-A P signal and a C-A N signal.

The input signals of the comparator 1 are MIPI D-PHY P signals and DAC reference voltage signals, and the output signals are LP P/single-ended signals.

The input signals of the comparator 2 are MIPI D-PHY N signals and DAC reference voltage signals, and the output signals are LP N/single-ended signals.

The input signals of the comparator 3 are MIPI C-PHY A signals and DAC reference voltage signals, and the output signals are LP A signals.

The input signals of the comparator 4 are MIPI C-PHY B signals and DAC reference voltage signals, and the output signals are LP B signals.

The input signals of the comparator 5 are MIPI C-PHY C signals and DAC reference voltage signals, and the output signals are LP C signals.

In another embodiment of the present invention, the switch switching module includes ten single-input dual-output switches, five high-speed differential signal decoding modules, three high-speed three-wire three-level decoding modules, five first high-speed comparator modules, and three second high-speed comparator modules.

The switch switching module is shown in fig. 5, and the input and output signals of each single-input dual-output switch in the switch switching module are shown in the figure.

Since the C-PHY signal is usually composed of 9 lines in total, the D-PHY signal is usually composed of five differential signals in total, including 4 sets of data plus one clock, the LVDS is also composed of five differential signals similarly to the D-PHY signal, the high-speed SPI is composed of 6 lines in total, including 4 high-speed data plus one chip select signal and one clock, the 8-bit parallel signal is composed of 8 high-speed data lines plus one clock, the signal lines of the above five signals can be input through 10 data lines before entering the switch selection module, for example, the C-PHY uses only 9 of 10 data lines, the D-PHY and LVDS use 10 lines, the high-speed SPI uses 6 lines, and the 8-bit high-speed parallel signal uses 9 lines, the switch switching module needs ten switch chips with 1 input and 2 output, in order to complete the general input interface circuit, the differential signal decoding module and nineteen high-speed comparators in the high-speed three-wire three-level decoding module cooperate with the DAC module to complete single-ended signal decoding.

When the FPGA pins are distributed, HS signals and LVDS signals of MIPI D-PHY and MIPI C-PHY are converted into CML signal types, MIPI LP signals, SPI and multi-bit parallel single-ended signals are converted into LVCMOS signal types, and multiple signal types are simplified into two signal types through a circuit module for classified reception, so that the use of the FPGA pins can be reduced.

A test apparatus according to an embodiment of the present invention includes any one of the above-described multi-type signal receiving circuits.

Furthermore, the test equipment also comprises a plurality of camera modules, and the camera modules are used for generating any type of signals in MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS and 8-bit parallel signals.

The implementation principle and technical effect of the test equipment are similar to those of the receiving circuit, and are not described herein again.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the utility model, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. The receiving circuit of the multi-type signals is characterized by comprising a switch switching module, a signal decoding module, an LVDS-to-CML module and a control module, wherein the input end of the switch switching module is used for receiving any one of MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS and multi-bit parallel signals, the input end of the signal decoding module is electrically connected with the output end of the switch switching module, the output end of the signal decoding module is electrically connected with the input end of the LVDS-to-CML module, the output end of the LVDS-to-CML module is electrically connected with the control module, the output end of the signal decoding module is further electrically connected with the control module, and the control module is further electrically connected with the switch switching module.

2. The circuit of claim 1, wherein the signal decoding module comprises decoding circuits corresponding to MIPI D-PHY, MIPI C-PHY, high-speed SPI, LVDS, and multi-bit parallel signals, and the switch switching module is controlled by the control module to conduct an output of the switch switching module to one of the decoding circuits.

3. The multi-type signal receiving circuit according to claim 1 or 2, wherein the signal decoding module comprises a high-speed differential signal decoding module, a high-speed three-wire three-level decoding module, a first high-speed comparator module and a second high-speed comparator module, the LVDS-to-CML module comprises a first LVDS-to-CML module and a second LVDS-to-CML module, the input terminals of the high-speed differential signal decoding module and the first high-speed comparator module are electrically connected to the first set of output terminals of the switch switching module, the input terminals of the high-speed three-wire three-level decoding module and the second high-speed comparator module are electrically connected to the second set of output terminals of the switch switching module, the input terminal of the first LVDS-to-CML module is electrically connected to the output terminal of the high-speed differential signal decoding module, the input terminal of the second LVDS-to-CML module is electrically connected to the output terminal of the high-speed three-wire three-level decoding module, the output ends of the first high-speed comparator module, the second high-speed comparator module, the first LVDS-to-CML module and the second LVDS-to-CML module are electrically connected with the control module.

4. The multi-type signal receiving circuit according to claim 3, wherein the high-speed differential signal decoding module comprises a first LVDS buffer, and the first high-speed comparator module comprises a first comparator and a second comparator.

5. The circuit for receiving multiple types of signals according to claim 4, wherein the first set of outputs of the switch switching module includes a first pin, a second pin, and a third pin, one input of the first LVDS buffer and one input of the first comparator are electrically connected to the first pin of the switch switching module, the other input of the first LVDS buffer and one input of the second comparator are electrically connected to the second pin of the switch switching module, the third pin of the switch switching module is grounded, and the other input of the first comparator and the other input of the second comparator are connected to a reference voltage signal.

6. The multi-type signal receiving circuit according to claim 3, wherein the high-speed three-wire three-level decoding module comprises a second LVDS buffer, a third LVDS buffer and a fourth LVDS buffer, and the second high-speed comparator module comprises a third comparator, a fourth comparator and a fifth comparator.

7. The circuit for receiving multiple types of signals according to claim 6, wherein the first set of outputs of the switch switching module includes a fourth pin, a fifth pin, and a sixth pin, an input of the second LVDS buffer and an input of the third comparator are electrically connected to the fourth pin of the switch switching module, an input of the third LVDS buffer and an input of the fourth comparator are electrically connected to the fifth pin of the switch switching module, an input of the fourth LVDS buffer and an input of the fifth comparator are electrically connected to the sixth pin of the switch switching module, and another input of the third comparator, another input of the fourth comparator, and another input of the fifth comparator are connected to the reference voltage signal.

8. The multi-type signal receiving circuit of claim 3, further comprising a DAC module, wherein the DAC module is controlled by the control module and outputs a reference voltage signal to the first high speed comparator module and the second high speed comparator module.

9. The multi-type signal receiving circuit of claim 3, wherein the switch switching module comprises ten single-input dual-output switches, the number of the high-speed differential signal decoding modules is five, the number of the high-speed three-wire three-level decoding modules is three, the number of the first high-speed comparator modules is five, and the number of the second high-speed comparator modules is three.

10. A test apparatus comprising a multi-type signal receiving circuit according to any one of claims 1 to 9.

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