KR100874671B1 - Apparatus and method for data transmission - Google Patents

Abstract

An apparatus and method for data transmission are disclosed. According to an embodiment of the present invention, a data output unit for outputting m (arbitrary natural number) of parallel data and synchronized synchronization signals; And receiving the parallel data and the synchronization signals from the data output unit, inserting the synchronization codes set corresponding to the synchronization signals into the parallel data, and converting them into a serial data stream of n (any natural number) bits. And a first interface unit configured to generate a clock signal synchronized to a serial data stream, wherein the data output unit and the first interface unit, which are either a sensor or a processor, are provided on the same chip. Can be. Therefore, according to the present invention, the bandwidth can be expanded approximately twice in transmission of pixel data of a high pixel.

Description

Device and method for transferring data

1 illustrates a parallel interface structure for transmitting image data between a general image sensor and an additional processor.

2 is a block diagram of a system capable of transmitting data in a serial transmission method according to an embodiment of the present invention.

3 is a block diagram of internal functional components of a first interface unit according to an embodiment of the present invention;

4 is an exemplary diagram of pixel data and synchronization signals output by an image sensor according to an exemplary embodiment of the present invention.

5 is an exemplary diagram of data and clock signals output by an encoder unit according to an embodiment of the present invention.

6 is an exemplary diagram of pixel data in which a sync code is inserted according to an embodiment of the present invention.

7 is an exemplary diagram of data and clock signals outputted from a serial data converter according to an exemplary embodiment of the present invention.

8 illustrates an LVDS circuit according to an embodiment of the present invention.

9 illustrates a waveform of an LVDS in accordance with an embodiment of the present invention.

10 illustrates an internal functional block of a second interface unit according to an embodiment of the present invention.

FIG. 11 is a graph comparing a case where data is transmitted through an interface for high speed serial data transmission and a case where data is transmitted through an interface for conventional parallel data transmission according to an embodiment of the present invention. FIG.

12 is a flowchart illustrating a method of converting m-bit parallel data into an n-bit serial data stream and outputting the m-bit parallel data according to an embodiment of the present invention.

FIG. 13 is a flowchart illustrating a method of converting a serial data stream into a parallel data stream and outputting the serial data stream according to an embodiment of the present invention. FIG.

<Explanation of symbols for main parts of the drawings>

220: first interface unit

310: encoder section

320: serial data converter

330: differential signal output unit

230: second interface unit

1010: differential signal input unit

1020: parallel data converter

1030: decoder unit

The present invention relates to data transmission, and more particularly, to a method and a system capable of transferring data between an image sensor and an image signal processor at a high speed.

In recent years, small and thin image pickup devices are mounted in small and thin portable terminals such as mobile phones and PDAs (Personal Digital Assistants), whereby the portable terminals can function as image pickup devices. That is, the imaging device is provided not only in a mobile phone or a PDA but also in a portable terminal such as an MP3 player so that various devices can hold external images as electronic data. Therefore, in the case of a portable terminal having a communication function, not only the voice information but also the captured image information can be transmitted to a remote place.

In general, a solid-state imaging device such as a charge coupled device (CCD) image sensor or a complementary metal-oxide semiconductor (CMOS) image sensor is used for such an imaging device. The pixel data generated by the imaging device is transmitted in a parallel transmission method through a data bus capable of transmitting m-bit pixel data.

Referring to FIG. 1, a brief description will be given of a data transmission method between a general image pickup device and an image signal processor.

The image sensor 110 is a sensor having a Bayer pattern. The image sensor 110 outputs raw data corresponding to the amount of light input through the lens for each unit pixel (hereinafter, referred to as "pixel data" for convenience). To).

The image signal processor 120 converts pixel data input from the image sensor 110 into a YUV value, and outputs the converted YUV value to a baseband processor (not shown). The YUV method focuses on the fact that the human eye is more sensitive to brightness than color. The YUV method distinguishes colors into Y components of luminance and U and V components of chrominance. Since the Y component is sensitive to error, we code more bits than the color components U and V. A typical Y: U: V ratio is 4: 2: 2.

The image sensor 110 outputs m-bit pixel data through a data bus capable of simultaneously transmitting m-bit data, and a clock synchronized to the pixel data so that the image signal processor 120 may acquire the pixel data. The signal PCLK, the vertical synchronization signal VSYNC, and the valid data enable signal HREF are output to the image signal processor 120 through respective signal lines.

For example, if the size of the pixel data to be transmitted is an a ㅧ b pixel (including a line and b pixels per line), a valid period (for example, one vertical sync signal VSYNC) may be used. A valid data enable signal HREF is output corresponding to a high state or a low state in advance, and a valid period of one valid data enable signal HREF is output. For example, b pixel data may be output during the high state or the low state).

Since the image sensor 110 and the image signal processor 120 transmit data using a single ended signal method of a CMOS or TTL level, the image signal 110 and the image signal processor 120 may not increase the clock signal to 100 MHz or higher. In addition, many signal lines must be connected to transmit pixel data, and signals swing at relatively high input / output (I / O) voltages (for example, 1.8 V to 3.3 V), and high-capacity pixel data can be quickly Since the frequency of the clock signal PCLK must be increased in order to transmit the data, the power consumption is rapidly increased. In addition, there are many problems such as signal noise generation.

Accordingly, the present invention for solving the above problems provides an interface, an apparatus, and a method for data transmission that can be transmitted using a low pressure differential signal after converting m-bit parallel data into an n-bit serial data stream. It is for.

Another object of the present invention is to provide an interface, an apparatus, and a method for data transmission, in which a bandwidth can be approximately doubled in transmitting pixel data of a high pixel in a portable terminal.

In addition, an object of the present invention is to provide an interface, an apparatus, and a method for data transmission, which can reduce signal lines necessary for data transmission and transmit power by transmitting pixel data using a low pressure differential signal.

In addition, the present invention is to provide an interface, an apparatus, and a method for data transmission that can improve the electromagnetic interference (EMI) of the signal line for transmitting data or clock signal by transmitting the pixel data using the low pressure differential signal. .

In addition, the present invention reduces the number of internal signal lines required for data transmission, thereby facilitating PCB design and an interface for data transmission that can reduce costs by reducing the number of cables, PCB traces and connectors. To provide a device, and a method thereof.

In addition, the present invention is to provide an interface, an apparatus and a method for data transmission that can reduce the number of signal lines required for data transmission, thereby reducing the size of the I / O pin.

Other objects of the present invention will be easily understood through the description of the following examples.

In order to achieve the above object, according to an aspect of the present invention, there is provided an apparatus capable of transmitting and receiving parallel data as serial data during data transmission between each chip.

According to an embodiment of the present invention, a data output unit for outputting m (arbitrary natural number) of parallel data and synchronized synchronization signals; And receiving the parallel data and the synchronization signals from the data output unit, inserting the synchronization codes set corresponding to the synchronization signals into the parallel data, and converting them into a serial data stream of n (any natural number) bits. And a first interface unit configured to generate a clock signal synchronized to a serial data stream, wherein the data output unit and the first interface unit, which are either a sensor or a processor, are provided on the same chip. Can be.

The first interface unit includes: an encoder unit for inserting and outputting the sync code into the parallel data, and generating and outputting a first clock signal synchronized to the parallel data into which the sync code is inserted; And converting the parallel data into which the sync code is inserted, by n bits, converting the parallel data into the serial data stream in units of n bits, and generating and outputting a second clock signal obtained by dividing the first clock signal. It may include a serial data converter.

The encoder unit may be connected to the serial data converter through a plurality of data buses for outputting parallel data into which the sync code is inserted and a first clock signal line for outputting the first clock signal.

When the input clock of the encoder is faster than the output clock, the encoder inserts a synchronization code into pre-input pixel data and outputs the serial data converter through one of a first data bus and a second data bus to the serial data converter. The pixel data may be inserted into a synchronization code and output to the serial data converter through another one of the first data bus and the second data bus.

When the encoder unit temporarily stores the pixel data into which the sync code is inserted and then writes a predetermined bit amount, the encoder unit may output the serial data converter through the first data bus and the second data bus in units of m bits, respectively. Can be.

When the data output unit is an image sensor that outputs m-bit pixel data corresponding to a subject and corresponding synchronization signals, the synchronization signals are a clock signal PCLK for acquiring the parallel data and for identification of each frame. A vertical synchronization signal VSYNC and a valid data enable signal HREF for identifying a line in each frame, and the encoder unit SOF indicating the start of a frame when the vertical synchronization signal VSYNC changes to a first state. (start of frame sync code) is inserted into the parallel data, and when the vertical sync signal VSYNC is changed to the second state, an end of frame sync code (EOF) indicating the end of the frame is inserted into the parallel data. The first state is any one of a falling edge or a rising edge, and the second state is one of a falling edge or a rising edge. It may be another one.

When the valid data enable signal HREF is changed to the third state after the vertical synchronization signal VSYNC is changed to the first state, the encoder unit generates a start of line sync code (SOL) indicating the start of a line. Inserting the parallel data and inserting an end of line sync code (EOL) indicating the end of the line when the valid data enable signal is changed to a fourth state, wherein the third state is the third state; One of the first state and the second state, and the fourth state may be the other of the first state and the second state.

And a differential signal output unit converting the serial data stream and the second clock signal into a low pressure differential signal and outputting the differential data signal, wherein the serial data converter outputs a plurality of data signal lines and the clock signal for outputting the serial data stream. The differential signal output unit may be connected to a clock signal line.

The serial data converter may output bit values at odd positions of the serial data stream through a third data signal line, and output bit values at even positions to the differential signal output unit through a fourth data signal line.

비트씩 시프트시켜 상위

비트의 직렬 데이터 스트림은 제3 데이터 신호선을 통해 출력하며, 하위 quation.3

비트의 직렬 데이터 스트림은 제4 데이터 신호선을 통해 상기 차등신호 출력부로 출력할 수 있다.The serial data converter may convert pixel data into which the sync code is inserted.

Shift bit by bit

The serial data stream of bits is output through the third data signal line, and the lower quation.3

The serial data stream of bits may be output to the differential signal output unit through a fourth data signal line.

According to another embodiment of the present invention, an n (random natural number) bit serial data stream and a synchronized clock signal are input and converted into m (random natural number) bit parallel data, and a preset sync code is detected. Generating a corresponding synchronization signal, and outputting parallel data from which the synchronization code has been removed; And a processor configured to receive the parallel data and the synchronization signal through the second interface unit and convert the parallel data and the synchronization signal into a predetermined data format, wherein the processor and the second interface unit are provided on the same chip. Can be provided.

The second interface unit may include: a parallel data converter configured to shift the serial data stream by n bits to convert the serial data stream into m-bit parallel data, and to generate and output a clock signal synchronized with the parallel data; And a decoder configured to receive the parallel data and the clock signal, detect a sync code set in the parallel data using the clock signal, generate a corresponding sync code, and generate and output parallel data from which the sync code has been removed. It may include.

The parallel data converter may be connected to the decoder through a plurality of data buses for outputting the parallel data and a clock signal line for outputting the clock signal.

When the input clock of the parallel data converter is faster than the output clock, the parallel data converter converts the pre-input serial data stream into parallel data and outputs the same to the decoder by using one of the first data bus and the second data bus. The converted serial data stream may be converted into parallel data and then output to the decoder using another one of the first data bus and the second data bus.

When the parallel data converter temporarily stores the parallel data in a buffer and satisfies a predetermined bit amount, the parallel data converter performs parallel transmission on the first data bus and the second data bus by m bits in parallel data stored in the buffer. Each can be output to the decoder.

The decoder generates and outputs a vertical synchronizing signal VSYNC changed to a first state when the converted parallel data is SOF, and outputs a vertical synchronizing signal VSYNC changed to a second state when the converted parallel data is EOF. Generate and output, wherein the first state is any one of a falling edge or a rising edge, and the second state is the other of a falling edge or a rising edge. Can be.

The decoder generates and outputs a valid data enable signal HREF converted to the third state when the converted parallel data is SOL, and valid data converted to the fourth state when the converted parallel data is EOL. Generate and output an enable signal HREF, wherein the third state is any one of the first state and the second state, and the fourth state may be another one of the first state and the second state. have.

And a differential signal input unit configured to receive the low differential pressure signal and convert the low voltage differential signal into the serial data stream and output the converted differential data signal, wherein the serial data converter includes a plurality of data signal lines for inputting the serial data stream and one for inputting the clock signal. It may be connected to the differential signal input unit through a clock signal line.

The serial data converter receives a bit value of an odd position of the serial data stream through a first data signal line, and receives a bit value of an even position of the serial data stream through a second data signal line to convert the bit data into the parallel data. Can be.

비트의 비트값들을 입력받고, 제2 데이터 신호선을 통해 상기 직렬 데이터 스트림의 하위

비트의 비트값들을 입력받아 상기 병렬 데이터로 변환할 수 있다.The serial data converter is higher than the serial data stream through a first data signal line.

Receive bit values of a bit, and subordinate the serial data stream through a second data signal line

The bit values of the bits may be input and converted into the parallel data.

According to still another embodiment of the present invention, there is provided a data transmission apparatus for converting m (any natural number) bits of parallel data into a serial data stream of n (any natural numbers) bits; And a data receiving device receiving the serial data stream and converting the serial data stream into parallel data, wherein the data transmission device comprises: a data output unit configured to output synchronization signals synchronized with parallel data of m (any natural number) bits; And receiving the parallel data and the synchronization signal from the data output unit, inserting synchronization codes set according to the synchronization signals into parallel data, converting the serial data stream to the n-bit serial data, and outputting the serial data stream. And a first interface unit configured to generate and output a clock signal synchronized with a data stream, wherein the data receiving device receives the input n-bit serial data stream and the synchronized clock signal and converts the m-bit parallel data into parallel data. A second interface unit detecting a preset sync code to generate a corresponding sync signal, and outputting parallel data from which the sync code has been removed; And a processor configured to receive the parallel data and the synchronization signal through the second interface unit and convert the parallel data and the synchronization signal into a predetermined data format.

The data output unit and the first interface unit, which are either the sensor or the processor, may be provided on the same chip, and the second interface unit and the processor may be provided on the same chip.

According to another aspect of the present invention, there is provided a data transmission method capable of transmitting and receiving parallel data as serial data during data transmission between each chip.

According to an embodiment of the present invention, in a method in which a first interface unit provided on the same chip as a data output unit, which is either a sensor or a processor, transmits data, the encoder unit is m from the data output unit (any natural number). Receiving parallel data of bits and synchronized synchronization signals; Inserting and outputting, by the encoder, synchronization codes set corresponding to the synchronization signals into the parallel data, and generating and outputting a first clock signal synchronized with the parallel data into which the synchronization codes are inserted; And a serial data converter converts the parallel data into which the sync code is inserted and converts the data into a serial data stream by n bits (random natural numbers), and generates a second clock signal synchronized with the serial data stream. A data transmission method including the step of outputting may be provided.

Inserting and outputting sync codes set corresponding to the sync signals into the parallel data includes: temporarily storing parallel data having a sync code inserted into the buffer; Determining whether parallel data in which a sync code is inserted is stored in the buffer by an area having a predetermined size; And storing the parallel data into which the stored sync code is inserted to the serial data converter through the first data bus and the second data bus in units of m bits when the data is stored in an area having a predetermined size.

When the data output unit is an image sensor that outputs m-bit pixel data corresponding to a subject and corresponding synchronization signals, the synchronization signals are a clock signal PCLK for acquiring the parallel data and for identification of each frame. It may be a vertical synchronization signal VSYNC and a valid data enable signal HREF for identification of a line in each frame.

The outputting of the parallel data into which the sync codes are inserted may include inserting a start of frame sync code (SOF) set corresponding to the start of the frame into the parallel data when the vertical sync signal VSYNC is in the first state. step; If the vertical synchronization signal is in the second state, inserting an end of frame sync code (EOF) set corresponding to the end of the frame into the parallel data; If the valid data enable signal (HREF) is in a third state, inserting a start of line sync code (SOL) corresponding to the start of a line into the parallel data; And inserting an end of line sync code (EOL) set to the parallel data when the valid data enable signal HREF is in a fourth state, wherein the first state is polled. Either an edge or a rising edge, the second state is the other of a falling edge or a rising edge, and the third state is the first state and the rising edge. Any one of the second states, and the fourth state may be another one of the first state and the second state.

Converting and outputting the serial data stream may include outputting bit values at odd positions of the serial data stream through a third data signal line; And outputting bit values of even positions of the serial data stream through a fourth data signal line.

비트의 비트값들을 출력하는 단계; 및 제4 데이터 신호선을 통해 상기 직렬 데이터 스트림의 하위

비트의 비트값들을 출력하는 단계를 포함할 수 있다.An upper portion of the serial data stream via a third data signal line

Outputting bit values of the bit; And a lower portion of the serial data stream via a fourth data signal line.

Outputting bit values of the bit.

According to another embodiment of the present invention, a method of receiving data in a second interface unit included in the same chip as a processor that acquires m (arbitrary natural number) of parallel data and converts it into a predetermined data format, the received n Converting and outputting a (random natural number) bit of the serial data stream and the synchronized first clock signal; Shifting the serial data stream by the n bits to generate and output the parallel data, and generating and outputting a second clock signal synchronized with the parallel data; And detecting sync codes set in the parallel data using the second clock signal to generate and output corresponding sync signals, and outputting parallel data from which the sync codes have been removed. Can be.

The generating and outputting the parallel data by shifting the bits by n bits may include: temporarily storing the parallel data in a buffer; Determining whether parallel data are stored by an area of a predetermined size of the buffer; And if the data is stored in a predetermined area, outputting the stored parallel data to the decoder through the first data bus and the second data bus in units of m bits.

Detecting the sync codes set in the parallel data and generating and outputting corresponding sync signals includes: when the parallel data is the SOF, the vertical sync signal VSYNC changed to a first state and valid data changed to a third state. Generating and outputting an enable signal HREF; Generating and outputting a vertical synchronization signal changed to a second state and a valid data enable signal changed to a fourth state if the parallel data is the EOF; Generating and outputting a valid data enable signal changed to the third state if the parallel data is the SOL; And generating and outputting a valid data enable signal changed to the fourth state if the parallel data is the EOL, wherein the first state includes any of a falling edge and a rising edge. The second state is one of a falling edge and a rising edge, the third state is any one of the first state and the second state, and the fourth state is the first state and the second state. It may be another one of the states.

The generating and outputting the parallel data by shifting the bits by n bits may include receiving n-bit bit values through a third data signal line and a fourth data signal line, respectively; And generating and outputting the parallel data by shifting and inputting each of the input bit values by n bits in a predetermined order.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted. In addition, in describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

2 is a block diagram of a system for transmitting data in a serial transmission method according to an embodiment of the present invention. Hereinafter, the sensor unit 202 includes an image sensor 210 and a first interface 220, and the sensor unit 202 may be connected to a processor (eg, an image signal processor 220) connected to a rear end thereof. It will be described on the assumption that m (natural number) bit pixel data is converted into n (natural number) bit serial data stream and output. That is, in the present specification, the sensor unit 202 converts pixel data into an n-bit serial data stream, and the processor unit 204 receives an n-bit serial data and converts it into m-bit pixel data for processing. Can be done.

Referring to FIG. 2, the system 200 for transmitting data in a serial data transmission method includes a sensor unit 202 and a processor unit 204.

The sensor unit 202 includes an image sensor 210 and a first interface unit 220, and the processor unit 204 includes a second interface unit 230 and an image signal processor 240. It is composed.

The image sensor 210 generates a signal obtained by converting an optical signal corresponding to a subject (hereinafter, referred to as "pixel data" for convenience of understanding and explanation) and outputs the signal to the first interface unit 220. To perform.

For example, the image sensor 210 includes a pixel array in which a plurality of unit pixels are arranged along a row or a column, such as a CCD or CMOS sensor, and each unit pixel electrically converts an optical signal of a subject. It may include a photoelectric conversion element (for example, a photodiode) to convert the signal into a signal.

The image sensor 210 generates pixel data and synchronization signals synchronized with the pixel data (for example, a clock signal PCLK, a vertical synchronization signal VSYNC, and a valid data enable signal HREF). Output to the interface unit 220.

Here, the clock signal PCLK is a synchronization signal for acquiring pixel data output from the image sensor 210, and the vertical synchronization signal VSYNC is a synchronization signal for identifying data according to each frame. The valid data enable signal HREF is a synchronization signal for identifying data output during each valid period (ie, each line).

Hereinafter, in the present specification, when the vertical synchronization signal VSYNC is in the first state (falling edge) and the valid data enable signal HREF is in the second state (rising edge), the pixel data is acquired at the corresponding edge. Although the description will be focused on the following, depending on the implementation method, when the vertical synchronization signal is in the second state and the valid data enable signal HREF is in the first state, acquisition of pixel data may be started at the corresponding edge. Of course it is.

In addition, the valid data enable signal HREF has a plurality of valid periods (for example, 420a, 420b, ..., 420n) and the x-axis information counter within the valid period while the vertical synchronization signal VSYNC is low. (Not shown) is updated, and x-axis coordinates can be generated by the updated count.

The y-axis coordinates may be generated by the updated count of the y-axis information counter (not shown) at each starting point of the valid section in the valid data enable signal HREF.

That is, the image sensor 210 generates m-bit pixel data and corresponding synchronization signals (for example, a clock signal PCLK, a vertical synchronization signal VSYNC, and a valid data enable signal HREF). Output to the interface unit 220.

The first interface unit 220 receives the synchronization signals corresponding to the m-bit pixel data from the image sensor 210, converts them into an n-bit serial data stream, and generates a clock signal synchronized to the serial data stream. Perform the function of printing. Hereinafter, the internal function of the first interface unit 220 will be described in detail with reference to FIG. 3.

As described above, the sensor unit 202 generates m-bit pixel data corresponding to a subject, converts it into an n-bit serial data stream, and processes the processor unit 204 together with a clock signal synchronized to the serial data stream. Perform the function to output to.

The processor unit 204 acquires an n-bit serial data stream corresponding to a clock signal input through the sensor unit 202, converts the n-bit serial data stream into m-bit pixel data, and then converts it into a predetermined image data format. .

The function of the second interface unit 230 that receives the n-bit serial data stream from the processor unit 204 and converts the m-bit parallel data (ie, pixel data) will be described in detail with reference to FIG. 10 below. Shall be.

The image signal processor 240 receives the m-bit pixel data output through the second interface unit 230 and converts the pixel data into a predetermined image data format.

As described above, the sensor unit 202 according to the present invention generates m-bit pixel data, converts it into an n-bit serial data stream, and outputs the data to the processor unit 204 connected to the rear stage, thereby transmitting data at high speed. There is an advantage to that.

In the present specification, the sensor unit 202 converts m-bit parallel data into an n-bit serial data stream and outputs the data. However, any device that outputs data in a parallel transmission method (for example, baseband). Naturally, the same may be applied to the processor.

In addition, in the present specification, the processor unit 204 receives n-bit serial data stream and converts it to m-bit pixel data. However, the processor unit 204 converts m-bit parallel data to n-bit serial data. Naturally, it can be converted to a data stream and output to another later processor (eg, a baseband processor).

As described above, the sensor unit 202 converts m-bit pixel data into an n-bit serial data stream and outputs the same, thereby increasing the frame rate during data transmission.

3 is a block diagram of an internal functional component of a first interface unit according to an embodiment of the present invention, and FIG. 4 is an example of pixel data and synchronization signals output by an image sensor according to an embodiment of the present invention. 5 is a diagram illustrating data and a clock signal output by an encoder according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating pixel data in which a sync code is inserted according to an embodiment of the present invention. 7 is a diagram illustrating a data and clock signal output by the serial data converter according to an embodiment of the present invention, FIG. 8 is a diagram illustrating an LVDS circuit according to an embodiment of the present invention, and FIG. 9 is a diagram of the present invention. A diagram illustrating a waveform of an LVDS according to an embodiment of the present invention. Hereinafter, the sensor unit 202 for outputting pixel data corresponding to a subject will be described with a focus on converting m-bit pixel data into an n-bit serial data stream and outputting the same. The first interface unit 220 described below is assumed to be included in the sensor unit 202 will be described. Accordingly, the image sensor 210 and the first interface unit 220 of the sensor unit 202 are included in one chip, and data transmission between components in one chip may be transmitted in a parallel transmission method. In addition, the data transmission between the chips may be to transmit data in a serial data transmission method (that is, the data transmission between the image sensor 210 and the first interface unit 220 in the sensor unit 202 is a parallel transmission method). Data may be transmitted, and data transmission between the sensor unit 202 and the processor unit 204 may be transmitted in a serial data manner).

Hereinafter, the first interface unit 220 included in the sensor unit 202 and converting pixel data output from the image sensor 210 into a serial data stream and outputting the same will be described in detail.

Referring to FIG. 3, the first interface unit 220 capable of converting pixel data in units of m bits into a serial data stream in units of n bits includes an encoder unit 310, a serial data converter 320, and a differential signal output. It is configured to include a portion 330.

The encoder 310 may include pixel data and one or more synchronization signals synchronized with the pixel data (for example, the first clock signal PCLK, the vertical synchronization signal VSYNC, and the valid data enable signal HREF). Is input from the image sensor 210 to insert a predetermined sync code in front of or behind the pixel data according to the corresponding sync signals, and output the same to the serial data converter 320. Also, the encoder unit 310 converts a clock signal (hereinafter, referred to as a “first clock signal” for convenience of understanding and explanation) to the serial data converter 320 in synchronization with pixel data into which a sync code is inserted. You can print

First, a method of obtaining pixel data and a method of inserting respective sync codes by the encoder unit 310 will be briefly described with reference to FIG. 4.

Referring to FIG. 4, when the vertical synchronization signal VSYNC is in a low state and the valid data enable signal HREF is in a high state, the encoder unit 310 corresponds to the pixel signal in response to the clock signal PCLK. Can be obtained. In the present specification, the valid data enable signals HREF are respectively in a high state. The pixel data acquired in each valid section of the valid data enable signal HREF indicates that the pixel data is included in the same line. That is, pixel data obtained in the state of 420a of FIG. 4 have the same y-axis coordinate. As described above, since the y-axis coordinate is updated every time the valid data enable signal HREF becomes the second state, the 430a, 430b,... At 430n, the y-axis coordinates are updated.

Accordingly, it can be seen that the vertical synchronization signal VSYNC is in a low state, and the pixel data obtained for the first time in the first valid period of the valid data enable signal HREF is the first data in the corresponding frame. For this reason, the encoder unit 310 is a sync code (SOF: start of frame sync code) for notifying the start of the frame in front of the pixel data obtained at the corresponding time point, for convenience of understanding and explanation. ), Referred to as "SOF".

In addition, when the valid data enable signal HREF is changed to the second state, the encoder unit 310 may indicate a synchronization code (line start synchronization code (SOL) start of line before the first pixel data obtained). sync code)-hereafter referred to as "SOL" for ease of understanding and explanation. That is, the encoder unit HREF may insert the SOL immediately after the valid data enable signal HREF is changed to the second state.

In this case, the encoder 310 inserts the SOF immediately after the vertical synchronization signal VSYNC is changed to the first state. In this case, the encoder unit 310 does not insert the SOL even when the valid data enable signal HREF is changed to the second state. That is, the SOF alone may recognize that the vertical synchronization signal VSYNC is changed to the first state and the valid data enable signal HREF is changed to the second state.

In addition, the encoder unit 310 may include a sync code (end of line sync code (EOL)) indicating the end of a line after pixel data last obtained in a valid period of the valid data enable signal HREF. -For convenience of understanding and explanation, hereinafter referred to as "EOL").

Similarly, when the vertical sync signal VSYNC is in the low state, the encoder unit 310 indicates a sync code indicating the end of the frame after the last acquired pixel data in the last valid period of the valid data enable signal HREF. (End of frame sync code (EOF)-hereinafter referred to as "EOF" for ease of understanding and explanation) is inserted.

Here, the encoder unit 310 is inserted when the EOF is inserted (i.e., when the vertical synchronization signal VSYNC is low, after the last acquired pixel data within the last valid period of the valid data enable signal HREF). Insert only EOF without inserting EOL. That is, the EOF may indicate that the vertical synchronization signal VSYNC is changed to the second state and may indicate that the valid data enable signal HREF is changed to the first state.

That is, the encoder 310 receives the m-bit pixel data and the synchronization signals synchronized with the pixel data from the image sensor 210, and inserts the respective synchronization codes preset in correspondence with the respective synchronization signals. And a first clock signal synchronized with the pixel data into which the corresponding sync code is inserted, may be output to the serial data converter 320.

In FIG. 5, pixel data and a first clock signal including a synchronization code output from the encoder 310 to the serial data converter 320 are illustrated. 6 illustrates pixel data in which the encoder 310 inserts respective sync codes corresponding to sync signals input from the image sensor 210. Referring to FIG. 6, it can be seen that the SOF indicating the start of the frame is inserted at the best and the EOF indicating the end of the frame is inserted last. In addition, it can be seen that a SOL is inserted at the beginning of each line to indicate the beginning of the line, and an EOL is inserted at the end of each line to indicate the end of the line.

As such, by inserting sync codes indicating the characteristics (ie, start and end) of each frame or line in the pixel data, the encoder unit 310 generates separate sync signals indicating the characteristics of each frame and line (eg, For example, there is an advantage that the vertical synchronization signal VSYNC and the valid data enable signal HREF do not need to be output.

Referring back to FIG. 3, the encoder 310 may include a plurality of data buses (eg, a first data bus 341 and a second) capable of transmitting the serial data converter 320 and m-bit data in parallel. Data bus 342 and a first clock signal line 343 for transmitting a clock signal.

For example, the encoder 310 temporarily stores pixel data into which a synchronization code is inserted, in a buffer, and then serial data converter through the first data bus 341 and the second data bus 342 in m-bit units. And output to 320.

For another example, when the clock speeds of the encoder unit 310 and the image sensor 210 are different (that is, when the clock speed of the image sensor 210 is faster than the clock speed of the encoder unit 310), The pixel data input from the image sensor 210 is input faster than the pixel data into which the sync code output through the encoder 310 is inserted. That is, suppose that the clock speed of the image sensor 210 is about twice faster than the clock speed of the encoder 310. In this case, a speed difference of about twice occurs between the pixel data input from the image sensor 210 by the encoder 310 and the pixel data into which the sync code output from the encoder 310 is inserted. As a result, the encoder 310 receives the pixel data about twice as fast from the image sensor 210 as compared with outputting the pixel data into which the sync code is inserted. In this case, the encoder unit 310 may reduce the difference between the pixel data input from the image sensor 210 and the pixel data into which the sync code outputted through the encoder unit 310 is inserted. The pixel data into which the synchronization code is inserted is output to the serial data converter 320 using the first data bus 341 and the second data bus 342. Through this, the encoder 310 may reduce the input / output difference between the pixel data input from the image sensor 210 and the pixel data into which the synchronization code is output.

The serial data converter 320 acquires pixel data into which a sync code is inserted using the first clock signal input from the encoder 310, and converts the serial data stream into a serial data stream in units of n (any natural number) bits. Outputs to the differential signal output unit 330 together with the clock signal synchronized to the serial data stream (hereinafter referred to as "second clock signal" for convenience of understanding and explanation).

Here, since the serial data converter 320 outputs an n-bit serial data stream through a plurality of data signal lines, the serial data converter 320 generates a second clock signal in which the first clock signal is divided in accordance with the number of the corresponding data signal lines to generate a differential signal. The output unit 330 may output the same.

For example, the serial data converter 320 may generate the n-bit serial data stream by shifting the pixel data inserted with the sync code input through the encoder 310 by n bits. The serial data converter 320 outputs even-numbered bit values of the n-bit serial data stream through the fifth data signal line 351, and odd-numbered bit values of the n-bit serial data stream through the sixth data signal line 352. You can output it. In addition, the serial data converter 320 may generate a second clock signal obtained by dividing the first clock signal input through the encoder 310 into the second clock signal line 353 to generate the second clock signal 330. Can be printed as

It is assumed that the serial data converter 320 generates a 2-bit serial data stream by shifting pixel data into which an m-bit sync code is inserted by 2 bits. Then, the serial data converter 320 outputs the first bit value through the fifth data signal line 351 and the second bit value through the second data signal line 352 to the differential signal output unit 330. can do.

비트씩 시프트시켜 상위

비트값들은 제5 데이터 신호선(351)을 통해 차등신호 출력부(330)로 출력하고, 하위

비트값들은 제6 데이터 신호선(352)을 통해 차등신호 출력부(330)로 출력할 수 있다. 이와 같은 경우, 직렬 데이터 스트림과 제2 클럭 신호는 더블 데이터 레이트(double data rate)의 관계를 갖음은 당연하다.As another example, the serial data converter 320 may convert pixel data into which a sync code of m-bit units is inserted.

Shift bit by bit

The bit values are output to the differential signal output unit 330 through the fifth data signal line 351, and

The bit values may be output to the differential signal output unit 330 through the sixth data signal line 352. In such a case, it is natural that the serial data stream and the second clock signal have a double data rate relationship.

7 illustrates a serial data stream and a second clock signal output from the serial data converter 320 to the differential signal output unit 330.

Referring to FIG. 3 again, the differential signal output unit 330 is connected to the serial data converter 320 through a fifth data signal line 351, a sixth data signal line 352, and a second clock signal line 353. . The differential signal output unit 330 converts the LVCMOS / LVTTL level serial data stream and the second clock signal input through the serial data converter 320 into low voltage differential signaling (LVDS). Performs a function of outputting to the processor unit 204. Here, the method of inputting and outputting data through the LVCMOS or / and LVTTL signal is obvious to those skilled in the art, so a separate description thereof will be omitted.

For convenience of understanding and explanation, referring to FIG. 8, a low pressure differential signal (LVDS-hereinafter referred to as "LVDS") will be briefly described. LVDS is an interface standard for high-speed data transmission. The use of the differential signal has advantages such as fast bit rate, low power consumption, and excellent noise performance in data transmission.

Referring to the LVDS circuit illustrated in FIG. 8, when data input from the driver 810 is high, 1.5 mA is driven. A voltage signal of 150 mV is generated by the 100 kΩ termination resistor on the receiver 820 side. If the data input from the driver 810 is low, -1.5 mA is driven, and a signal of -150 mV is generated at an input terminal of the receiver 920 side. Here, the driver 810 is a differential signal output unit 330, the receiver 820 is a differential signal input unit 1010 described below.

A waveform according to LVDS is illustrated in FIG. 9. Referring to FIG. 9, when data corresponding to high is input to the driver 910, a low pressure differential signal of 75 mV as the first signal line and -75 mV as the second signal line is generated and output. It can be seen that a signal of 150mV is generated and input to the receiver 920 by the 100Ω termination resistor.

In the present specification, the low-pressure differential signal output by the differential signal output unit 330 is assumed to be 75mV, which has been described with emphasis on this.

That is, the differential signal output unit 330 is configured as such LVDS, and converts the serial data stream input through the serial data converter 320 into a low pressure differential signal. Through this, data can be transmitted at high speed and common noise can be reduced. In addition, the use of fewer signal lines compared to the conventional LVCMOS / LVTTL has the advantage of reducing the electromagnetic interference (EMI) to the RF radiation.

10 is a diagram illustrating an internal functional block of a second interface unit according to an embodiment of the present invention. The second interface unit 330 described below is a component of the processor unit 204 and performs a function of receiving a serial data stream input through the sensor unit 202 and converting the serial data stream into parallel data.

As illustrated in FIG. 10, the second interface unit 230 includes a differential signal input unit 1010, a parallel data converter 1020, and a decoder 1030.

The differential signal input unit 1010 converts the serial data stream and the second clock signal input from the sensor unit 202 as the low voltage differential signal into the LVCMOS / LVTTL signal level and outputs the parallel data converter 1020. . Here, as described above, the low pressure differential signal may be 75mV, or may be implemented in 150mV, 300mV, etc. depending on the implementation method.

The differential signal input unit 1010 includes a plurality of data signal lines (seventh data signal line 1041 and an eighth data signal line 1042) for outputting a serial data stream and a third clock signal line for outputting a second clock signal ( 1043 is connected to the parallel data converter 1020.

For example, the differential signal input unit 1010 outputs bit values at odd positions of the serial data stream to the parallel data converter 1020 through the seventh data signal line 1041 and bit values at even positions of the serial data stream. They may be output to the parallel data converter 1020 through the eighth data signal line 1042. The differential signal input unit 1010 may output the second clock signal to the parallel data converter 1020 through the third clock signal line.

As another example, the differential signal input unit 1010 receives a serial data stream corresponding to a predetermined k (natural number greater than n and less than m) bits from the sensor unit 202, respectively, using the first data signal line and the second data signal line. Suppose we receive input via In this case, the differential signal input unit 1010 receives a k-bit serial data stream input as a low pressure differential signal from the sensor unit 202 and outputs it to the parallel data converter 1020 through the seventh data signal line 1041. . The differential signal input unit 1010 may output another k-bit serial data stream to the parallel data converter 1020 through the eighth data signal line 1042.

비트에 상응하는 직렬 데이터 스트림을 제1 데이터 신호선 및 제2 데이터 신호선을 통해 각각 입력 받는 다고 가정하자. 차등신호 입력부(1010)는 상위

비트의 직렬 데이터 스트림은 제7 데이터 신호선(1041)을 통해 병렬 데이터 변환부(1020)로 출력하며, 하위

비트의 직렬 데이터 스트림은 제8 데이터 신호선(1042)을 통해 병렬 데이터 변환부(1020)로 출력할 수 있다.For example, the differential signal input unit 1010 may be moved from the sensor unit 202.

Assume that a serial data stream corresponding to a bit is input through a first data signal line and a second data signal line, respectively. Differential signal input unit 1010 is higher

The serial data stream of bits is output to the parallel data converter 1020 through the seventh data signal line 1041, and

The serial data stream of bits may be output to the parallel data converter 1020 through the eighth data signal line 1042.

The parallel data converter 1020 may include a plurality of data buses (eg, a third data bus 1051 and a fourth data bus 1052) for outputting data and a fourth clock signal line 1053 for outputting a clock signal. It is connected to the decoder unit 1030 through.

The parallel data converter 1020 receives the second clock signal from the differential signal input unit 1010 through the third clock signal line 1043, and through the fifth data signal line 1041 and the sixth data signal line 1042, respectively. Receive a serial data stream. The parallel data converter 1020 acquires serial data streams respectively input through the fifth data signal line 1041 and the sixth data signal line 1042 using the second clock signal, and merges them according to a predetermined method. merge) to generate m-bit parallel data. The parallel data converter 1020 outputs m-bit parallel data to the decoder unit 1030 through the third data bus 1051 and the fourth data bus 1052 according to a predetermined method. The parallel data converter 1020 generates a clock signal (for example, a third clock signal) synchronized to the generated parallel data and outputs the clock signal to the decoder 1030 through the fourth clock signal line 1053.

For example, the parallel data converter 1020 may temporarily store the generated m-bit parallel data in a buffer (not shown). When all data is written to the buffer, the parallel data converter 1020 may output the data to the decoder 1030 through the third data bus 1051 and the fourth data bus 1052.

For another example, the speeds of the clocks of the parallel data converter 1020 and the decoder 1030 may be different. That is, when the speed at which the decoder 1030 outputs data is faster than the speed at which data is input, a difference occurs between the speed at which data is input and the speed at which data is output. Accordingly, the decoder 1030 receives and processes data through a plurality of data buses (that is, the third data bus 1051 and the fourth data bus 1052), and then generates pixel data to generate image data processor 240. ) Can be sent.

The decoder unit 1030 inputs each of the data buses (ie, the third data bus 1051 and the fourth data bus 1052) by using the third clock signal input from the parallel data converter 1020. After the parallel data is acquired, the synchronization codes preset to the obtained parallel data are detected, and the synchronization signals corresponding to the synchronization code (for example, the vertical synchronization signal VSYNC and the valid data enable signal HREF) are obtained. To generate and output to the image signal processor (240). If the parallel data acquired corresponding to the third clock signal does not match the preset synchronization code, the decoder 1030 outputs the parallel data as pixel data to the image signal processor 240.

For example, if the parallel data acquired in response to the third clock signal is SOF, the decoder 1030 generates a vertical synchronization signal VSYNC which is in state transition to the first state, and outputs the generated vertical synchronization signal VSYNC to the image signal processor 240. . The decoder 1030 may generate the valid data enable signal HREF transitioned to the second state and output the valid data enable signal HREF to the image signal processor 240. Here, the first state and the second state may be either a falling edge or a rising edge as described above. The decoder 1030 does not output the obtained parallel data as pixel data since the obtained parallel data is a synchronization code for indicating a state transition of corresponding synchronization signals.

In addition, if the obtained parallel data is SOL, the decoder unit 1030, the valid data enable signal (HREF) transitioned to the second state to indicate the start of each line of each frame (that is, the start of the valid period) Generates and outputs the image signal to the processor 240. If the obtained parallel data is EOL, the valid data enable signal HREF which is in a state transition to the first state is generated and output to the image signal processor 240 to indicate the end of the valid period.

In addition, if the acquired parallel data is EOF, the decoder 1030 generates a vertical synchronization signal VSYNC which has transitioned to a second state to notify the end of the frame, and outputs the generated vertical synchronization signal VSYNC to the image signal processor 240.

When the obtained parallel data matches the preset synchronization code, the decoder unit 1030 may obtain the image signal processor 240 as pixel data since the obtained parallel data is a synchronization code for generating synchronization signals. Do not print

On the other hand, if the obtained parallel data is not one of SOF, SOL, EOL, and EOF (that is, the obtained parallel data does not match the preset sync code), the decoder unit 1030 obtains the corresponding acquired data. Parallel data is output to the image signal processor 240 as pixel data.

Accordingly, the image signal processor 240 may receive pixel data input from the sensor unit 202 in the form of a serial data stream and convert the pixel data into a predetermined image data format.

11 is a graph comparing a case where data is transmitted through an interface for high speed serial data transmission and a case where data is transmitted through an interface for conventional parallel data transmission according to an embodiment of the present invention.

Referring to FIG. 11, a graph comparing a conventional method of transmitting data through an interface for parallel data transmission and a case of transmitting data through an interface for serial data transmission according to an embodiment of the present invention. The x-axis of FIG. 11 represents a frame rate, and the y-axis represents a pixel clock frequency. Each graph represents a bandwidth of a band according to transmission of pixel data according to 1MP (mega pixel), 1.2MP, 2MP, 3MP, 4MP, 5MP, 6MP, and 8MP. In the graph of FIG. 11, the blanking time per line was 5.5 us, and the blanking time per frame was 500 us.

1110 of FIG. 11 illustrates an interface for high-speed serial data transmission in YUV422 (16 bit / pixel) format for each pixel (for example, when the first interface 220 and the second interface 230 are transmitted). In FIG. 11, 1120 shows a bandwidth for transmitting a YUV422 (16 bit / pixel) format to an interface for conventional parallel data transmission. Comparing 1110 and 1120 of FIG. 11, it can be seen that an interface according to the present invention capable of transmitting high-speed serial data of two channels has a transmission bandwidth more than twice that of a conventional interface.

In the present specification, the sensor unit 202 converts m-bit pixel data into an n-bit serial data stream and outputs the same. However, the same may be applied to any device or processor that transmits m-bit parallel data. Of course it is.

12 is a flowchart illustrating a method of outputting m-bit pixel data by a serial transmission method according to an embodiment of the present invention. Hereinafter, the sensor unit 202 uses an image sensor 210 for photographing a subject with a single chip to generate corresponding pixel data, and a first interface unit 220 for converting the pixel data into an n-bit serial data stream. It will be described on the assumption that it is configured to include. In addition, since the components inside the sensor unit 202 are located in the same chip, data may be transmitted in a parallel transmission method, and serial data may be transmitted when a component of another chip (for example, the processor unit 204 is transmitted). Assume that the stream is converted and transmitted.

In operation 1205, the image sensor 210 generates m-bit pixel data corresponding to a subject and synchronizes synchronization signals (eg, a clock signal PCLK, a vertical synchronization signal VSYNC), and valid data synchronized with the corresponding pixel data. The enable signal HREF is generated and output to the first interface unit 220. Here, since the image sensor 210 and the first interface unit 220 are components included in one chip, data may be transmitted using a parallel data transmission method.

In operation 1210, the encoder 310 inserts sync codes set corresponding to sync signals input from the image sensor 210, obtains m-bit pixel data using the sync signals, and then inserts the sync data. A clock signal (ie, a second clock signal) synchronized with the code and the acquired pixel data is generated and output to the serial data converter 320.

As described above, the encoder unit 310 uses the first data bus 341 and the second data bus (in the m-bit unit) to insert pixel data in which a preset synchronization code is inserted into the pixel data input from the image sensor 210. The output may be output to the serial data converter 320 through 342.

For example, when the vertical synchronization signal VSYNC is changed to the first state, the encoder unit 220 inserts the SOF, and when the vertical synchronization signal VSYNC is changed from the low state to the high state (that is, the first state). In the case of two states), the encoder unit 310 inserts an EOF.

In addition, when the valid data enable signal HREF is changed to the second state, the encoder unit 220 inserts an SOL. When the valid data enable signal HREF is changed to the first state, the encoder unit 220 is inserted. ) Can insert an EOL.

If the vertical synchronization signal VSYNC is in the low state and the valid data enable signal HREF is in the valid period, the encoder unit 310 may acquire m-bit pixel data corresponding to the clock signal PCLK. have.

In operation 1215, the serial data converter 320 shifts the inserted sync code and the obtained pixel data by n bits using the input second clock signal to generate n-bit serial data streams, and inputs the input second clock. A third clock signal divided by two signals is generated. The serial data converter 320 outputs the n-bit serial data stream to the differential signal output unit 330 through the plurality of data signal lines, and outputs the third clock signal through the clock signal line to the differential signal output unit 330. Will output

For example, the serial data converter 320 may output bit values at odd positions of the generated n-bit serial data stream through the first data signal line, and output bit values at even positions through the second data signal line. Can

비트씩 시프트시켜 상위

비트의 비트값들은 제1 데이터 신호선을 통해 출력하며, 하위

비트의 비트값들은 제2 데이터 신호선을 통해 출력하도록 할 수도 있다.As another example, the serial data converter 320 may convert m-bit pixel data.

Shift bit by bit

Bit values of the bit are output through the first data signal line,

Bit values of the bit may be output through the second data signal line.

In operation 1220, the differential signal output unit 330 converts the n-bit serial data stream and the third clock signal inputted through the serial data converter 320 into a low voltage differential signal and outputs the low voltage differential signal to the processor unit 204.

FIG. 13 is a flowchart illustrating a method in which a processor converts a serial data stream into parallel data and outputs the parallel data according to an embodiment of the present invention. Hereinafter, it is assumed that the processor unit 204 includes a second interface unit 230 that receives a serial data stream and converts the serial data stream into parallel data and an image signal processor 240 that converts the parallel data into a predetermined image format. This will be described. That is, since the second interface unit 230 and the image signal processor 240 are components included in the same chip, the second interface unit 230 and the image signal processor 240 may transmit data in a parallel transmission method, and components of another chip (for example, the sensor unit 202). In the case of receiving data from)) or transmitting data to another chip component (for example, a baseband processor (not shown)), it is assumed that the data is converted into a serial data stream and transmitted. In the present specification, the processor 204 will be described with emphasis on receiving a serial data stream from the sensor unit 202.

In operation 1305, the differential signal input unit 1010 converts the low voltage differential signal input through the first interface unit 220 into a serial data stream according to the LVCMOS / LVTTL signal and outputs the serial data stream to the parallel data converter 1020.

In operation 1310, the parallel data converter 1020 receives n-bit serial data streams and shifts n bits to generate m-bit parallel data, and generates a fourth clock signal synchronized with the m-bit parallel data to generate a decoder. Output to the unit 1030.

As described above, the parallel data converter 1020 receives the m-bit parallel data through a plurality of data buses (that is, the third data bus 1051 and the fourth data bus 1052). Can be printed as

For example, suppose a serial data stream is a 2-bit bitstream and the parallel data to be generated is m bits. The parallel data converter 1020 may generate m-bit parallel data by shifting the serial data stream input through the differential signal input unit 1010 four times by two bits.

In operation 1315, the decoder 1030 obtains parallel data using a fourth clock signal input through the parallel data converter 1020.

In operation 1320, the decoder 1030 determines whether the obtained parallel data matches any one of predetermined synchronization codes.

If it matches one of the predetermined sync codes, the decoder 1030 generates a sync signal corresponding to the sync code in step 1425 and outputs the sync signal to the image signal processor 240. At this time, the parallel data matched with the sync code is for generating the sync signal and is not output to the image signal processor 240.

However, if one of the predetermined sync codes does not match, the decoder 1030 outputs the obtained parallel data to the image signal processor 240 as m-bit pixel data in step 1320. Of course, the decoder 1030 may generate and output the clock signal PCLK synchronized with the pixel data so that the image signal processor 240 may obtain the pixel data.

As a result, the image signal processor 240 may receive and process pixel data output from the image sensor 210 through the second interface unit 230.

As described above, by providing an interface, an apparatus, and a method for data transmission, the m-bit parallel data is converted into an n-bit serial data stream and then transmitted using a low differential pressure signal to transmit data using a bandwidth. ) Can be expanded about 2 times.

In addition, the present invention can reduce the signal line required for data transmission by transmitting the pixel data using the low pressure differential signal, it is also possible to reduce the strategy consumption.

In addition, the present invention also has the effect of improving the electromagnetic interference (EMI) of the signal line transmitting the data or clock signal by transmitting the pixel data using the low pressure differential signal.

In addition, the present invention facilitates PCB design by reducing internal signal lines required for data transmission, and also reduces costs by reducing the size of cables, PCB traces and connectors.

In addition, the present invention also has the effect of miniaturizing components by reducing the I / O pin by reducing the signal line required for data transmission.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (32)

a data output unit for outputting parallel data of m (any natural number) bits and synchronized synchronization signals; And The parallel data and the synchronization signals are input from the data output unit, and the synchronization codes set corresponding to the synchronization signals are inserted into the parallel data, and converted into a serial data stream of n (arbitrary natural numbers) bits. A first interface portion for generating a clock signal synchronized to the serial data stream, The first interface unit, An encoder unit inserting and outputting the sync code into the parallel data, and generating and outputting a first clock signal synchronized with the parallel data into which the sync code is inserted; And A serial to shift and output the parallel data into which the synchronization code is inserted, by n bits, to the serial data stream in units of n bits, and to generate and output a second clock signal divided by the first clock signal; Includes a data converter, The data output unit and the first interface unit which is any one of a sensor or a processor is provided on the same chip. delete The method of claim 1, And the encoder unit is connected to the serial data converter through a plurality of data buses for outputting parallel data into which the synchronization code is inserted and a first clock signal line for outputting the first clock signal. . The method of claim 1, When the input clock of the encoder is faster than the output clock, the encoder inserts a synchronization code into pre-input pixel data and outputs the serial data converter through one of a first data bus and a second data bus to the serial data converter. And outputting the converted pixel data to the serial data converter through another one of the first data bus and the second data bus by inserting a sync code. The method of claim 1, When the encoder unit temporarily stores the pixel data into which the sync code is inserted in the buffer and then writes a predetermined bit amount, the encoder unit outputs the serial data converter through the first data bus and the second data bus in units of m bits, respectively. A data transmission device, characterized in that. The method of claim 1, When the data output unit is an image sensor that outputs m-bit pixel data corresponding to a subject and corresponding synchronization signals, The synchronization signals are a clock signal PCLK for acquiring the parallel data, a vertical synchronization signal VSYNC for identification of each frame, and a valid data enable signal HREF for identification of a line in each frame. When the vertical sync signal VSYNC is changed to a first state, the encoder inserts a start of frame sync code (SOF) indicating the start of a frame into the parallel data, and the vertical sync signal VSYNC is a second one. When the state is changed, an end of frame sync code (EOF) is inserted into the parallel data indicating the end of the frame. The first state is any one of a falling edge or a rising edge, and the second state is another one of a falling edge or a rising edge. Transmission device. The method of claim 6, When the valid data enable signal HREF is changed to the third state after the vertical synchronization signal VSYNC is changed to the first state, the encoder unit generates a start of line sync code (SOL) indicating the start of a line. Inserting into the parallel data, When the valid data enable signal is changed to the fourth state, an end of line sync code (EOL) indicating end of the line is inserted into the parallel data, And the third state is any one of the first state and the second state, and the fourth state is another one of the first state and the second state. The method of claim 1, And a differential signal output unit configured to convert the serial data stream and the second clock signal into a low pressure differential signal and output the converted signal. And the serial data converter is connected to the differential signal output unit through a plurality of data signal lines for outputting the serial data stream and a clock signal line for outputting the clock signal. The method of claim 8, The serial data converter outputs bit values at odd positions of the serial data stream through a third data signal line, and outputs bit values at even positions to the differential signal output unit through a fourth data signal line. Transmission device. The method of claim 8, The serial data converter may convert pixel data into which the sync code is inserted.

Shift bit by bit

The serial data stream of bits is output via the third data signal line,

And a serial data stream of bits is output to the differential signal output section through a fourth data signal line. Receives an n (random natural number) bit serial data stream and a synchronized clock signal and converts it into m (random natural number) bit parallel data, detects a preset synchronous code, and generates a corresponding synchronous signal. A second interface unit for outputting parallel data from which the synchronization code has been removed; And And a processor configured to receive the parallel data and the synchronization signal through the second interface unit and convert the parallel data and the synchronization signal into a predetermined data format. The second interface unit, A parallel data converter for shifting the serial data stream by the n bits and converting the serial data stream to the m bits of parallel data, and generating and outputting a clock signal synchronized with the parallel data; And A decoder configured to receive the parallel data and the clock signal, detect a sync code set in the parallel data using the clock signal, generate a corresponding sync signal, and generate and output parallel data from which the sync code has been removed; , And the processor and the second interface unit are provided on the same chip. delete The method of claim 11, And the parallel data converter is connected to the decoder through a plurality of data buses for outputting the parallel data and a clock signal line for outputting the clock signal. The method of claim 11, When the input clock of the parallel data converter is faster than the output clock, the parallel data converter converts the pre-input serial data stream into parallel data and outputs the same to the decoder by using one of the first data bus and the second data bus. And converting a post-input serial data stream into parallel data and outputting the serial data stream to the decoder by using another one of a first data bus and a second data bus. The method of claim 11, When the parallel data converter temporarily stores the parallel data in a buffer and satisfies a predetermined bit amount, the parallel data converter performs parallel transmission on the first data bus and the second data bus by m bits in parallel data stored in the buffer. And data output to the decoders, respectively. The method of claim 11, The decoder generates and outputs a vertical synchronizing signal VSYNC changed to a first state when the converted parallel data is SOF, and outputs a vertical synchronizing signal VSYNC changed to a second state when the converted parallel data is EOF. Create and print, The first state is any one of a falling edge or a rising edge, and the second state is another one of a falling edge or a rising edge. Receiving device. The method of claim 16, The decoder generates and outputs a valid data enable signal HREF converted to the third state when the converted parallel data is SOL, and valid data converted to the fourth state when the converted parallel data is EOL. Generate and output the enable signal (HREF), The third state is any one of the first state and the second state, and the fourth state is another one of the first state and the second state. The method of claim 11, And a differential signal input unit configured to receive the low differential pressure signal and convert the low pressure differential signal into the serial data stream. And the serial data converter is connected to the differential signal input unit through a plurality of data signal lines for inputting the serial data stream and one clock signal line for inputting the clock signal. The method of claim 18, The serial data converting unit receives a bit value of an odd position of the serial data stream through a first data signal line, receives a bit value of an even position of the serial data stream through a second data signal line, and converts the bit value into the parallel data. Data receiving apparatus, characterized in that. The method of claim 18, The serial data converter is higher than the serial data stream through a first data signal line.

Receive bit values of a bit, and subordinate the serial data stream through a second data signal line

And receiving bit values of a bit into the parallel data. a data transmission device for converting parallel data of m (any natural number) bits into a serial data stream of n (any natural number) bits; And And a data receiving device receiving the serial data stream and converting the serial data stream into parallel data. The data transmission device,  a data output unit for outputting synchronization signals synchronized with parallel data of m (any natural number) bits; And Receiving the parallel data and the synchronization signal from the data output unit, inserting synchronization codes set corresponding to the synchronization signals into the parallel data, converting the serial data stream into the n-bit serial data, and outputting the serial data; A first interface unit generating and outputting a clock signal synchronized with the stream; The data receiving device, Receives the n-bit serial data stream and the synchronized clock signal and converts them into the m-bit parallel data, detects a preset sync code to generate a corresponding sync signal, and removes the sync code. A second interface unit for outputting a; And And a processor configured to receive the parallel data and the synchronization signal through the second interface unit and convert the parallel data and the synchronization signal into a predetermined data format. The data output unit and the first interface unit, which are either the sensor or the processor, are provided on the same chip. And the second interface unit and the processor are provided on the same chip. delete In the method for transmitting data in the first interface unit provided on the same chip as the data output unit which is either a sensor or a processor, Receiving m (random natural number) bits of parallel data and synchronized synchronization signals from the data output unit; Inserting and outputting sync codes set corresponding to the sync signals into the parallel data, and generating and outputting a first clock signal synchronized with the parallel data into which the sync codes are inserted; And Shifting the parallel data into which the sync codes are inserted and converting the data into a serial data stream by n bits (random natural numbers), and generating and outputting a second clock signal synchronized with the serial data stream. Data transmission method. The method of claim 23, wherein Inserting and outputting the synchronization codes set corresponding to the synchronization signals into the parallel data, Temporarily storing parallel data having a synchronization code inserted in the buffer; Determining whether parallel data in which a sync code is inserted is stored in the buffer by an area having a predetermined size; And Outputting the parallel data into which the stored synchronization code is inserted to the serial data converter through the first data bus and the second data bus in units of m bits when the data is stored in a predetermined sized area. Transmission method. The method of claim 24, When the data output unit is an image sensor that outputs m-bit pixel data corresponding to a subject and corresponding synchronization signals, The sync signals are a clock signal PCLK for acquiring the parallel data, a vertical sync signal VSYNC for identification of each frame, and a valid data enable signal HREF for identification of a line in each frame. The data transmission method. The method of claim 25, Outputting parallel data into which the sync codes are inserted may include: Inserting a start of frame sync code (SOF) set to the parallel data when the vertical synchronization signal VSYNC is in a first state; If the vertical synchronization signal is in the second state, inserting an end of frame sync code (EOF) set corresponding to the end of the frame into the parallel data; If the valid data enable signal (HREF) is in a third state, inserting a start of line sync code (SOL) corresponding to the start of a line into the parallel data; And If the valid data enable signal HREF is in a fourth state, inserting an end of line sync code (EOL) set to correspond to the end of a line into the parallel data, The first state is either a falling edge or a rising edge, and the second state is the other of a falling edge or a rising edge, And wherein the third state is one of the first state and the second state, and the fourth state is the other of the first state and the second state. The method of claim 24, Converting and outputting the serial data stream, Outputting bit values of odd positions of the serial data stream via a third data signal line; And Outputting bit values of even positions of the serial data stream via a fourth data signal line. The method of claim 24, An upper portion of the serial data stream via a third data signal line

Outputting bit values of the bit; And A lower portion of the serial data stream via a fourth data signal line

Outputting the bit values of the bit. A method for receiving data by a second interface unit included in the same chip as a processor that acquires parallel data of m (arbitrary natural numbers) and converts it into a predetermined data format, Converting and outputting an input n (random natural number) bit serial data stream and a synchronized first clock signal; Shifting the serial data stream by the n bits to generate and output the m-bit parallel data, and generating and outputting a second clock signal synchronized to the parallel data; And Detecting the sync codes set in the parallel data by using the second clock signal to generate and output corresponding sync signals, and outputting parallel data from which the sync codes have been removed. The method of claim 29, The step of shifting by n bits to generate and output the parallel data, Temporarily storing the parallel data in a buffer; Determining whether parallel data are stored by an area of a predetermined size of the buffer; And If the data is stored in a predetermined area, outputting the stored parallel data to the decoder through the first data bus and the second data bus in units of m bits. The method of claim 29, Detecting the sync codes set in the parallel data to generate and output corresponding sync signals, Generating and outputting a vertical synchronization signal VSYNC changed to a first state and a valid data enable signal HREF changed to a third state if the parallel data is the SOF; Generating and outputting a vertical synchronization signal changed to a second state and a valid data enable signal changed to a fourth state if the parallel data is the EOF; Generating and outputting a valid data enable signal changed to the third state if the parallel data is the SOL; And If the parallel data is the EOL, generating and outputting a valid data enable signal changed to the fourth state; The first state is any one of a falling edge and a rising edge, and the second state is the other of a falling edge and a rising edge, The third state is any one of the first state and the second state, and the fourth state is another one of the first state and the second state. The method of claim 29, The step of shifting by n bits to generate and output the parallel data, Receiving n-bit bit values through the third data signal line and the fourth data signal line, respectively; And And shifting and inputting the input bit value by n bits in a predetermined order, respectively, to generate and output the parallel data.

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