CN215834688U - Low-temperature co-fired ceramic power divider - Google Patents
Low-temperature co-fired ceramic power divider Download PDFInfo
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- CN215834688U CN215834688U CN202122346091.2U CN202122346091U CN215834688U CN 215834688 U CN215834688 U CN 215834688U CN 202122346091 U CN202122346091 U CN 202122346091U CN 215834688 U CN215834688 U CN 215834688U
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Abstract
The utility model belongs to the field of power amplifiers, and particularly relates to a low-temperature co-fired ceramic power divider which comprises a ceramic substrate, a signal input end electrode, a first signal output end electrode, a second signal output end electrode, a third signal output end electrode, a fourth signal output end electrode, a power distribution circuit and an isolation resistor, wherein the signal input end electrode, the first signal output end electrode, the second signal output end electrode, the third signal output end electrode and the fourth signal output end electrode are arranged on the surface of the ceramic substrate. According to the low-temperature co-fired ceramic power divider, the isolation resistor is printed on the ceramic substrate by adopting a thick film process, so that the product is small in size, high in integration level, light in weight, enhanced in environmental adaptability and high in reliability.
Description
Technical Field
The utility model relates to the technical field of power dividers, in particular to a low-temperature co-fired ceramic power divider
Background
With the rapid development of microwave technology, radio frequency terminal equipment is developed towards passive integration design with low cost, high performance, miniaturization and light weight. The power divider is an important microwave passive device in radio frequency and microwave circuits, and is a device for dividing one path of input signal energy into two or more paths of output signal energy, wherein the four paths of power dividers are devices for dividing one path of input signal energy into four paths of output signal energy, and a good power divider requires a wider working frequency band, small insertion loss, good amplitude and phase consistency of four paths of signals, and high isolation between the four paths of signals. In addition, the volume of the power divider is as small as possible, which is a demand for the development of electronic systems toward miniaturization and light weight.
At present, most merit divides the ware to need external isolation resistor, through with a plurality of discrete resistance table pastes the mode welding on merit divides the ware surface or PCB board, the reliability and the environmental suitability of ware are divided to the welding process's thermal shock can be reduced to the merit, also can increase the thickness that the ware was divided to the merit simultaneously, leads to the merit to divide the ware bulky.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a low-temperature co-fired ceramic power divider, which is used for solving the problems that a plurality of discrete resistors are welded on the surface of the power divider or a PCB in a surface-mounted mode, thermal shock in the welding process easily damages a ceramic substrate, the reliability and the environmental adaptability of the power divider can be reduced, and the thickness of the power divider can be increased to cause the large volume of the power divider.
To this end, according to one aspect of the present application, there is provided a low temperature co-fired ceramic power divider comprising:
a ceramic substrate;
a signal input terminal electrode, a first signal output terminal electrode, a second signal output terminal electrode, a third signal output terminal electrode and a fourth signal output terminal electrode which are arranged on the surface of the ceramic substrate;
the power distribution circuit is embedded in the ceramic substrate and is used for distributing signal energy input by the signal input end electrode to the first signal output end electrode, the second signal output end electrode, the third signal output end electrode and the fourth signal output end electrode;
the first isolation resistor is connected between the second signal output end electrode and the third signal output end electrode;
the second isolation resistor is connected between the first signal output end electrode and the second signal output end electrode; and
the third isolation resistor is connected between the third signal output end electrode and the fourth signal output end electrode;
the first isolation resistor, the second isolation resistor and the third isolation resistor are printed on the surface of the ceramic substrate through a thick film process.
The application provides a ware is divided to low temperature ceramic merit altogether's beneficial effect lies in: compared with the prior art, the low-temperature co-fired ceramic power divider has the advantages that the isolation resistor is printed on the ceramic substrate by adopting a thick film process, the product size is small, the integration level is high, the weight is light, the environmental adaptability is enhanced, and the reliability is high.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
FIG. 1 is a schematic circuit diagram of a low temperature co-fired ceramic power divider according to an embodiment of the present invention;
FIG. 2 is a schematic product shape diagram of a low-temperature co-fired ceramic power divider according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a low-temperature co-fired ceramic power divider according to an embodiment of the present invention;
FIG. 4 is a schematic top view illustrating the overall structure of a low-temperature co-fired ceramic power divider according to an embodiment of the present invention;
FIG. 5 is a schematic side view of the overall structure of a LTCC power divider according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a first electrode pattern of a low-temperature co-fired ceramic power divider according to an embodiment of the utility model;
FIG. 7 is a schematic diagram of a second electrode pattern of a low temperature co-fired ceramic power divider according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a third electrode pattern of the low-temperature co-fired ceramic power divider according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating a fourth electrode pattern of the low-temperature co-fired ceramic power divider according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a terminal electrode pattern of a LTCC power divider according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of an end-side electrode pattern of a low-temperature co-fired ceramic power divider according to an embodiment of the present invention;
FIG. 12 is a graph illustrating the insertion loss of a LTCC power divider according to an embodiment of the present invention;
FIG. 13 is a graph of voltage standing wave ratio of a LTCC power divider according to an embodiment of the present invention;
FIG. 14 is a graph illustrating isolation of a LTCC power divider according to an embodiment of the present invention;
fig. 15 is a graph illustrating amplitude balance of a low-temperature co-fired ceramic power divider according to an embodiment of the present invention.
Description of the main element symbols:
100. a ceramic substrate;
p1, a first ground terminal electrode; p2, a second ground terminal electrode; p3, signal input terminal electrode; p4, a third ground terminal electrode; p5, a fourth ground terminal electrode; p6, a first signal output terminal electrode; p7, a second signal output terminal electrode; p8, a fifth ground terminal electrode; p9, a third signal output terminal electrode; p10, a fourth signal output terminal electrode;
p11, eleventh electrode; p12, twelfth electrode; p21, twenty-first electrode; p22, a twenty-second electrode; p31, thirty-first electrode; p32, thirty-second electrode; p41, a forty-first electrode; p42, a forty-second electrode; p51, fifty-first electrode; p52, fifty-second electrode; p61, sixty-first electrode;
p62, sixty-second electrode; p71, seventy-first electrode; p72, seventy-second electrode; p81, eighty-first electrode; p82, eighty-second electrode; p91, the ninety first electrode; p92, a ninety second electrode; p101, a first hundred and zero electrodes; p102, a first hundred and two electrodes;
r1, a first isolation resistor; r2 and a second isolation resistor; r3, third isolation resistance;
l1, a first inductor; l2, a second inductor; l3, third inductance; l4, fourth inductance; l5, fifth inductance; l6, sixth inductance;
a1, a first surface electrode; a2, a second surface electrode; a3, a third surface electrode; b1, fourth surface electrode; b2, fifth surface electrode; b3, a sixth surface electrode; b4, a seventh surface electrode; b5, eighth surface electrode; b6, ninth surface electrode;
c1, a first capacitance; c11, a first capacitive electrode; c2, a second capacitor; c21, a second capacitive electrode; c3, a third capacitance; c4, a fourth capacitance; c5, a fifth capacitance; c6, a sixth capacitor; c7, a seventh capacitance; c71, a seventh capacitive electrode; c72, a seventh capacitive electrode; c8, an eighth capacitor; c81, an eighth capacitive electrode; c82, an eighth capacitive electrode;
G. a ground electrode; s1, a first transmission line; s1, a second transmission line; s3, a third transmission line; s4, a fourth transmission line;
k1, a first electrical connection hole post; k2, a second electrical connection hole post; k3, a third electrical connection hole post; k4, a fourth electrical connection hole post; k5, a fifth electrical connection hole post; k6, a sixth electrical connection hole post; k7, a seventh electrical connection hole post; k8, eighth electrical connection hole post; k9, ninth electrical connection hole post; k10, tenth electrical connection hole post; k11, eleventh electrically connecting via post; k12, a twelfth electric connection hole column; k13, a thirteenth electrical connection hole post; k14, a fourteenth electrically connecting hole post; k15, a fifteenth electrical connection hole post; k16, sixteenth electrically connecting hole post; k17, seventeenth electrical connection hole post; k18, eighteenth electric connection hole column; k19, nineteenth electrical connection hole post; k20, twentieth electrical connection hole post; k21, twenty-first electrical connection hole post; k22, a twenty-second electrical connection hole post; k23, a twenty-third electrical connection hole post; k24, a twenty-fourth electrical connection hole post; k25, twenty-fifth electric connection hole column; k26, a twenty-sixth electrical connection hole post; k27, twenty-seventh electrical connection hole column; k28, twenty-eighth electrical connection hole post; k29, a twenty ninth electrical connection hole post.
Detailed Description
To facilitate an understanding of the utility model, the utility model will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As described in the background art, currently, most power dividers need to be externally connected with isolation resistors, and a plurality of discrete resistors are welded on the surface of the power divider or a PCB in a surface-mount manner, so that the reliability and environmental adaptability of the power divider can be reduced due to thermal shock in the welding process, and meanwhile, the thickness of the power divider can be increased, which results in a large volume of the power divider.
In order to solve the above problem, according to an aspect of the present application, an embodiment of the present application provides a low-temperature co-fired ceramic power divider, which is configured to print isolation resistors on a ceramic substrate by a thick film process, so that the product has a small volume, high integration level, light weight, enhanced environmental adaptability, and high reliability. The antenna can be applied to the fields of microwave communication, radar navigation, satellite communication, automotive electronics, electronic countermeasure and the like, and meets the requirements of miniaturization, high reliability, high performance and patch installation.
In the embodiment of the present invention, as shown in fig. 1 to 4, the low-temperature co-fired ceramic power divider includes a ceramic substrate 100, a signal input terminal electrode P3, a first signal output terminal electrode P6, a second signal output terminal electrode P7, a third signal output terminal electrode P9, a fourth signal output terminal electrode P10, a power distribution circuit, a first isolation resistor R1, a second isolation resistor R2, and a third isolation resistor R3. The signal input terminal electrode P3, the first signal output terminal electrode P6, the second signal output terminal electrode P7, the third signal output terminal electrode P9 and the fourth signal output terminal electrode P10 are all disposed on the surface of the ceramic substrate 100; the power distribution circuit is embedded in the ceramic substrate 100 and is used for distributing the input signal energy of the signal input end electrode P3 to the first signal output end electrode P6, the second signal output end electrode P7, the third signal output end electrode P9 and the fourth signal output end electrode P10; the first isolation resistor R1, the second isolation resistor R2 and the third isolation resistor R3 are printed on the surface of the ceramic substrate 100 through a thick film process, the first isolation resistor R1 is connected between the second signal output terminal electrode P7 and the third signal output terminal electrode P9, and the second isolation resistor R2 is connected between the first signal output terminal electrode P6 and the second signal output terminal electrode P7; the third isolation resistor R3 is connected between the third signal output terminal electrode P9 and the fourth signal output terminal electrode P10.
In the embodiment of the utility model, the low-temperature co-fired ceramic power divider integrates the isolation resistor on the ceramic substrate 100 by adopting a thick film process, so that the whole power divider product has the advantages of small volume, high integration level, light weight, enhanced environmental adaptability and high reliability.
Specifically, the power distribution circuit includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5 and a sixth inductor L6, an input end of the first inductor L1 and an input end of the second inductor L2 are commonly connected to a signal input terminal electrode P3, an input end of a third inductor L3 and an input end of the fourth inductor L4 are commonly connected to an output end of the first inductor L1, an input end of the fifth inductor L5 and an input end of the sixth inductor L6 are commonly connected to an output end of the second inductor L2, an output end of the third inductor L3 is connected to a first signal output terminal electrode P6, an output end of the fourth inductor L4 is connected to a second signal output terminal electrode P7, an output end of the fifth inductor L5 is connected to a third signal output terminal electrode P9, and an output end of the sixth inductor L6 is connected to a fourth signal output terminal electrode P10; the first isolation resistor R1 is connected between the output terminal of the first inductor L1 and the output terminal of the second inductor L2, the second isolation resistor R2 is connected between the output terminal of the third inductor L3 and the output terminal of the fourth inductor L4, and the third isolation resistor R3 is connected between the output terminal of the fifth inductor L5 and the output terminal of the sixth inductor L6.
It can be understood that, a first isolation resistor R1 is disposed between the output terminal of the first inductor L1 and the output terminal of the second inductor L2, since the resistance of the first isolation resistor R1 is very high and the signal passing through the first inductor L1 and the second inductor L2 is weak, so that the first isolation resistor R1 can isolate the signal between the output terminal of the first inductor L1 and the output terminal of the second inductor L2, a second isolation resistor R2 disposed between the output terminal of the third inductor L3 and the output terminal of the fourth inductor L4 can isolate the signal between the output terminal of the third inductor L3 and the output terminal of the fourth inductor L4, and a voltage difference between the output terminal of the third inductor L3 and the output terminal of the fourth inductor L4 can be eliminated by the second isolation resistor R2, so that the output terminal of the third inductor L3 and the signal of the fourth inductor L4 are identical, and similarly, a fifth isolation resistor R5857324 disposed between the output terminal of the fifth inductor L395 and the sixth inductor L6 can isolate the output terminal of the third inductor L3 from each other The signals between the output terminal of the L5 and the output terminal of the sixth inductor L6 are isolated from each other, and the third isolation resistor R3 can also eliminate the voltage difference between the output terminal of the fifth inductor L5 and the output terminal of the sixth inductor L6, so that the signals at the output terminals of the fifth inductor L5 and the output terminal of the sixth inductor L6 are consistent. Through adopting thick film technology printing integration with the isolation resistance on ceramic base member 100, not only make whole merit divide the ware product small, the integrated level is high, light in weight, environmental adaptability reinforcing, the reliability is high, simultaneously, the mode fine tuning resistance that cooperates the laser to transfer hinders makes the isolation resistance precision high, and each way output signal uniformity is good.
In an embodiment, as shown in fig. 3 to 4 and 7, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5 and the sixth inductor L6 are all planar spiral inductors, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5 and the sixth inductor L6 are disposed on the same plane, the first inductor L1 and the second inductor L2 are disposed in a mirror symmetry manner, the third inductor L3 and the fourth inductor L4 are disposed in a mirror symmetry manner, and the fifth inductor L5 and the sixth inductor L6 are disposed in a mirror symmetry manner with the third inductor L3 and the fourth inductor L4.
The six planar spiral inductors are arranged on the same plane, so that the number of layers occupied by longitudinal space can be reduced, the forming process is simplified, the miniaturization of the power divider is realized, and a compact structure is formed. Meanwhile, the parasitic capacitance of the inductor can be reduced by adopting the planar spiral inductor at high frequency.
In one embodiment, as shown in fig. 1-4, the power distribution circuit further includes a seventh capacitor C7 and an eighth capacitor C8, the seventh capacitor C7 being connected between the first signal output terminal electrode P6 and the second signal output terminal electrode P7, and the eighth capacitor C8 being connected between the third signal output terminal electrode P9 and the fourth signal output terminal electrode P10.
By providing the seventh capacitor C7 between the first signal output terminal electrode P6 and the second signal output terminal electrode P7, and the eighth capacitor C8 between the third signal output terminal electrode P9 and the fourth signal output terminal electrode P10, the isolation and the amplitude balance between the output ports can be improved.
Specifically, as shown in fig. 7-8, the seventh capacitor C7 is a plate capacitor formed by two metal surfaces, the seventh capacitor C7 is composed of a seventh first capacitor electrode C71 and a seventh second capacitor electrode C72, and the thickness of the ceramic dielectric layer is 40-50 μm; the eighth capacitor C8 is a plate capacitor formed by two metal surfaces, the eighth capacitor C8 is composed of an eighth capacitor electrode C81 and an eighth capacitor electrode C82, and the thickness of the ceramic dielectric layer is 40-50 μm.
In one embodiment, as shown in fig. 1-4 and fig. 7-9, the low-temperature co-fired ceramic power divider further includes a ground electrode G, a first capacitive electrode C11, and a second capacitive electrode C21, wherein the ground electrode G is a grid-like planar structure.
The first capacitor electrode C11 is connected to the input terminal of the first inductor L1 and spaced from the ground electrode G to form a first capacitor C1, and the second capacitor electrode C21 is connected to the input terminal of the second inductor L2 and spaced from the ground electrode G to form a second capacitor C2.
The third inductor L3, the fourth inductor L4, the fifth inductor L5, and the sixth inductor L6 respectively generate a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6 with the ground electrode G at high frequency.
Through the arrangement of the six capacitors playing a role of bypass, the four-path power divider has the performances of better phase balance degree and low insertion loss.
Specifically, the thickness of the ceramic dielectric layer between the first capacitance electrode C11 and the ground electrode G and between the second capacitance electrode C21 and the ground electrode G is 40-50 μm.
In a more specific embodiment, as shown in fig. 1 to 4, the low-temperature co-fired ceramic power divider further includes a first ground terminal electrode P1, a second ground terminal electrode P2, a third ground terminal electrode P4, a fourth ground terminal electrode P5, and a fifth ground terminal electrode P8, wherein the ground electrode G is respectively connected to the first ground terminal electrode P1, the second ground terminal electrode P2, the third ground terminal electrode P4, the fourth ground terminal electrode P5, and the fifth ground terminal electrode P8 in a one-to-one correspondence manner through a twenty-fourteen electrical connection hole pillar K24, a twenty-third electrical connection hole pillar K23, a twenty-second electrical connection hole pillar K22, a twenty-first electrical connection hole pillar K21, and a twenty-ninth electrical connection hole pillar K29.
By designing the ground electrode G to have a gridded planar structure, the generation of parasitic capacitance at high frequencies can be reduced.
Further, a first ground terminal electrode P1, a second ground terminal electrode P2, a signal input terminal electrode P3, a third ground terminal electrode P4 and a fourth ground terminal electrode P5 are disposed on one side of the ceramic body 100, and are sequentially disposed at equal intervals along the length direction of the ceramic body 100; the first signal output terminal electrode P6, the second signal output terminal electrode P7, the fifth ground terminal electrode P8, the third signal output terminal electrode P9 and the fourth signal output terminal electrode P10 are sequentially disposed on the other side of the ceramic substrate 100 at equal intervals.
Ten terminal electrodes are uniformly and symmetrically distributed on two sides of the ceramic substrate 100, four of the terminal electrodes are signal output terminal electrodes on the same side, four of the terminal electrodes are ground terminal electrodes on the same side as the signal input terminal electrode P3, and the signal input terminal electrode P3 is disposed between the four ground terminal electrodes. By the design, the positions of the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the isolation resistors and the capacitors can be better arranged, the number of the electric connection hole columns and the number of the printed circuits are reduced, devices are separated, the mutual influence among the devices is reduced, the insertion loss is reduced, and better phase balance and high isolation are guaranteed.
In an embodiment, as shown in fig. 6 to 7, the low-temperature co-fired ceramic power divider further includes surface electrodes disposed on one side of the ceramic substrate 100 printed with the isolation resistors, where the surface electrodes include a fourth surface electrode B1, a fifth surface electrode B2, a sixth surface electrode B3, a seventh surface electrode B4, an eighth surface electrode B5, and a ninth surface electrode B6;
the fourth surface electrode B1 and the fifth surface electrode B2 are connected through a first isolation resistor R1, the first inductor L1 is connected to the fourth surface electrode B1 through a first electrical connection hole pillar K1, the second inductor L2 is connected to the fifth surface electrode B2 through a fifth electrical connection hole pillar K5, the fourth surface electrode B1 is connected to the third inductor L3 and the fourth inductor L4 through a second electrical connection hole pillar K2, and the fifth surface electrode B2 is connected to the fifth inductor L5 and the sixth inductor L6 through a sixth electrical connection hole pillar K6;
the sixth surface electrode B3 and the seventh surface electrode B4 are connected through a second isolation resistor R2, the third inductor L3 is connected to the sixth surface electrode B3 through a third electrical connection hole pillar K3, and the fourth inductor L4 is connected to the seventh surface electrode B4 through a fourth electrical connection hole pillar K4;
the eighth surface electrode B5 and the ninth surface electrode B6 are connected through a third isolation resistor R3, the fifth inductor L5 is connected to the eighth surface electrode B5 through a seventh electrical connection hole pillar K7, and the sixth inductor L6 is connected to the ninth surface electrode B6 through an eighth electrical connection hole pillar K8.
By providing surface electrodes, it is convenient to connect the isolation resistors to the inductors in the power distribution circuit.
In a specific embodiment, as shown in fig. 6, the surface electrodes further include a first surface electrode a1, a second surface electrode a2, and a third surface electrode A3, the first isolation resistor R1 sequentially connects the fourth surface electrode B1, the first surface electrode a1, and the fifth surface electrode B2 in series, and the second isolation resistor R2 sequentially connects the sixth surface electrode B3, the second surface electrode a2, and the seventh surface electrode B4 in series; the eighth surface electrode B5, the third surface electrode A3 and the ninth surface electrode B6 are connected in series in sequence by a third isolation resistor R3.
By arranging the first surface electrode A1, the second surface electrode A2 and the third surface electrode A3, resistance measurement and resistance trimming of the first isolation resistor R1, the second isolation resistor R2 and the third isolation resistor R3 during resistance trimming through laser are facilitated.
In a more specific embodiment, as shown in fig. 1 to 9, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5 and the sixth inductor L6 all adopt planar spiral inductors, six planar spiral inductors are arranged on the same plane, the first inductor L1 and the second inductor L2 are arranged in a mirror symmetry manner, the signal input terminal electrode P3 is connected to the first inductor L1 through the thirteenth electrical connection hole pillar K13 and the ninth electrical connection hole pillar K9, and the signal input terminal electrode P3 is electrically connected to the second inductor L2 through the fourteenth electrical connection hole pillar K14 and the tenth electrical connection hole pillar K10;
the third inductor L3 and the fourth inductor L4 are arranged in mirror symmetry, the fifth inductor L5 and the sixth inductor L6 are arranged in mirror symmetry with the third inductor L3 and the fourth inductor L4, the sixth surface electrode B3 is connected to the first transmission line S1 through a seventeenth electric connection hole column K17, the other end of the first transmission line S1 is connected to the first signal output terminal electrode P6 through a twenty fifth electric connection hole column K25, the seventh surface electrode B4 is connected to the second transmission line S2 through an eighteenth electric connection hole column K18, and the other end of the second transmission line S2 is connected to the second signal output terminal electrode P7 through a twenty sixth electric connection hole column K26; the eighth surface electrode B5 is connected to the third transmission line S3 through a nineteenth electrical connection post K19, the other end of the third transmission line S3 is connected to the third signal output terminal electrode P9 through a twenty-seventh electrical connection post K27, the ninth surface electrode B6 is connected to the fourth transmission line S4 through a twentieth electrical connection post K20, and the other end of the fourth transmission line S4 is connected to the fourth signal output terminal electrode P10 through a twenty-eighteenth electrical connection post K28.
Further, the relative dielectric constant of the ceramic substrate 100 is 7.6-8.2, the dielectric loss tan alpha is less than or equal to 0.001, the power distribution circuit is made of silver, and each end of the power distribution circuit is composed of three layers of structures, including an inner silver layer, an intermediate nickel layer, an outermost tin-lead layer, and a surface sealing cover protective glaze of the isolation resistor.
By adopting the material with low dielectric constant and matching with the design of the planar spiral inductor and the grounding electrode G with a gridding planar structure, the parasitic capacitance at high frequency can be reduced, so that the relative bandwidth is wider at high frequency.
The utility model adopts LTCC (low temperature co-fired ceramic) process to manufacture a miniaturized low temperature co-fired ceramic power divider, an isolation resistor is printed and integrated on the surface of a ceramic substrate 100 through thick film process, the passband frequency of the four-way power divider is 1000-2000MHz, the passband bandwidth is 1GHz, the relative bandwidth is up to 66%, the passband bandwidth is wider, as shown in figures 12-15, the total insertion loss is less than or equal to 6.7dB, the insertion loss of output signals is small, the voltage standing wave ratio (1) is less than or equal to 1.6, the standing wave ratio is smaller, the isolation is more than or equal to 11.5dB, the isolation between ports is good, the amplitude balance is less than or equal to 0.5dB, and the amplitude balance is good. The radio frequency system terminal has the advantages of good consistency, high precision, small volume, low cost, high reliability, good temperature stability, strong environment adaptability and the like, and is widely applied to the field of radio frequency system terminals.
According to another aspect of the application, the embodiment of the application also provides a preparation method of the low-temperature co-fired ceramic power divider.
In one embodiment, the preparation method comprises the following steps:
preparing a ceramic body: the method comprises the following steps of preparing a ceramic body by using a low-temperature co-fired ceramic technology, wherein a signal input end electrode P3, a first signal output end electrode P6, a second signal output end electrode P7, a third signal output end electrode P9 and a fourth signal output end electrode P10 are arranged on the surface of the ceramic body, and a power distribution circuit for distributing input signal energy of the signal input end electrode P3 to the first signal output end electrode P6, the second signal output end electrode P7, the third signal output end electrode P9 and the fourth signal output end electrode P10 is embedded in the ceramic body;
preparing an isolation resistor: respectively printing resistance slurry on the surface of a ceramic body to form a first isolation resistor R1, a second isolation resistor R2 and a third isolation resistor R3, wherein the first isolation resistor R1 is connected between a second signal output terminal electrode P7 and a third signal output terminal electrode P9, the second isolation resistor R2 is connected between a first signal output terminal electrode P6 and a second signal output terminal electrode P7, and the third isolation resistor R3 is connected between a third signal output terminal electrode P9 and a fourth signal output terminal electrode P10;
laser resistance adjustment: the first isolation resistor R1, the second isolation resistor R2 and the third isolation resistor R3 are trimmed by laser.
According to the preparation method of the low-temperature co-fired ceramic power divider, the isolation resistor is printed on the ceramic substrate 100 by adopting a thick film process, and the resistor is finely adjusted by adopting a laser resistance adjusting mode, so that the isolation resistor is high in precision, good in consistency of each path of output signals, small in product size, high in integration level, light in weight, enhanced in environmental adaptability and high in reliability.
Specifically, the power distribution circuit includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, and a sixth inductor L6, an input end of the first inductor L1 is connected to an input end of the second inductor L2 and then connected to the signal input terminal electrode P3, an input end of the third inductor L3 is connected to an input end of the fourth inductor L4 and then connected to an output end of the first inductor L1, an input end of the fifth inductor L5 is connected to an input end of the sixth inductor L6 and then connected to an output end of the second inductor L2, an output end of the third inductor L3 is connected to the first signal output terminal electrode P6, an output end of the fourth inductor L4 is connected to the second signal output terminal electrode P7, an output end of the fifth inductor L5 is connected to the third signal output terminal electrode P9, and an output end of the sixth inductor L6 is connected to the fourth signal output terminal electrode P10. The first isolation resistor R1 is connected between the output terminal of the first inductor L1 and the output terminal of the second inductor L2, the second isolation resistor R2 is connected between the output terminal of the third inductor L3 and the output terminal of the fourth inductor L4, and the third isolation resistor R3 is connected between the output terminal of the fifth inductor L5 and the output terminal of the sixth inductor L6.
In one embodiment, preparing the ceramic body comprises the steps of:
preparing a forming auxiliary material layer and a ceramic substrate 100 material layer: the forming auxiliary material layer is a first medium carbon film layer which is prepared by carbon powder slurry and has the thickness of 30-50 mu m, and the ceramic substrate 100 material layer comprises a second medium blank layer which is prepared by the ceramic slurry and has the thickness of 900-1000 mu m, a third medium blank layer which is prepared by the ceramic slurry and has the thickness of 40-50 mu m, a fourth medium blank layer which is prepared by the ceramic slurry and has the thickness of 40-50 mu m, and a fifth medium blank layer which is prepared by the ceramic slurry and has the thickness of 20-30 mu m;
punching: a plurality of electric connecting holes are formed in the second dielectric body layer, the third dielectric body layer, the fourth dielectric body layer and the fifth dielectric body layer, and the aperture of each electric connecting hole is 240-;
molding: printing a first electrode pattern with a thickness of 8-12 μm on one surface of the first dielectric carbon film layer by using silver paste, as shown in fig. 6, wherein the first electrode pattern comprises a first surface electrode a1, a second surface electrode a2, a third surface electrode A3, a fourth surface electrode B1, a fifth surface electrode B2, a sixth surface electrode B3, a seventh surface electrode B4, an eighth surface electrode B5 and a ninth surface electrode B6;
laminating a second dielectric green body layer on one side of the first dielectric carbon film layer, where the first electrode pattern is formed, filling an electrical connection hole in the second dielectric green body layer by silver paste printing to form an electrical connection hole pillar, printing a second electrode pattern with a thickness of 8-12 μm by silver paste on one side of the second dielectric green body layer, which is away from the first electrode pattern, as shown in fig. 7, where the second electrode pattern includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh capacitor electrode C71 and an eighth capacitor electrode C81, an output end of the first inductor L1 is connected to the fourth surface electrode B1 through a first electrical connection hole pillar K1, an output end of the second inductor L2 is connected to a fifth surface electrode inductor B2 through a fifth electrical connection hole pillar K5, an output end of the third inductor L3 is connected to a sixth surface electrode B3 through a third electrical connection hole pillar K3, an output end of a fourth inductor L4 is connected to a seventh surface electrode B4 through a fourth electrical connection hole pillar K4, an input end of a third inductor L3 and an input end of a fourth inductor L4 are connected to form a common connection point and then are connected to a fourth surface electrode B1 through a second electrical connection hole pillar K2, an output end of a fifth inductor L5 is connected to an eighth surface electrode B5 through a seventh electrical connection hole pillar K7, an output end of a sixth inductor L6 is connected to a ninth surface electrode B6 through an eighth electrical connection hole pillar K8, an input end of a fifth inductor L5 and an input end of a sixth inductor L6 are connected to form a common connection point and then are connected to a fifth surface electrode B2 through a sixth electrical connection hole pillar K6;
laminating a third dielectric green body layer on one surface of the second dielectric carbon film layer, which is provided with the second electrode pattern, printing and filling an electric connection hole on the third dielectric green body layer by using silver paste to form an electric connection hole column, printing a third electrode pattern with the thickness of 8-12 microns on one surface of the third dielectric green body layer, which is far away from the second electrode pattern, by using silver paste, as shown in fig. 8, wherein the third electrode pattern comprises a first capacitor electrode C11, a second capacitor electrode C21, a seventh capacitor electrode C72 and an eighth capacitor electrode C82, the first capacitor electrode C11 is connected with the second capacitor electrode C21, the first capacitor electrode C11 is connected with the first inductor L1 through a ninth electric connection hole column K9, and the second capacitor electrode C21 is connected with the second inductor L2 through a tenth electric connection hole column K10; the seventh capacitor electrode C72 and the seventh capacitor electrode C71 form a seventh capacitor C7, and the eighth capacitor electrode C82 and the eighth capacitor electrode C81 form an eighth capacitor C8;
laminating a fourth dielectric blank layer on the third dielectric layer with the third electrode pattern, and using silver paste
Printing electrical connection holes filled in the fourth dielectric green layer to form electrical connection hole pillars, printing a fourth electrode pattern having a thickness of 8-12 μm on a side of the fourth dielectric green layer facing away from the third electrode pattern with silver paste, as shown in fig. 9, the fourth electrode pattern including a ground electrode G, a first transmission line S1, a second transmission line S2, a third transmission line S3 and a fourth transmission line S4, the first transmission line S1 being connected to the sixth surface electrode B3 through a seventeenth electrical connection hole pillar K17, the second transmission line S2 being connected to the seventh surface electrode B4 through an eighteenth electrical connection hole pillar K18, the third transmission line S3 being connected to the eighth surface electrode B5 through a nineteenth electrical connection hole pillar K19, the fourth transmission line S4 being connected to the ninth surface electrode B6 through a twentieth electrical connection hole pillar K20, the first transmission line S1 being connected to the seventh capacitor electrode C71 through an eleventh electrical connection hole pillar K11, the second transmission line S2 is connected to the seventh second capacitor electrode C72 through the fifteenth via post K15, the third transmission line S3 is connected to the eighth second capacitor electrode C82 through the sixteenth via post K16, and the fourth transmission line S4 is connected to the eighth first capacitor electrode C81 through the twelfth via post K12;
laminating a fifth dielectric blank layer on one surface of the fourth dielectric layer, forming a fourth electrode pattern, printing and filling electrical connection holes on the fifth dielectric blank layer with silver paste to form electrical connection hole pillars, printing and filling an end surface electrode pattern with the thickness of 8-12 μm on one surface of the fifth dielectric blank layer, which is far away from the fourth electrode pattern, with silver paste, as shown in fig. 10, wherein the end surface electrode pattern comprises an eleventh electrode P11, a twenty-first electrode P21, a thirty-first electrode P31, a forty-first electrode P41, a fifty-first electrode P51, a sixty-first electrode P61, a seventy-first electrode P71, an eighty-first electrode P81, a ninety-first electrode P91 and a hundred-zero-first electrode P101, the eleventh electrode P11 is connected to a ground electrode G through a fourteenth electrical connection hole pillar K24, the twenty-first electrode P21 is connected to the ground electrode G through a thirteenth electrical connection hole pillar K23, and the thirteenth electrode P31 is connected to a fourteenth electrical connection hole pillar 399634 and a fourteenth electrical connection pillar C3638 through a fourteenth electrical connection hole pillar 3, respectively And a second capacitor electrode C21, the forty-first electrode P41 is connected to the ground electrode G through a twenty-twelve electrical connection hole column K22, the fifty-first electrode P51 is connected to the ground electrode G through a twenty-first electrical connection hole column K21, the sixty-first electrode P61 is connected to the first transmission line S1 through a twenty-fifth electrical connection hole column K25, the seventy-first electrode P71 is connected to the second transmission line S2 through a twenty-sixth electrical connection hole column K26, the eighty-first electrode P81 is connected to the ground electrode G through a twenty-ninth electrical connection hole column K29, the ninety-first electrode P91 is connected to the third transmission line S3 through a twenty-seventh electrical connection hole column K27, and the one hundred-zero-first electrode P101 is connected to the fourth transmission line S4 through a twenty-eighteenth electrical connection hole column K28; obtaining a lamination structure block through printing and laminating;
pressure equalizing: maintaining the pressure of the laminated structure bar block at 70-80 ℃ and 25-32MPa for 8-10 minutes to obtain a laminated bar block;
cutting: cutting and dispersing the laminated bar blocks into single green bodies;
and (3) sintering: heating the green body to 400-450 ℃ at the heating rate of 0.3-0.5 ℃/min, preserving heat for 10-12 hours, removing the glue, heating to 600-650 ℃ at the heating rate of 0.8-1 ℃/min, heating to 880-900 ℃ at the heating rate of 3-4 ℃/min, preserving heat, sintering for 2-3 hours, and naturally cooling to room temperature to obtain the sintered ceramic body.
Wherein, preparing the forming auxiliary material layer and the ceramic substrate 100 material layer further comprises pulping and casting.
The pulping process comprises the following specific steps: the ceramic material is prepared from two dielectric materials, namely carbon powder and ceramic powder.
The carbon powder slurry comprises carbon powder (the particle size D50 is 1.5-2.5 μm), a solvent, a plasticizer, a binder and a dispersing agent. Wherein, the carbon powder slurry comprises, by mass, 45-55% of carbon powder, 40-50% of a solvent, 2-4.5% of a plasticizer, 2.5-6% of a binder and 0.2-1.5% of a dispersant. The solvent can be a mixture of isobutyl alcohol and propyl acetate in a mass ratio of 2:8, the plasticizer can be dioctyl phthalate, the binder can be polyvinyl butyral, and the dispersant can be castor oil.
The preparation process of the carbon powder slurry is as follows: mixing and ball-milling carbon powder, a solvent and a dispersing agent for 8-12 hours, then adding a binder, and continuing ball-milling for 16-24 hours at the ball-milling rotating speed of 40-60rpm to prepare carbon powder slurry.
Wherein, the ceramic slurry comprises ceramic powder (the grain diameter D50 is 1.0-2.0 μm, the medium constant is 7.6-8.2), solvent, plasticizer, binder and dispersant. Wherein, the ceramic slurry comprises, by mass, 42-56% of ceramic powder, 40-50% of solvent, 2-5% of plasticizer, 2.5-6% of binder and 0.2-1.5% of dispersant. The solvent can be a mixture of isobutyl alcohol and propyl acetate in a mass ratio of 2:8, the plasticizer can be dioctyl phthalate, the binder can be polyvinyl butyral, and the dispersant can be castor oil.
The preparation process of the ceramic slurry is as follows: mixing and ball-milling the ceramic powder, the solvent and the dispersant for 8-12 hours, then adding the binder, and continuing ball-milling for 16-24 hours at the ball-milling rotating speed of 40-60rpm to prepare the ceramic slurry.
Wherein, in the forming process, the viscosity of the silver paste used for printing the electrode pattern is 90000-110000 mPa.S (at 25 ℃ +/-1 ℃, the rotational speed of a DV-Pro II viscometer is 5rpm), and the viscosity of the silver paste used for filling the electric connection hole column is 240000-260000 mPa.S (at 25 ℃ +/-1 ℃, the rotational speed of a DV-Pro II viscometer is 14 rpm, 10 rpm). In the lamination process, the lamination temperature is 50-60 ℃, and the lamination pressure is 30-40 tons.
In a specific embodiment, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5 and the sixth inductor L6 are all planar spiral inductors, and the ground electrode G is a grid-type planar structure.
By adopting the material with low dielectric constant and matching with the design of the planar spiral inductor and the grounding electrode G with a gridding planar structure, the parasitic capacitance at high frequency can be reduced, so that the relative bandwidth is wider at high frequency.
In a more specific embodiment, forming the first isolation resistor R1, the second isolation resistor R2, and the third isolation resistor R3 includes: printing resistance paste with the thickness of 8-10 μm between the fourth surface electrode B1 and the fifth surface electrode B2 to form a first isolation resistance R1 connecting the fourth surface electrode B1, the first surface electrode A1 and the fifth surface electrode B2; printing resistance paste with the thickness of 8-10 μm between the sixth surface electrode B3 and the seventh surface electrode B4 to form a second isolation resistance R2 connecting the sixth surface electrode B3, the second surface electrode A2 and the seventh surface electrode B4; a resistance paste having a thickness of 8-10 μm was printed between the eighth surface electrode B5 and the ninth surface electrode B6 to form a third isolation resistance R3 connecting the eighth surface electrode B5, the third surface electrode A3 and the ninth surface electrode B6.
Resistance values of the designed isolation resistors are all 100 +/-0.5 omega, a calculation formula of the designed resistance values is that R is Rs L/W (Rs is a square resistor, L is an effective length of the resistor, and W is a resistor width), the square resistor Rs is 40-50 omega/□, and the effective length L of the resistor is determined by the distance between two ends of the resistor, so that the resistor width W can be determined; the resistance value of the thick film resistor is required to be smaller than the target resistor (100 +/-0.5 omega), so that the laser resistor trimming machine can accurately trim the resistance value to reach the target resistance value conveniently.
The resistance is manufactured by adopting a thick film process, the viscosity of the resistance paste is 100000-200000 mPa.S (under the condition of 25 +/-1 ℃, the rotational speed of a 14-rotor DV-Pro II viscometer is 10 rpm).
In a more specific embodiment, the laser trimming specifically includes: monitoring the resistance values of the two ends of the fifth surface electrode B2 and the first surface electrode A1, the two ends of the first surface electrode A1 and the fifth surface electrode B2, the two ends of the sixth surface electrode B3 and the second surface electrode A2, the two ends of the second surface electrode A2 and the seventh surface electrode B4, the two ends of the eighth surface electrode B5 and the third surface electrode A3, and the two ends of the surfaces of the third surface electrode A3 and the ninth surface electrode B6 in real time, and adjusting the resistance values corresponding to the resistance values to 50 +/-0.2 omega through a laser resistor adjuster, so that the resistance values of the first isolation resistor R1, the second isolation resistor R2 and the third isolation resistor R3 reach 100 +/-0.5 omega.
In some embodiments, the step of preparing the isolation resistor further comprises silver coating, and the step of preparing the isolation resistor further comprises electroplating.
The silver coating comprises the following specific steps: by adopting a method of printing silver coating, the viscosity of silver paste is 9000-110000 mPa.S (at 25 +/-1 ℃, the rotational speed of a No. 52 rotor of a DV-Pro II viscometer is 5rpm), two side ends of the ceramic body are respectively printed with 8-10 micron end side electrodes, as shown in figure 11, the end side electrodes comprise a twelfth electrode P12, a twenty-second electrode P22, a thirty-second electrode P32, a forty-second electrode P42, a fifty-second electrode P52, a sixty-second electrode P62, a seventy-second electrode P72, an eighty-second electrode P82, a ninety-second electrode P92 and a hundred-zero second electrode P102, the end side electrodes and the end surface electrodes are correspondingly connected one by one to form each end, and then the ceramic body which is printed with silver coating is heated in a chain furnace at 830-850 ℃ for 8-10 minutes.
Wherein, the electroplating is as follows: the bottom layer materials of the terminals (namely a first grounding terminal electrode P1, a second grounding terminal electrode P2, a signal input terminal electrode P3, a third grounding terminal electrode P4, a fourth grounding terminal electrode P5, a first signal output terminal electrode P6, a second signal output terminal electrode P7, a third signal output terminal electrode P9, a fourth signal output terminal electrode P10 and a fifth grounding terminal electrode P8) and the surface electrodes (namely a first surface electrode A1, a second surface electrode A2, a third surface electrode A3, a fourth surface electrode B1, a fifth surface electrode B2, a sixth surface electrode B3, a seventh surface electrode B4, an eighth surface electrode B5 and a ninth surface electrode B6) are all silver by adopting a rolling type electroplating method, and then a nickel layer and a tin layer are sequentially plated on the bottom layer materials, wherein the thickness is 3-5 mu m, and the thickness of the tin layer is 5-9 mu m. Wherein, the nickel layer is used for heat insulation and reducing welding thermal shock damage and the ceramic substrate 100; the tin-lead layer is easy to tin-weld, and the tin-lead can inhibit silver migration and improve the welding reliability.
By the preparation method, the low-temperature co-fired ceramic power divider with the volume of 7.6mm multiplied by 6.4mm multiplied by 1.3mm can be realized, the passband frequency is 1-2GHz, the bandwidth is 1GHz, and the relative bandwidth is up to 66%. And the preparation method has simple process, stable and reliable structure and easy industrial production.
In summary, the low-temperature co-fired ceramic power divider provided by the embodiment at least has the following beneficial technical effects:
according to the low-temperature co-fired ceramic power divider, the isolation resistor is printed on the ceramic substrate by adopting a thick film process, so that the product is small in size, high in integration level, light in weight, enhanced in environmental adaptability and high in reliability.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A low temperature co-fired ceramic power divider is characterized by comprising:
a ceramic substrate;
a signal input terminal electrode, a first signal output terminal electrode, a second signal output terminal electrode, a third signal output terminal electrode and a fourth signal output terminal electrode which are arranged on the surface of the ceramic substrate;
the power distribution circuit is embedded in the ceramic substrate and is used for distributing signal energy input by the signal input end electrode to the first signal output end electrode, the second signal output end electrode, the third signal output end electrode and the fourth signal output end electrode;
the first isolation resistor is connected between the second signal output end electrode and the third signal output end electrode;
the second isolation resistor is connected between the first signal output end electrode and the second signal output end electrode; and
the third isolation resistor is connected between the third signal output end electrode and the fourth signal output end electrode;
the first isolation resistor, the second isolation resistor and the third isolation resistor are printed on the surface of the ceramic substrate through a thick film process.
2. The low temperature co-fired ceramic power divider of claim 1, wherein the power distribution circuit comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, and a sixth inductor;
the input end of the first inductor and the input end of the second inductor are connected to the signal input end electrode, the input end of the third inductor and the input end of the fourth inductor are connected to the output end of the first inductor, the input end of the fifth inductor and the input end of the sixth inductor are connected to the output end of the second inductor, the output end of the third inductor is connected to the first signal output end electrode, the output end of the fourth inductor is connected to the second signal output end electrode, the output end of the fifth inductor is connected to the third signal output end electrode, and the output end of the sixth inductor is connected to the fourth signal output end electrode;
the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor and the sixth inductor are all planar spiral inductors, and the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor and the sixth inductor are arranged on the same plane.
3. The low temperature co-fired ceramic power divider of claim 2, wherein the first inductor and the second inductor are arranged in mirror symmetry, the third inductor and the fourth inductor are arranged in mirror symmetry, and the fifth inductor and the sixth inductor are arranged in mirror symmetry with the third inductor and the fourth inductor.
4. The low temperature co-fired ceramic power divider of claim 1, wherein the power distribution circuit further comprises a seventh capacitor and an eighth capacitor;
the seventh capacitor is connected between the first signal output end electrode and the second signal output end electrode, and the eighth capacitor is connected between the third signal output end electrode and the fourth signal output end electrode;
and the seventh capacitor and the eighth capacitor are both plate capacitors.
5. The low-temperature co-fired ceramic power divider of claim 2, further comprising a ground electrode, a first capacitive electrode and a second capacitive electrode, wherein the ground electrode is in a grid-like planar structure;
the first capacitor electrode is connected with the input end of the first inductor and forms a first capacitor with the grounding electrode at intervals, and the second capacitor electrode is connected with the input end of the second inductor and forms a second capacitor with the grounding electrode at intervals;
the third inductor, the fourth inductor, the fifth inductor and the sixth inductor respectively generate a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor with the grounding electrode at high frequency.
6. The low-temperature co-fired ceramic power divider of claim 5, further comprising a first ground end electrode, a second ground end electrode, a third ground end electrode, a fourth ground end electrode and a fifth ground end electrode, wherein the ground electrode is connected with the first ground end electrode, the second ground end electrode, the third ground end electrode, the fourth ground end electrode and the fifth ground end electrode in a one-to-one correspondence manner through a twenty-fourth electrical connection hole column, a twenty-third electrical connection hole column, a twenty-second electrical connection hole column, a twenty-first electrical connection hole column and a twenty-ninth electrical connection hole column.
7. The low-temperature co-fired ceramic power divider of claim 6, wherein the first ground terminal electrode, the second ground terminal electrode, the signal input terminal electrode, the third ground terminal electrode and the fourth ground terminal electrode are disposed on one side of the ceramic substrate and are sequentially disposed at equal intervals along a length direction of the ceramic substrate; the first signal output end electrode, the second signal output end electrode, the fifth grounding end electrode, the third signal output end electrode and the fourth signal output end electrode are sequentially arranged on the other side of the ceramic base at equal intervals.
8. The low-temperature co-fired ceramic power divider of claim 2, further comprising a first surface electrode, a second surface electrode, a third surface electrode, a fourth surface electrode, a fifth surface electrode, a sixth surface electrode, a seventh surface electrode, an eighth surface electrode and a ninth surface electrode disposed on a side of the ceramic substrate on which the isolation resistor is printed;
the fourth surface electrode, the first surface electrode and the fifth surface electrode are sequentially connected in series through the first isolation resistor, the first inductor is connected to the fourth surface electrode through a first electric connection hole column, the second inductor is connected to the fifth surface electrode through a fifth electric connection hole column, the fourth surface electrode is connected to the third inductor and the fourth inductor through a second electric connection hole column, and the fifth surface electrode is connected to a fifth inductor sixth inductor through a sixth electric connection hole column;
the sixth surface electrode, the second surface electrode and the seventh surface electrode are sequentially connected in series by the second isolation resistor, the third inductor is connected to the sixth surface electrode through a third electric connection hole column, and the fourth inductor is connected to the seventh surface electrode through a fourth electric connection hole column;
the eighth surface electrode, the third surface electrode and the ninth surface electrode are sequentially connected in series by the third isolation resistor, the fifth inductor is connected to the eighth surface electrode through a seventh electric connection hole pillar, and the sixth inductor is connected to the ninth surface electrode through an eighth electric connection hole pillar.
9. The low-temperature co-fired ceramic power divider of claim 8, wherein the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor and the sixth inductor are all planar spiral inductors, six planar spiral inductors are arranged on the same plane, the first inductor and the second inductor are arranged in mirror symmetry, the signal input terminal electrode is connected to the first inductor through a thirteenth electrical connection hole pillar and a ninth electrical connection hole pillar, and the signal input terminal electrode is electrically connected to the second inductor through a fourteenth electrical connection hole pillar and a tenth electrical connection hole pillar;
the third inductor and the fourth inductor are arranged in a mirror symmetry mode, the fifth inductor and the sixth inductor are arranged in a mirror symmetry mode with the third inductor and the fourth inductor, the sixth surface electrode is connected to the first transmission line through a seventeenth electric connection hole column, the other end of the first transmission line is connected to the first signal output end electrode through a twenty-fifth electric connection hole column, the seventh surface electrode is connected to the second transmission line through an eighteenth electric connection hole column, and the other end of the second transmission line is connected to the second signal output end electrode through a twenty-sixth electric connection hole column; the eighth surface electrode is connected to the third transmission line through a nineteenth electric connection hole column, the other end of the third transmission line is connected to the third signal output end electrode through a twenty-seventh electric connection hole column, the ninth surface electrode is connected to the fourth transmission line through a twentieth electric connection hole column, and the other end of the fourth transmission line is connected to the fourth signal output end electrode through a eighteenth electric connection hole column.
10. The low-temperature co-fired ceramic power divider of claim 1, wherein the ceramic matrix has a relative dielectric constant of 7.6-8.2 and a dielectric loss tan α of 0.001 or less.
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| CN113725580A (en) * | 2021-09-26 | 2021-11-30 | 深圳振华富电子有限公司 | Low-temperature co-fired ceramic power divider and preparation method thereof |
| CN116169451A (en) * | 2023-04-03 | 2023-05-26 | 石家庄烽瓷电子技术有限公司 | Three-dimensional packaged miniaturized power divider |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113725580A (en) * | 2021-09-26 | 2021-11-30 | 深圳振华富电子有限公司 | Low-temperature co-fired ceramic power divider and preparation method thereof |
| CN116169451A (en) * | 2023-04-03 | 2023-05-26 | 石家庄烽瓷电子技术有限公司 | Three-dimensional packaged miniaturized power divider |
| CN116169451B (en) * | 2023-04-03 | 2024-05-07 | 石家庄烽瓷电子技术有限公司 | Three-dimensional packaged miniaturized power divider |
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