CN215815845U - Multi-chip filter packaging structure based on barrier layer - Google Patents
Multi-chip filter packaging structure based on barrier layer Download PDFInfo
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- CN215815845U CN215815845U CN202123314330.2U CN202123314330U CN215815845U CN 215815845 U CN215815845 U CN 215815845U CN 202123314330 U CN202123314330 U CN 202123314330U CN 215815845 U CN215815845 U CN 215815845U
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- chip
- barrier layer
- filter
- filter chip
- substrate
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 title claims description 55
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000000903 blocking effect Effects 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 238000005253 cladding Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
The utility model provides a multi-chip filter packaging structure based on a blocking layer, which comprises a substrate, a filter chip, a non-filter chip, the blocking layer and a plastic package layer, wherein the filter chip and the non-filter chip are respectively fixed on the substrate, the blocking layer and the plastic package layer are sequentially covered on the filter chip, the non-filter chip and the substrate, a vacuum cavity is formed between the filter chip and the substrate under the surrounding of the blocking layer, and the plastic package layer on the side surface of the non-filter chip extends to the position between the bottom surface of the non-filter chip and the substrate. The utility model can solve the problem that the existing non-filter chip and the filter chip can not be packaged in one structure, relatively reduces the packaging area while integrating the two chips, integrally reduces the product size, promotes the functional integration of the filter product, reduces the production cost and improves the economic benefit.
Description
Technical Field
The utility model relates to a filter, in particular to a filter chip.
Background
With the continuous progress of semiconductor technology, filter products also meet the huge market demand and rapid development opportunities, and the product structure is designed towards higher integration level, smaller package size and more comprehensive performance. In order to meet the trend of development, the filter chips and the non-filter chips need to be highly integrated in a package structure with a limited area, so as to reduce the overall size of the product. On one hand, the chip can be isolated from the outside by packaging the chip, and the electric performance reduction caused by the corrosion of the chip circuit by impurities in the air is prevented; on the other hand, the packaged chip is more convenient to mount and transport.
In a filter product, a filter chip usually requires a cavity at the bottom of the filter chip, and the cavity can be equivalent to an inductor parallel capacitor, so that a resonant level is formed, and a microwave filtering function is realized. The bottom of the other functional chips must be effectively filled, otherwise reliability problems arise. The existing multi-chip filter packaging structure cannot meet the requirements of bottom filling of other functional chips and simultaneously needs to form a structure of a bottom cavity of the filter chip.
SUMMERY OF THE UTILITY MODEL
Utility model purpose: the utility model aims to provide a barrier layer-based multi-chip filter packaging structure which can integrate a filter chip and a non-filter chip simultaneously and has small packaging area aiming at the defects of the prior art.
The technical scheme is as follows: the utility model provides a multi-chip filter packaging structure based on a blocking layer, which comprises a substrate, a filter chip, a non-filter chip, the blocking layer and a plastic package layer, wherein the filter chip and the non-filter chip are respectively fixed on the substrate, the blocking layer and the plastic package layer are sequentially covered on the filter chip, the non-filter chip and the substrate, a vacuum cavity is formed between the filter chip and the substrate under the surrounding of the blocking layer, and the plastic package layer on the side surface of the non-filter chip extends to the position between the bottom surface of the non-filter chip and the substrate.
Further, the barrier layer includes the first barrier layer of cladding filter chip and the second barrier layer of cladding non-filter chip, and the disconnection setting between first barrier layer and the second barrier layer.
Furthermore, the first blocking layer is attached to the top surface and the side surface of the filter chip, and the blocking layer on the side surface extends downwards to the surface of the substrate.
Further, the second barrier layer is only attached to the top surface and the side surface of the non-filter chip.
Further, the filter chip and the non-filter chip are flip-chip mounted on the substrate.
Further, the filter chip and the non-filter chip are fixed on the bonding pad of the substrate through a metal bump.
Furthermore, the metal bump is a solder paste, a solder ball or a copper column.
Further, the barrier layer is a PET white film.
Has the advantages that: according to the utility model, the barrier layer is arranged between the chip and the plastic package layer, the vacuum cavity is formed by surrounding the barrier layer aiming at the bottom of the filter chip, the barrier layer is not arranged at the bottom of the non-filter chip, and the plastic package layer is directly filled, so that the two chips can be simultaneously integrated on one substrate, the problem that the conventional non-filter chip and the filter chip cannot be packaged in one structure is solved, the packaging area is relatively reduced while the two chips are integrated, the product size is integrally reduced, the functional integration of the filter product is promoted, the production cost is reduced, and the economic benefit is improved.
Drawings
FIG. 1 is a schematic structural diagram of a package structure according to the present invention;
fig. 2 is a schematic diagram of a packaging process of the packaging structure of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention. While the utility model is illustrated and described in connection with these embodiments, it should be understood that the utility model is not limited to these embodiments. On the contrary, the utility model is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the utility model as defined by the appended claims.
A multi-chip filter packaging structure based on a barrier layer is shown in figure 1 and comprises a substrate 5, a filter chip 4, a non-filter chip 8, a barrier layer 2 and a plastic package layer 1. The filter chip 4 and the non-filter chip 8 are fixed on the substrate 5, and both the filter chip 4 and the non-filter chip 8 are flip-chip mounted on the substrate 5 and are welded on the bonding pads 7 of the substrate 5 through the metal bumps 6. The surface of the filter chip 4, the surface of the non-filter chip 8 and the surface of the substrate 5 are sequentially covered with a barrier layer 2 and a plastic package layer 1, wherein the barrier layer 2 is a PET white film, and the plastic package layer 1 is formed by injection molding of a plastic package material.
In particular, the barrier layer 2 comprises a first barrier layer covering the filter chip 4 and a second barrier layer covering the other functional chip 8, the discontinuity being broken between the first barrier layer and the second barrier layer.
The first barrier layer is attached to the top surface and the side surface of the filter chip 4, and the barrier layer 2 on the side surface extends downward to the surface of the substrate 5, so that the barrier layer 2 on the side surface is connected with the barrier layer 2 on the surface of the substrate 5 into a whole, a cavity 3 is formed below the bottom surface of the filter chip 4, above the surface of the substrate 5 and between the connected barrier layers 2, and the cavity 3 is a vacuum cavity 3.
The second barrier layer is only attached to the top surface and the side surface of the non-filter chip 8, the bottom end of the barrier layer 2 on the side surface is cut off and is flush with the bottom surface of the functional chip 8, and the barrier layer 2 on the surface of the substrate 5 is not connected with the second barrier layer, so that the plastic package material can flow to the bottoms of other functional chips 8 when being filled, and the plastic package layer 1 is directly filled between the bottom surface of the non-filter chip 8 and the surface of the substrate 5.
The packaging process for forming the above-mentioned package structure is as follows, as shown in fig. 2:
s1, preparing a substrate.
S2, chip mounting: the filter chip 4 is inversely arranged on the substrate 5 and is welded on a bonding pad 7 of the substrate 5 through a metal bump 6; similarly, the non-filter chip 8 is flip-chip mounted on the substrate 5 and is soldered to the pad 7 of the substrate 5 via the metal bump 6.
S3, barrier layer coating film: placing a substrate 5 on a film pasting platform, pasting a barrier layer 2 corresponding to the whole size of the substrate 5 on the front surface of the substrate 5, placing the film-covered substrate 5 into a vacuum cavity of a film laminator, and heating and vacuumizing the film-covered substrate 5 through the vacuum cavity of the film laminator; furthermore, barrier layer 2 closely laminates around base plate 5 upper surface, chip upper surface and chip, and filter chip 4 bottom and functional silicon chip bottom all form a cavity 3 through the encirclement of barrier layer 2 and between the base plate 5, then, through the cutting board with 8 barrier layer 2 of base plate 5 are connected to non-filter chip bottom all around, release inside vacuum.
S4, integral plastic package: completing product plastic package under a small film-combining pressure through a Compression Molding injection Molding machine, enabling the plastic package layer 1 to cover the barrier layer 2 and simultaneously flow below the non-filter chip 8 to complete bottom filling, and reserving the vacuum cavity 3 at the bottom of the filter chip 4; and cutting the whole plastic-encapsulated product into single pieces to finish the product encapsulation process.
As above, while the utility model has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.
Claims (8)
1. The utility model provides a multi-chip filter packaging structure based on barrier layer which characterized in that: including base plate, wave filter chip, non-wave filter chip, barrier layer and plastic envelope layer, wave filter chip and non-wave filter chip fix respectively on the base plate, cover barrier layer and plastic envelope layer on wave filter chip, non-wave filter chip and base plate in order, there is vacuum cavity between wave filter chip and the base plate under the surrounding of barrier layer, the plastic envelope layer of non-wave filter chip side extends to between the bottom surface and the base plate of non-wave filter chip.
2. The barrier layer-based multi-chip filter package structure of claim 1, wherein: the barrier layer includes the first barrier layer of cladding filter chip and the second barrier layer of cladding non-filter chip, and the disconnection setting between first barrier layer and the second barrier layer.
3. The barrier layer-based multi-chip filter package structure of claim 2, wherein: the first blocking layer is attached to the top surface and the side surface of the filter chip, and the blocking layer on the side surface extends downwards to the surface of the substrate.
4. The barrier layer-based multi-chip filter package structure of claim 2, wherein: the second barrier layer is only attached to the top surface and the side surface of the non-filter chip.
5. The barrier layer-based multi-chip filter package structure of claim 1, wherein: the filter chip and the non-filter chip are flip-chip mounted on the substrate.
6. The barrier layer-based multi-chip filter package structure of claim 1, wherein: the filter chip and the non-filter chip are fixed on the bonding pad of the substrate through the metal bump.
7. The barrier layer-based multi-chip filter package structure of claim 6, wherein: the metal bump is a solder paste, a solder ball or a copper column.
8. The barrier layer-based multi-chip filter package structure of claim 1, wherein: the barrier layer is a PET white film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123314330.2U CN215815845U (en) | 2021-12-27 | 2021-12-27 | Multi-chip filter packaging structure based on barrier layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123314330.2U CN215815845U (en) | 2021-12-27 | 2021-12-27 | Multi-chip filter packaging structure based on barrier layer |
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| Publication Number | Publication Date |
|---|---|
| CN215815845U true CN215815845U (en) | 2022-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123314330.2U Active CN215815845U (en) | 2021-12-27 | 2021-12-27 | Multi-chip filter packaging structure based on barrier layer |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114784179A (en) * | 2022-03-11 | 2022-07-22 | 江苏卓胜微电子股份有限公司 | Chip module packaging method and chip module |
| CN115642095A (en) * | 2022-09-08 | 2023-01-24 | 武汉敏声新技术有限公司 | Radio frequency module packaging structure and method |
-
2021
- 2021-12-27 CN CN202123314330.2U patent/CN215815845U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114784179A (en) * | 2022-03-11 | 2022-07-22 | 江苏卓胜微电子股份有限公司 | Chip module packaging method and chip module |
| CN114784179B (en) * | 2022-03-11 | 2023-09-15 | 江苏卓胜微电子股份有限公司 | Chip module packaging method and chip module |
| CN115642095A (en) * | 2022-09-08 | 2023-01-24 | 武汉敏声新技术有限公司 | Radio frequency module packaging structure and method |
| CN115642095B (en) * | 2022-09-08 | 2024-03-29 | 武汉敏声新技术有限公司 | Radio frequency module packaging structure and method |
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| GR01 | Patent grant | ||
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| CP03 | Change of name, title or address |
Address after: 210000 No. 8, Linchun Road, Pukou Economic Development Zone, Pukou District, Nanjing, Jiangsu Province Patentee after: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Country or region after: China Address before: 210000 a-11, No. 69, Shuangfeng Road, Pukou Economic Development Zone, Pukou District, Nanjing, Jiangsu Province Patentee before: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Country or region before: China |