CN215813807U - Autonomous controllable navigation control module - Google Patents

Abstract

The utility model relates to an autonomous controllable navigation control module which comprises an FPGA chip, a VPX connector, a nonvolatile memory and onboard memory particles, wherein the nonvolatile memory and the onboard memory particles are connected with the FPGA chip, an output port of a navigation management board of the VPX connector is connected with a first differential line driver, the first differential line driver is connected with a fourth signal isolator level conversion module, the fourth signal isolator level conversion module is connected with an RXD port of the FPGA chip, an input port of the navigation management board of the VPX connector is connected with a second differential line driver, the second differential line driver is connected with a fifth signal isolator level conversion module, and an analog quantity acquisition board of the VPX connector is connected with a sixth signal isolator level conversion module. The utility model has the characteristics of high system integration level, flexible interface expansion, simple hardware frame, high system stability, low cost and full-automatic controllability.

Description

Autonomous controllable navigation control module

Technical Field

The utility model relates to the technical field of navigation control, in particular to an autonomous controllable navigation control module.

Background

The navigation control module is a navigation control device integrating the acquisition, processing, distribution and control management of navigation data. The existing navigation control equipment needs a Central Processing Unit (CPU), a bus interface driver and an interface expander to complete a large amount of interface expansion and communication services due to complex data processing services and large workload. The complicated service system causes the hardware system design of the navigation control module to be too complex, the number of link nodes is large, the cost is high, the types and the number of supported interfaces are limited by CPU interface resources and bridge chip scheme resources, the expandability is poor, and the navigation control module is not suitable for being used in the scene of specific application requirements.

Disclosure of Invention

The utility model aims to solve the defects of the prior art and provides an autonomous controllable navigation control module.

In order to achieve the purpose, the utility model adopts the following technical scheme: an autonomous controllable navigation control module comprises an FPGA chip, a VPX connector, a nonvolatile memory and onboard memory particles, wherein the nonvolatile memory and the onboard memory particles are connected with the FPGA chip, the FPGA chip is provided with a JTAG debugging port, a UART debugging port, a power supply port and a fan state detection and control port, a CAN communication port of an interface board I of the VPX connector is connected with a signal isolator level conversion module I, a CAN communication port of an interface board II of the VPX connector is connected with a signal isolator level conversion module II, the signal isolator level conversion module I and the signal isolator level conversion module II are both connected with the FPGA chip, a signal port of the interface board I of the VPX connector is connected with a signal isolator level conversion module III, a signal port of the interface board II of the VPX connector is also connected with the signal isolator level conversion module III, and the signal isolator level conversion module III is connected with a GPI0 port of the FPGA chip, an output port of a navigation management board of the VPX connector is connected with a first differential line driver, the first differential line driver is connected with a fourth signal isolator level conversion module, the fourth signal isolator level conversion module is connected with an RXD port of the FPGA chip, an input port of the navigation management board of the VPX connector is connected with a second differential line driver, the second differential line driver is connected with a fifth signal isolator level conversion module, the fifth signal isolator level conversion module is connected with a TXD port of the FPGA chip, an analog quantity acquisition board of the VPX connector is connected with a sixth signal isolator level conversion module, and the sixth signal isolator level conversion module is connected with a GPI0 port of the FPGA chip.

And the optical fiber interface and the optical network interface of the interface board I of the VPX connector are both connected with the FPGA chip.

And the optical fiber interface and the optical network interface of the interface board II of the VPX connector are both connected with the FPGA chip.

The utility model has the beneficial effects that: the utility model has the characteristics of high system integration level, flexible interface expansion, simple hardware frame, high system stability, low cost and full-automatic controllability.

Drawings

FIG. 1 is a functional block diagram of the present invention;

FIG. 2 is a schematic diagram of the integrated structure of the present invention;

in the figure: 1-a cold plate; 2-a fin;

the following detailed description will be made in conjunction with embodiments of the present invention with reference to the accompanying drawings.

Detailed Description

The utility model is further illustrated by the following examples in conjunction with the accompanying drawings:

as shown in fig. 1 to fig. 2, an autonomous controllable navigation control module comprises an FPGA chip, a VPX connector, a nonvolatile memory and onboard memory particles, wherein the nonvolatile memory and the onboard memory particles are connected with the FPGA chip, the FPGA chip is provided with a JTAG debug port, a UART debug port, a power supply port and a fan status detection and control port, a first signal isolator level conversion module is connected to a CAN communication port of an interface board i of the VPX connector, a second signal isolator level conversion module is connected to a CAN communication port of an interface board ii of the VPX connector, the first signal isolator level conversion module and the second signal isolator level conversion module are connected with the FPGA chip, a third signal isolator level conversion module is connected to a signal port of the interface board i of the VPX connector, a third signal port of the interface board ii of the VPX connector is also connected with the third signal isolator level conversion module, and the third signal isolator level conversion module is connected with a GPI0 port of the FPGA chip, an output port of a navigation management board of the VPX connector is connected with a first differential line driver, the first differential line driver is connected with a fourth signal isolator level conversion module, the fourth signal isolator level conversion module is connected with an RXD port of the FPGA chip, an input port of the navigation management board of the VPX connector is connected with a second differential line driver, the second differential line driver is connected with a fifth signal isolator level conversion module, the fifth signal isolator level conversion module is connected with a TXD port of the FPGA chip, an analog quantity acquisition board of the VPX connector is connected with a sixth signal isolator level conversion module, and the sixth signal isolator level conversion module is connected with a GPI0 port of the FPGA chip.

And the optical fiber interface and the optical network interface of the interface board I of the VPX connector are both connected with the FPGA chip.

And the optical fiber interface and the optical network interface of the interface board II of the VPX connector are both connected with the FPGA chip.

The FPGA chip uses a Shanghai double-denier microelectronic high-performance field programmable gate array JFM7 series FPGA as a main control chip, the model of the FPGA chip is JFM7K325T, and the FPGA chip is compatible with K7 series products of Xilinx manufacturers. The FPGA chip realizes analog signal acquisition, differential signal acquisition, CAN interface communication, high-speed signal communication and optical network communication functions through logic.

The utility model is designed according to the standard 6U specification, and adopts the high-reliability blade type VPX connector, thereby ensuring the reliability of connection. The operating system is deployed on the soft core of the FPGA chip, so that the integration level and the interface flexibility of the system are greatly improved, and the complexity and the cost of a system hardware frame are reduced to a certain extent. The interface board I, the interface board II, the navigation management module and the analog quantity acquisition module of the navigation control system are interconnected through a high-speed backboard VPX connector to carry out system-level interface interconnection, and the whole service of the navigation control system is completed. Specifically, the CAN communication data of the interface board I and the interface board II firstly enter a signal isolator (namely a signal isolator level conversion module I and a signal isolator level conversion module II) with a level conversion function through a VPX connector, so that the signal level of 5V TTL is converted into the level of 3.3V TTL while the signal is electrically isolated, and the requirement of an FPGA chip with the model number of JFM7K325T on signal level matching is met. And the data of the CAN protocol enters the FPGA chip and then is processed by a corresponding service layer. The signal port of the interface board I, the signal port of the interface board II and the single-end signal of the analog quantity acquisition template are subjected to electrical isolation and level conversion chips with the same scheme, the signal level is converted into a level matched with a hardware interface of the FPGA chip, then the service data is subjected to corresponding service processing in the FPGA chip, and the system-level management and scheduling functions are realized through a soft core in the FPGA chip. Before entering the present invention, the data is IN the data format of RS422 standard, and is divided into a transmission signal RS422_ OUT _ P/N and a reception signal RS422_ IN _ P/N. The standard RS422 signal converts the standard RS422 differential data into a single-ended signal of TTL level through the RS422 differential line driver (namely, the differential line driver I and the differential line driver II), and then the signal is converted into a level matched with the FPGA chip hardware interface through the electrical isolation and level conversion chip with the same scheme, and then the service data is processed in the FPGA chip correspondingly. The optical fiber interface and the optical network interface of the navigation control module are used for transmitting services with high real-time requirements and huge data volume, such as a navigation radar and the like. The two interfaces are arranged on an FPGA chip, high-speed IO resources on the FPGA chip are applied, and the transmission of optical fiber and optical network services is realized by combining IP cores with corresponding functions.

In addition, the utility model integrates a large-capacity nonvolatile memory for storing and loading a starting program and an application program of the system; an onboard memory grain DDR3 is integrated and used for caching during system operation and large data transmission. The utility model reserves JTAG debugging port and UART debugging port for debugging and simulating FPGA chip. Meanwhile, the FPGA chip also monitors the transmitted fan state signal in real time and monitors the running state of the fan in the navigation control system. And the rotating speed of the fan is fed back and adjusted in real time by combining the chip junction temperature condition solved in the FPGA chip to increase the heat dissipation capacity and realize full closed-loop control of temperature control heat dissipation.

The VPX connector uses a medium-navigation photoelectric RT2 series connector, has the signal transmission rate as high as 6.25Gbps, and is suitable for signal transmission of the utility model. The devices of the utility model all adopt a localization scheme, and the autonomous controllability of the product in the key technology aspect of the chip is ensured.

The utility model simplifies the complexity of a hardware system, reduces communication transmission nodes, increases the flexibility of interface expansion, greatly reduces the hardware cost and improves the stability and reliability of the system.

As shown in fig. 2, the cold plate 1 is installed after integration, the surface of the cold plate 1 is oxidized to black by using an aluminum alloy plate 5a05 material, a heat dissipation device is arranged on the cold plate 1, a heat conduction pad is added between the cold plate 1 and the heat dissipation device to ensure that the cold plate 1 and the heat conduction pad can be in close contact, and the fins 2 are processed on the other surface of the cold plate 1 to increase the heat dissipation area and better release heat;

the utility model has been described in connection with the accompanying drawings, it is to be understood that the utility model is not limited to the specific embodiments disclosed, but is intended to cover various modifications, adaptations or uses of the utility model, and all such modifications and variations are within the scope of the utility model.

Claims (3)

1. An autonomous controllable navigation control module is characterized by comprising an FPGA chip, a VPX connector, a nonvolatile memory and onboard memory particles, wherein the nonvolatile memory and the onboard memory particles are connected with the FPGA chip, the FPGA chip is provided with a JTAG debugging port, a UART debugging port, a power supply port and a fan state detection and control port, a CAN communication port of an interface board I of the VPX connector is connected with a signal isolator level conversion module I, a CAN communication port of an interface board II of the VPX connector is connected with a signal isolator level conversion module II, the signal isolator level conversion module I and the signal isolator level conversion module II are connected with the FPGA chip, a signal port of the interface board I of the VPX connector is connected with a signal isolator level conversion module III, a signal port of the interface board II of the VPX connector is also connected with the signal isolator level conversion module III, and the signal isolator level conversion module III is connected with a GPI0 port of the FPGA chip, an output port of a navigation management board of the VPX connector is connected with a first differential line driver, the first differential line driver is connected with a fourth signal isolator level conversion module, the fourth signal isolator level conversion module is connected with an RXD port of the FPGA chip, an input port of the navigation management board of the VPX connector is connected with a second differential line driver, the second differential line driver is connected with a fifth signal isolator level conversion module, the fifth signal isolator level conversion module is connected with a TXD port of the FPGA chip, an analog quantity acquisition board of the VPX connector is connected with a sixth signal isolator level conversion module, and the sixth signal isolator level conversion module is connected with a GPI0 port of the FPGA chip.

2. The autonomous controllable navigation control module of claim 1, wherein the optical fiber interface and the optical network interface of the interface board i of the VPX connector are connected to the FPGA chip.

3. The autonomous controllable navigation control module according to claim 2, characterized in that the optical fiber interface and the optical network interface of the interface board ii of the VPX connector are both connected to the FPGA chip.

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