CN215731659U - Packaging structure of chip - Google Patents

Abstract

The utility model provides a packaging structure of a plurality of chips, which comprises: the chip carrying platform is used for supporting a plurality of chips; the waterproof groove is arranged on the periphery of the slide holder; the anti-overflow groove is arranged between two adjacent chips, the length of the anti-overflow groove is greater than the length of the shortest side of the chip in the direction of the anti-overflow groove, the width of the anti-overflow groove is between 0.05 and 0.1mm, and the depth of the anti-overflow groove is 1/10 to 1/5 of the thickness of the slide holder. According to the structure, the anti-overflow groove is formed between the chips of the chip carrying table, the overflow solder can enter the anti-overflow groove during chip welding, the influence on adjacent chips is avoided, the size of each chip can be increased by 0.35-0.55mm on one side, and therefore the integration of chip packaging can be improved.

Description

Packaging structure of chip

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a chip packaging structure.

Background

With the development of science and technology, semiconductor applications require semiconductor products with higher and higher integration level, higher and higher power density and higher reliability, so that not only the power density of the chip is continuously improved in the aspect of chip design, but also multi-device integration is continuously performed in the aspect of packaging, so as to improve the device integration level, increase the power density and improve the reliability. In the packaging of discrete devices, dual-chip or multi-chip integrated packaging is usually adopted, but because the size of the carrier area is limited, and a certain distance (usually, the distance between two chips is required to be 0.4-0.6mm) is also required to be arranged between the chips to ensure the reliability of the device, so that the phenomenon that in the process of welding the chips, solder overflows to cause the edge solder of the adjacent chip to be thickened and extend to the front side of the chip, or the cavity on the back side of the chip exceeds the standard, and the device is failed is prevented.

However, 0.4-0.6mm of space limits the number of multiple chip integrations and the chip size of the required package, and especially when multiple small chips are integrated into the package, the waste of space is more severe.

SUMMERY OF THE UTILITY MODEL

The utility model provides a chip packaging structure for solving the technical problems, and the structure is characterized in that an anti-overflow groove is arranged between chips of a chip carrying table, overflow solder can enter the anti-overflow groove during chip welding, so that adjacent chips are prevented from being influenced, the size of each chip can be increased by 0.35-0.55mm at one side, and the chip packaging integration can be improved.

The technical scheme adopted by the utility model is as follows:

the utility model provides a chip packaging structure, which comprises: the chip carrying table is used for supporting the plurality of chips; the waterproof groove is arranged on the periphery of the slide holder; the anti-overflow groove is arranged between two adjacent chips, the length of the anti-overflow groove is greater than that of the shortest edge of the chip in the direction of the anti-overflow groove, the width of the anti-overflow groove is 0.05-0.1mm, and the depth of the anti-overflow groove is 1/10-1/5 of the thickness of the slide holder.

The above proposed chip package structure of the present invention also has the following additional technical features:

specifically, the chip comprises two chips, the anti-overflow groove is arranged between the two chips, or the anti-overflow groove is arranged between the two chips, and the distance between the anti-overflow groove and one of the chips is larger than that between the anti-overflow groove and the other chip.

Specifically, the length of the overflow preventing groove is less than or equal to the length of the longest side of two adjacent chips, and is greater than or equal to the length of the shortest side of two adjacent chips.

Specifically, the overflow preventing groove is designed in a straight line or a curve.

Specifically, the waterproof groove and the anti-overflow groove are formed by adopting a mechanical stamping mode, a machine milling mode or a laser engraving mode or any mode capable of forming groove engraving.

The utility model has the beneficial effects that:

according to the utility model, the anti-overflow grooves are arranged between the chips of the chip carrier, overflow solder can enter the anti-overflow grooves during chip welding, so that adjacent chips are prevented from being influenced, and the size of each chip can be increased by 0.35-0.55mm on one side, thereby improving the integration of chip packaging.

Drawings

Fig. 1 is a schematic diagram of a package structure of a chip according to a first embodiment of the present invention;

fig. 2 is a schematic diagram of a package structure of a chip according to a second embodiment of the utility model;

fig. 3 is a schematic diagram of a package structure of a chip according to a third embodiment of the present invention;

fig. 4 is a schematic view showing the shape of an overflow preventing groove of a chip according to a first embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1 to 3, the number of the chips 4 is plural, and the package structure of the chip includes: the chip carrier comprises a chip carrier 1, a waterproof groove 2 and an anti-overflow groove 3, wherein the chip carrier 1 is used for supporting a plurality of chips 4; the waterproof groove 2 is arranged on the periphery of the slide holder 1; the anti-overflow grooves 3 are arranged between two adjacent chips 4, the length of each anti-overflow groove 3 is greater than the length of the shortest side of each chip in the anti-overflow groove direction, the width of each anti-overflow groove 3 is 0.05-0.1mm, and the depth of each anti-overflow groove 3 is 1/10-1/5 of the thickness of the slide holder 1.

Further, according to an embodiment of the present invention, the chips 4 may include two, and the overflow preventing groove 3 may be disposed in the middle of the two chips (as shown in fig. 1), or the overflow preventing groove 3 may be disposed between the two chips at a distance from one of the chips 4 greater than the other chip 4. The length of the overflow preventing groove 3 is less than or equal to the length of the longest side of two adjacent chips and is greater than or equal to the length of the shortest side of two adjacent chips. Specifically, the utility model mainly aims at packaging 2 chips and more than 2 chips, and the anti-overflow grooves are added between the adjacent chips 4 as shown in figures 1-3, so that the distance between the adjacent chips is reduced, the anti-overflow grooves are only required to be separated by one anti-overflow groove width (0.05-0.1mm), compared with the original design which requires the distance of 0.4-0.6mm, the distance between the chips is greatly reduced, the space is saved, the chips with larger size/more quantity can be packaged, and the anti-overflow grooves can be designed according to the size and the placement position of the packaged chips, and the design freedom degree is high.

In addition, the anti-overflow slot design can be divided into a general type and a special type. For general type design, because TO discrete device, for example in the TO encapsulation series, fixed a certain model is as TO-247 encapsulation, its frame has been fixed, and mostly 2 chip package, and slide holder 1 size has also been fixed, can be through the position with anti-overflow groove 3 fixed, for two chip package, anti-overflow groove 3 is fixed in the middle of the chip (as shown in fig. 1), or be partial TO a certain side edge fixed position, can be TO the same frame of multiple double-chip encapsulation sharing like this, avoid the volume production in-process frequently TO switch over the frame, cause man-hour extravagant. For the special design, because the chip position is placed specially, a large number of packaged chips on the market, including the size and the shape, can be designed according to the position of the anti-overflow groove 3.

The width, depth and length dimensions of the overflow preventing groove 3 are designed according to the principle that: the width is designed to be 0.05-0.1mm, the narrow process requirement is high, and the wide process loses the effect of saving the effective slide area of the bottom plate; the length design is at least the same as the shortest side length of the chips at two sides, and the safety design is preferably the same as the longest side length, so that the solder of the chip at the longest side length can overflow into the anti-overflow groove instead of the chip to be detected; the depth design is usually 1/10-1/5 of the thickness of the metal base plate (the wafer stage 1), the specific thickness should consider the solder overflow amount in each package, and on the premise of ensuring the solder overflow amount, the shallower the better, the deeper the depth will affect the whole metal base plate structure.

In an embodiment of the present invention, the stage 1 may be a copper plate.

In the embodiment of the present invention, the design of the anti-overflow groove 3 is not limited to the linear design, and other curved shapes including but not limited to the one shown in fig. 4 can also achieve the object of the present invention, and the curved shape can increase the anti-overflow groove path length and increase the solder overflow capacity compared with the linear design, thereby reducing the depth or width of the anti-overflow groove.

In the embodiment of the present invention, the water-proof groove 2 and the anti-overflow groove 3 may be formed by any method capable of forming groove marks, such as mechanical punching, milling by a machine tool, or laser engraving.

In particular, the anti-overflow groove 3 may be formed simultaneously with the waterproof groove 2, which has advantages of no additional process and convenient fabrication. The overflow prevention groove 3 can also be formed before or after the waterproof groove 2 is manufactured, which has the advantage that the depth of the overflow prevention groove can be controlled by adjusting the stamping parameters.

In summary, according to the chip packaging structure of the embodiment of the utility model, the water-proof groove is arranged at the periphery of the chip carrier, the anti-overflow groove is arranged between two adjacent chips, the length of the anti-overflow groove is greater than the length of the shortest side of the chip in the anti-overflow groove direction, the width of the anti-overflow groove is between 0.05 and 0.1mm, and the depth of the anti-overflow groove is between 1/10 and 1/5 of the thickness of the chip carrier. According to the structure, the anti-overflow groove is formed between the chips of the chip carrying table, the overflow solder can enter the anti-overflow groove during chip welding, the influence on adjacent chips is avoided, the size of each chip can be increased by 0.35-0.55mm on one side, and therefore the integration of chip packaging can be improved.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The meaning of "plurality" is two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims (6)

1. A chip packaging structure, wherein the chip is a plurality of chips, the chip packaging structure comprises:

the chip carrying table is used for supporting the plurality of chips;

the waterproof groove is arranged on the periphery of the slide holder;

the anti-overflow groove is arranged between two adjacent chips, the length of the anti-overflow groove is greater than that of the shortest edge of the chip in the direction of the anti-overflow groove, the width of the anti-overflow groove is 0.05-0.1mm, and the depth of the anti-overflow groove is 1/10-1/5 of the thickness of the slide holder.

2. The chip package structure according to claim 1, wherein the chips include two chips, the anti-overflow groove is disposed in the middle of the two chips, or the anti-overflow groove is disposed between the two chips and is spaced from one of the chips by a distance greater than that of the other chip.

3. The chip packaging structure according to claim 1, wherein the length of the overflow preventing groove is less than or equal to the length of the longest side of two adjacent chips and is greater than or equal to the length of the shortest side of two adjacent chips.

4. The chip package structure of claim 1, wherein the stage is a copper plate.

5. The chip package according to claim 1, wherein the anti-overflow groove is of a straight design or a curved design.

6. The chip packaging structure according to any one of claims 1 to 5, wherein the waterproof groove and the overflow-preventing groove are formed by mechanical punching, milling by a machine tool, or laser engraving.

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