CN215729733U - Input/output control circuit of mainboard - Google Patents
Input/output control circuit of mainboard Download PDFInfo
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- CN215729733U CN215729733U CN202121341530.4U CN202121341530U CN215729733U CN 215729733 U CN215729733 U CN 215729733U CN 202121341530 U CN202121341530 U CN 202121341530U CN 215729733 U CN215729733 U CN 215729733U
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Abstract
The utility model discloses a mainboard input/output control circuit, which can reduce the cost and comprises: the input and output control circuit of the mainboard is realized by adopting a complex programmable logic device CPLD chip, and the CPLD chip comprises: temperature sensor inquiry control module and fan speed control module, wherein: the temperature sensor query control module is connected with a CPU temperature sensor outside the CPLD chip through a temperature sensor interface to acquire a temperature value of the CPU temperature sensor; the temperature sensor query control module is also connected with the fan speed control module and sends a control instruction to the fan speed control module; and the output interface of the fan speed control module is connected with the CPU fan control interface outside the CPLD chip, and the fan speed control module sends a signal for controlling the fan speed to the CPU fan control interface.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to an input and output control circuit of a mainboard.
Background
The PC board, also called main board (main board) or system board (system board), is installed in the chassis, and is one of the most basic and important components of the microcomputer. PC boards are typically rectangular circuit boards. The PC motherboard has mounted thereon main circuits constituting a computer, including a Central Processing Unit (CPU), a memory, a Basic Input Output System (BIOS) chip, an Input/Output (I/O) control chip, a hard disk interface, a keyboard interface, a network interface, an expansion slot, and a dc power supply connector.
Currently, the functional circuit for implementing I/O control is mainly based on ASIC chips, for example: winbond's W83627 products, ITE's IT8786 products, SMSC's LPC47 series products. However, the ASIC chip is mainly used for fixed functions and controls, and when the functions of the product are upgraded and expanded, the corresponding chip must be newly selected and developed, thereby increasing maintenance costs and development time.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a mainboard input and output control circuit which is low in design and maintenance cost.
The embodiment of the utility model provides a mainboard input and output control circuit, which comprises: the input and output control circuit of the mainboard is realized by adopting a complex programmable logic device CPLD chip, and the CPLD chip comprises: temperature sensor inquiry control module and fan speed control module, wherein:
the temperature sensor query control module is connected with a CPU temperature sensor outside the CPLD chip through a temperature sensor interface to acquire a temperature value of the CPU temperature sensor; the temperature sensor query control module is also connected with the fan speed control module and sends a control instruction to the fan speed control module;
and the output interface of the fan speed control module is connected with the CPU fan control interface outside the CPLD chip, and the fan speed control module sends a signal for controlling the fan speed to the CPU fan control interface.
Optionally, the output interface of the fan speed control module is an interface that transmits a Pulse Width Modulation (PWM) signal, and a duty ratio of the PWM signal is positively correlated with a fan speed.
Optionally, the temperature sensor interface is an I2C interface.
Optionally, the CPLD chip further includes: and the CPU interface processing module is connected with a CPU management interface outside the CPLD chip and used for receiving an instruction sent by the CPU management interface, and the CPU interface processing module is connected with an indicator lamp outside the CPLD chip and used for sending a signal of turning on or turning off the indicator lamp.
Optionally, the CPU interface processing module is connected to the temperature sensor query control module, and the CPU interface processing module sends a control instruction for acquiring a temperature value to the temperature sensor query control module.
Optionally, the CPLD chip further includes: and the buzzer control module is connected with the CPU interface processing module and used for receiving a buzzer alarm control instruction sent by the CPU interface processing module, and the buzzer control module is also connected with a buzzer interface outside the CPLD chip and used for sending an alarm sound signal to the buzzer interface.
Optionally, the CPLD chip further includes: and the input interface of the power-on and power-off time sequence control module is respectively connected with the starting button interface, the reset button interface and the power input detection interface outside the CPLD chip, and the output interface of the power-on and power-off time sequence control module is connected with the power output control interface.
Optionally, the CPLD chip further includes: and the input interface of the power-on and power-off time sequence control module is respectively connected with the starting button interface, the reset button interface, the power input detection interface and the CPU interface processing module outside the CPLD chip, and the output interface of the power-on and power-off time sequence control module is connected with the power output control interface.
Optionally, the CPLD chip further includes: and the oscillator OSC clock module provides a working clock signal for the module in the CPLD chip.
The input and output control circuit of the mainboard provided by the embodiment of the utility model is realized by adopting a CPLD chip; the CPLD chip is used for realizing the input/output I/O control function corresponding to the development requirement on the mainboard circuit. Because the CPLD chip is adopted to realize the I/O control function, the corresponding functions can be expanded according to different requirements, thereby reducing the design and maintenance cost.
Additional features and advantages of the utility model will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model. The objectives and other advantages of the utility model may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the example serve to explain the principles of the utility model and not to limit the utility model.
FIG. 1 is a schematic diagram of an input/output control circuit of a motherboard according to an exemplary embodiment of the utility model;
FIG. 2 is a schematic diagram of an input/output control circuit of a motherboard according to another exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of an input/output control circuit of a motherboard according to another exemplary embodiment of the present invention;
fig. 4 is a schematic diagram of an input/output control circuit of a motherboard according to another exemplary embodiment of the utility model.
Fig. 5 is a schematic diagram of an input/output control circuit of a motherboard according to another exemplary embodiment of the utility model.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The existing I/O control ASIC chip has fixed functions and can not meet the requirements of function upgrading and expanding of subsequent products, and main relevant ASIC suppliers on the market come from abroad and have higher price.
For this reason, the embodiment of the present invention proposes that a CPLD (Complex Programmable logic device) chip may be used to replace an ASIC chip to implement I/O control, and further, a domestic CPLD chip may be used to replace an imported ASIC chip, and a CPLD chip of Programmable logic is used to implement an I/O control circuit function on a motherboard, and the functions required by customization and development according to the own characteristic needs or control needs of the motherboard may be satisfied, and the present invention has an extremely high cost performance.
As shown in fig. 1, the input/output control circuit of the motherboard according to an exemplary embodiment of the present invention is implemented by using a CPLD chip, where the CPLD chip includes: the temperature sensor queries the control module 11 and the fan speed control module 12, wherein:
the temperature sensor query control module 11 is connected with a CPU temperature sensor outside the CPLD chip through a temperature sensor interface 5 to acquire a temperature value of the CPU temperature sensor; the temperature sensor query control module 11 is further connected with the fan speed control module 12, and sends a control instruction to the fan speed control module 12;
the fan speed control module 12, an output interface of the fan speed control module 12 is connected with a CPU fan control interface outside the CPLD chip, and the fan speed control module 12 sends a signal for controlling the fan speed to the CPU fan control interface 9.
The CPLD chip is adopted to realize the function of an I/O control circuit on the mainboard, the cost can be reduced, and the temperature control function of the CPU can be realized through the arranged temperature sensor query control module and the fan speed control module.
In an exemplary embodiment, the output interface of the fan speed control module is an interface that transmits a PWM (pulse width modulation) signal whose duty ratio is positively correlated with the fan wind speed. That is, the larger the duty ratio, the larger the fan speed, the larger the wind speed, and conversely, the smaller the duty ratio, the smaller the fan speed, the smaller the wind speed.
In an exemplary embodiment, the temperature sensor interface is an I2C interface.
In an exemplary embodiment, as shown in fig. 2, the CPLD chip may further include: and the CPU interface processing module 13 is connected with the CPU management interface 4 outside the CPLD chip, receives the instruction sent by the CPU management interface 4, and the CPU interface processing module 13 is connected with the indicator lamp 16 outside the CPLD chip and sends a signal for turning on or off the indicator lamp 16.
In an exemplary embodiment, the CPU interface processing module may be connected to the temperature sensor query control module (as shown in fig. 3), the CPU interface processing module sends a control instruction for acquiring a temperature value to the temperature sensor query control module, and the temperature sensor query control module receives the control instruction for acquiring a temperature value sent by the CPU interface processing module.
In an exemplary embodiment, as shown in fig. 3, the CPLD chip may further include: and the buzzer control module 14 is connected with the CPU interface processing module 13, receives a buzzer alarm control instruction sent by the CPU interface processing module 13, and the buzzer control module 14 is also connected with a buzzer interface 8 outside the CPLD chip and sends an alarm sound signal to the buzzer interface. Through setting up bee calling organ control module, can realize alarming function.
In an exemplary embodiment, as shown in fig. 4, the CPLD chip may further include: and an input interface of the power-on and power-off timing sequence control module 15 is respectively connected with the power-on key interface 3, the reset key interface 2 and the power input detection interface 6 outside the CPLD chip, and an output interface of the power-on and power-off timing sequence control module 15 is connected with the power output control interface 7. One or more of the following functions can be realized by arranging the power-on and power-off timing control module 15: starting up, powering down when shutting down, restarting, and performing aging test.
Optionally, the input interface of the power-on/power-off timing control module 15 may also be connected with the CPU interface processing module 13. The following functions may be implemented: s3 sleep, S3 wake up.
In an exemplary embodiment, as shown in fig. 5, the CPLD chip may further include: an oscillator OSC clock module 10, wherein the OSC clock module 10 may be connected to the temperature sensor query control module and the fan speed control module, respectively. In addition, the OSC clock module 10 can also be connected with other functional modules (not shown in the figure) in the CPLD chip to provide an operating clock signal.
The embodiment shown in fig. 5 will be specifically described below.
As shown in fig. 5, the overall circuit of the CPLD chip 1 of the present embodiment may include: the external interface of the CPLD chip comprises an OSC clock module 10, an upper and lower electric time sequence control module 15, a CPU interface processing module 13, a buzzer control module 14, a temperature sensor query control module 11 and a fan speed control module 12, wherein the related external interface of the CPLD chip comprises: the system comprises a reset key interface 2, a starting key interface 3, a CPU management interface 4, a CPU temperature sensor interface 5, a power input detection interface 6, a power output control interface 7, a buzzer interface 8, a CPU fan control interface 9 and an indicator light 16.
The clock module 10 can obtain a clock source of 33MHz or approximately 33MHz by setting the frequency division parameter, the clock module 10 can provide a working clock for each functional circuit inside the CPLD, and the OSC clock module is arranged inside the CPLD, so that the power consumption of the system can be reduced.
The temperature sensor query control module 11 is connected with a CPU temperature sensor interface 5 outside the CPLD chip through a temperature sensor interface 5(I2C interface), acquires a temperature value of the CPU temperature sensor through an I2C interface, and sends a control instruction to the fan speed control module according to the temperature value; optionally, the temperature sensor query control module 11 may be connected to the CPU interface processing module 13, receive a control instruction for acquiring a temperature value sent by the CPU interface processing module 13, and acquire the temperature value through an I2C interface.
The fan speed control module 12 is connected to the temperature sensor query control module 11, receives the control command sent by the temperature sensor query control module 11, and sends a signal to the CPU fan control interface 9 according to the control command, where the signal is used to control the fan speed, for example, the speed of the fan can be dynamically controlled by adjusting a duty ratio, the duty ratio is positively correlated with the fan speed, and the larger the duty ratio, the larger the fan speed, and vice versa, so as to ensure that the CPU is at an appropriate temperature.
The CPU interface processing module 13 is connected to the CPU management interface 4, and is connected to the buzzer control module 14, the power-on/off sequence control module 15, and the LED indicator light 16, and is responsible for performing data interaction with the CPU, analyzing and analyzing the instruction information and the data information from the CPU management interface 4, and performing corresponding operations according to the received instruction information and data information, including but not limited to: buzzer control, fan control, LED indicator light, and the like, as well as status information collection (e.g., fan speed, temperature values, etc.).
The buzzer control module 14 is connected to the buzzer interface 8, receives the buzzer alarm control command from the CPU interface processing module 13, and sends an alarm sound signal to the buzzer interface 8 according to a pre-established correspondence between the buzzer alarm control command and the type of alarm sound, so as to control the buzzer to send out a corresponding alarm sound, for example: 1 short, 1 long, 2 short, 4 short, etc. (the short sound may be, for example, a sound lasting 1S, and the long sound may be, for example, a sound lasting 2S).
A power-up and power-down sequence control module 15, which is mainly responsible for power-up and power-down management control in various situations, including but not limited to one or more of the following: power-on and power-off sequence control, power-off and power-off sequence control during shutdown, power-off and sleep sequence control during S3, power-on and power-off sequence control during S3 awakening and aging test. The power output control interface 7 is connected with the reset key interface 2, the power-on key interface 3, the power input detection interface 6 and the CPU interface processing module 13, and sends a control signal to the power output control interface 6 according to an instruction signal received from the reset key interface 2 or the power-on key interface 3 or the power input detection interface 6 or the CPU interface processing module 13, wherein the control signal includes but is not limited to one or more of the following: the method comprises the following steps of starting up, powering down when the power is turned off, restarting the power up, sleeping at S3, waking up at S3 and the like, wherein the S3 mode refers to a mode that components except a memory stop working.
The above-mentioned modules can be implemented by using circuits in the prior art.
The control process of the CPLD chip is explained below.
Fan management control flow
The temperature sensor query control module 11 periodically reads (for example, the period may be 1S-2S) the temperature value of the CPU temperature sensor through the I2C interface, or the temperature sensor query control module 11 reads the temperature value of the CPU temperature sensor through the I2C interface according to the control instruction of the CPU interface processing module 13, the temperature sensor query control module 11 sends the read temperature value to the fan speed control module 12, and the fan speed control module 12 adjusts the duty ratio of the PWM waveform (for example, the period of the square wave is 25KHz) sent to the fan according to the value range in which the temperature value is located. The larger the PWM duty ratio is, the faster the fan rotating speed is; when the duty ratio is 100% (namely high level), the rotating speed of the fan reaches the maximum; at a duty cycle of 0 (i.e., low), the fan is off. For example, when the temperature value of the CPU temperature sensor is T1, the duty ratio corresponding to the first temperature range is D1 within a preset first temperature range, and when the temperature value of the CPU temperature sensor is T2, the duty ratio corresponding to the second temperature range is D2 within a preset second temperature range, where T1 is greater than T2 and D1 is greater than D2, that is, when the temperature is high, the rotation speed of the fan needs to be increased, and when the temperature is low, the rotation speed of the fan can be decreased.
Buzzer management control flow
CPU sends various preset buzzer sounding type information through CPU management interface 4, CPU interface processing module 13 sends the analyzed alarm sounding type to buzzer control module 14, buzzer control module 14 sends a PWM waveform (for example, PWM with frequency of 1KHz and duty ratio of 70%) to control buzzer sounding, and sends low-level buzzer to stop sounding. The type of alarm may include, but is not limited to, one or more of the following: memory exception, motherboard clock exception, graphics card exception, hardware not found, etc.
Power-on and power-off management control flow
The power-on and power-off timing sequence control module 15 controls the timing sequence of each power supply and IO switch on and off on the motherboard by outputting a control signal through the power output control interface 7 according to a power-on or power-off instruction sent by the power-on key interface 3, a restart instruction sent by the reset key interface 2, an S3 sleep instruction and an S3 wake-up instruction sent by the CPU interface processing module 13, a self-test aging instruction sent by the power input control module, and the like, and includes but is not limited to one or more of the following: ATX (Advanced Technology Extended) power supply, clock power supply, core power supply, IO power supply, USB (Universal Serial Bus), RGMII (Reduced Gigabit Media Independent Interface), PCIE _ RESET (RESET mode is a standard for high-speed Serial computer Extended Bus), and the like.
In the description of the present invention, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "mouth" structure ", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the structures referred to have specific orientations, are configured and operated in specific orientations, and thus, are not to be construed as limiting the present invention.
In the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "connected," "directly connected," "indirectly connected," "fixedly connected," "mounted," and "assembled" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; the terms "mounted," "connected," and "fixedly connected" may be directly connected or indirectly connected through intervening media, or may be connected through two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.
Claims (9)
1. An input/output control circuit of a motherboard, comprising: the input and output control circuit of the mainboard is realized by adopting a complex programmable logic device CPLD chip, and the CPLD chip comprises: temperature sensor inquiry control module and fan speed control module, wherein:
the temperature sensor query control module is connected with a CPU temperature sensor outside the CPLD chip through a temperature sensor interface to acquire a temperature value of the CPU temperature sensor; the temperature sensor query control module is also connected with the fan speed control module and sends a control instruction to the fan speed control module;
and the output interface of the fan speed control module is connected with the CPU fan control interface outside the CPLD chip, and the fan speed control module sends a signal for controlling the fan speed to the CPU fan control interface.
2. The I/O control circuit of claim 1, wherein,
the output interface of the fan speed control module is an interface for sending a Pulse Width Modulation (PWM) signal, and the duty ratio of the PWM signal is positively correlated with the fan wind speed.
3. The I/o control circuit of claim 1, wherein the temperature sensor interface is an I2C interface.
4. The input-output control circuit of motherboard according to claim 1, wherein said CPLD chip further comprises: and the CPU interface processing module is connected with a CPU management interface outside the CPLD chip and used for receiving an instruction sent by the CPU management interface, and the CPU interface processing module is connected with an indicator lamp outside the CPLD chip and used for sending a signal of turning on or turning off the indicator lamp.
5. The i/o control circuit of motherboard according to claim 4, wherein said CPU interface processing module is connected to said temperature sensor query control module, and said CPU interface processing module sends a control command for acquiring a temperature value to said temperature sensor query control module.
6. The input-output control circuit of motherboard according to claim 4, wherein said CPLD chip further comprises: and the buzzer control module is connected with the CPU interface processing module and used for receiving a buzzer alarm control instruction sent by the CPU interface processing module, and the buzzer control module is also connected with a buzzer interface outside the CPLD chip and used for sending an alarm sound signal to the buzzer interface.
7. The input-output control circuit of motherboard according to claim 1, wherein said CPLD chip further comprises: and the input interface of the power-on and power-off time sequence control module is respectively connected with the starting button interface, the reset button interface and the power input detection interface outside the CPLD chip, and the output interface of the power-on and power-off time sequence control module is connected with the power output control interface.
8. The input-output control circuit of motherboard according to claim 4, wherein said CPLD chip further comprises: and the input interface of the power-on and power-off time sequence control module is respectively connected with the starting button interface, the reset button interface, the power input detection interface and the CPU interface processing module outside the CPLD chip, and the output interface of the power-on and power-off time sequence control module is connected with the power output control interface.
9. The input-output control circuit of motherboard according to claim 1, wherein said CPLD chip further comprises: and the oscillator OSC clock module provides a working clock signal for the module in the CPLD chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121341530.4U CN215729733U (en) | 2021-06-16 | 2021-06-16 | Input/output control circuit of mainboard |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121341530.4U CN215729733U (en) | 2021-06-16 | 2021-06-16 | Input/output control circuit of mainboard |
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