CN215682247U

CN215682247U - Circuit for accelerating establishment of oscillator

Info

Publication number: CN215682247U
Application number: CN202121470916.5U
Authority: CN
Inventors: 徐明揆; 吴彤彤
Original assignee: Xtx Technology Inc
Current assignee: Xtx Technology Inc
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2022-01-28
Anticipated expiration: 2031-06-30

Abstract

The application discloses accelerate circuit that oscillator established includes: the charging module is connected with the discharging module in parallel, one end of the charging module and one end of the discharging module which are connected in parallel are connected with a working capacitor C0, at least one input end of an input end of the internal bias voltage Vbias, an input end of the reference voltage Vref and an input end of the capacitor upper plate voltage Vosc in the comparator is connected with the starting module, the starting module is used for charging the corresponding input end in the pulse period of a starting pulse signal en _ s, and the starting pulse signal en _ s is obtained by processing the enabling signal en through the starting module. The embodiment of the application provides a circuit for accelerating the establishment of an oscillator, which can effectively shorten the oscillation starting time of the oscillator and shorten the waiting time of user operation equipment.

Description

Circuit for accelerating establishment of oscillator

Technical Field

The utility model belongs to the technical field of integrated circuits, and particularly relates to a circuit for accelerating the establishment of an oscillator.

Background

Oscillators (OSCs) are widely used in various electronic products, particularly in integrated circuits, to provide clock signals to various digital signal processing blocks in the integrated circuits. The OSC circuit generally includes three major parts, a reference module (outputting a reference voltage Vref), a charging module and a discharging module (controlling a capacitor upper plate voltage Vosc), a comparator and a logic processing module. When the conventional OSC is started, the oscillation starting time of the OSC is limited by the setup time of each internal bias point (mainly including the reference voltage Vref, the capacitor super-plate voltage Vosc, and the programming voltage Vbias of the comparator), and the OSC can be operated after a long time.

Accordingly, the prior art is in need of improvement and development.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a circuit for accelerating the establishment of an oscillator, which can effectively shorten the oscillation starting time of the oscillator and shorten the waiting time of user operation equipment.

In order to solve the technical problem, a circuit for accelerating establishment of an oscillator provided in an embodiment of the present application includes: the system comprises a reference module, a comparator, a logic processing module, a charging module, a discharging module and at least one starting module, wherein the reference module, the comparator, the charging module and the starting module are respectively connected with a power supply VCC, the power supply VCC provides an internal bias voltage Vbias for the comparator, and the reference module and the starting module are respectively connected with an enabling signal en of an oscillator;

the reference module is connected with the comparator and used for providing a reference voltage Vref for the comparator, the charging module is connected with the discharging module in parallel, one end of the two parallel-connected modules is connected with a working capacitor C0, an upper plate of the working capacitor C0 is connected with the comparator and used for providing a capacitor upper plate voltage Vosc for the comparator, the other end of the two parallel-connected modules is connected with the comparator through the logic processing module, the comparator is used for comparing whether the capacitor upper plate voltage Vosc is greater than the reference voltage Vref or not, the logic processing module is used for outputting a clock signal Vosc _ clk according to a comparison result of the comparator, and the clock signal Vosc _ is used for controlling the charging module to charge the working capacitor C0 or controlling the discharging module to discharge the working capacitor C0 and outputting the clock signal Vosc _ clk to a load;

in the comparator, at least one of an input end of the internal bias voltage Vbias, an input end of the reference voltage Vref, and an input end of the capacitor upper plate voltage Vosc is connected with the starting module, the starting module is configured to charge a corresponding input end during a pulse period of a starting pulse signal en _ s, and the starting pulse signal en _ s is obtained by processing the enable signal en by the starting module.

Furthermore, the starting module comprises a pulse signal generating module and a circuit module, wherein one end of the circuit module is connected with the power supply VCC, and the other end of the circuit module is connected with a corresponding input end; the pulse signal generation module comprises a reversing unit, a delaying unit and a combining unit which are connected in sequence, the reversing unit and the combining unit are respectively connected to the enable signal en, the reversing unit is used for performing reversing operation on the enable signal en and generating a reverse signal enb, the delaying unit is used for performing delaying processing on the reverse signal enb and generating a delayed signal enb _ delay, the combining unit is used for performing combining operation on the enable signal en and the delayed signal enb _ delay and generating a starting pulse signal en _ s, and the starting pulse signal en _ s is input to the circuit module so that the circuit module charges a corresponding input end in a pulse period of the starting pulse signal en _ s.

Further, the circuit module comprises a second NMOS transistor nm2 and a third NMOS transistor nm3 which are sequentially connected in series, the drain of the second NMOS transistor nm2 is connected with the power VCC, the source of the second NMOS transistor nm2 is connected with the drain and the gate of the third NMOS transistor nm3, the gate of the second NMOS transistor nm2 is used for accessing the start pulse signal en _ s, and the source of the third NMOS transistor nm3 is connected with the corresponding input end.

Further, the circuit module further comprises at least one fourth NMOS transistor nm4, the at least one fourth NMOS transistor nm4 is connected in series between the third NMOS transistor nm3 and the corresponding input terminal, and the source of the previous fourth NMOS transistor nm4 is connected to the drain and the gate of the next fourth NMOS transistor nm 4.

Further, the above-mentioned benchmark module includes first resistance R1 and second resistance R2 that establish ties in proper order, first resistance R1 with insert between the second resistance R2 the comparator, first resistance R1 connects through second PMOS pipe pm2 the power VCC, second PMOS pipe pm 2's source with the power VCC connects, second PMOS pipe pm 2's drain electrode with first resistance R1 connects, second PMOS pipe pm 2's grid is used for inserting enable signal en.

Further, the reference module further comprises at least one third resistor R3, and the at least one third resistor R3 is connected in series with the second resistor R2.

Further, the above-mentioned module of charging includes first PMOS pipe pm1, the drain electrode of first PMOS pipe pm1 with electric capacity C0 is connected, the grid of first PMOS pipe pm1 with the logic processing module is connected, the emission set of first PMOS pipe pm1 with power VCC connects.

Further, the discharge module comprises a first NMOS transistor nm1, a drain of the first NMOS transistor nm1 is connected to the capacitor C0, a gate of the first NMOS transistor nm1 is connected to the logic processing module, and a source of the first NMOS transistor nm1 is grounded.

Further, the circuit further comprises a frequency adjusting module, wherein the frequency adjusting module is connected with the power supply VCC and is connected with the charging module through a switch S0.

Further, in the comparator, the input end of the internal bias voltage Vbias, the input end of the reference voltage Vref, and the input end of the capacitor upper plate voltage Vosc are all connected to the starting module.

The circuit for accelerating the establishment of the oscillator is characterized in that the starting module is arranged at least one of the input end of the internal bias voltage Vbias of the comparator, the input end of the reference voltage Vref and the input end of the upper plate voltage Vosc of the capacitor, and at least one bias point of the comparator is charged through the starting module, so that the establishment of the corresponding bias point is accelerated, the oscillation starting time of the oscillator is effectively shortened, and the waiting time of a user for operating equipment is shortened.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Fig. 1 is a schematic diagram of an embodiment of the present application.

Fig. 2 is a schematic diagram of a pulse signal generation module according to an embodiment of the present application.

Fig. 3 is a timing diagram of a pulse signal generating module according to an embodiment of the present disclosure.

Fig. 4 is a diagram of a setup of an oscillator using an embodiment of the present application.

Fig. 5 is a diagram of the setup of a prior art oscillator.

Description of reference numerals: 100. A reference module; 200. a comparator; 300. a logic processing module; 400. a charging module; 500. a discharge module; 600. a starting module; 610. a pulse signal generation module; 611. an inversion unit; 612. a delay unit; 613. a merging unit; 620. a circuit module; 700. and a frequency adjusting module.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the utility model. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.

As shown in fig. 1, the circuit for accelerating the establishment of the oscillator of the present invention comprises: the circuit comprises a reference module 100, a comparator 200, a logic processing module 300, a charging module 400, a discharging module 500 and at least one starting module 600, wherein the reference module 100, the comparator 200, the charging module 400 and the starting module 600 are respectively connected with a power supply VCC, the power supply VCC provides an internal bias voltage Vbias for the comparator 200, and the reference module 100 and the starting module 600 are respectively connected with an enabling signal en of an oscillator;

the reference module 100 is connected to the comparator 200, and is configured to provide a reference voltage Vref for the comparator 200, the charging module 400 is connected to the discharging module 500 in parallel, one end of the two parallel connected modules is connected to a working capacitor C0, an upper plate of the working capacitor C0 is connected to the comparator 200, and is configured to provide a capacitor upper plate voltage Vosc for the comparator 200, the other end of the two parallel connected modules is connected to the comparator 200 through the logic processing module 300, the comparator 200 is configured to compare whether the capacitor upper plate voltage Vosc is greater than the reference voltage Vref, the logic processing module 300 is configured to output a clock signal Vosc _ clk according to a comparison result of the comparator 200, the clock signal Vosc _ clk is configured to control the charging module 400 to charge the working capacitor C0, or control the discharging module 500 to discharge the working capacitor C0, and output to the load;

in the comparator 200, at least one of the input terminal of the internal bias voltage Vbias, the input terminal of the reference voltage Vref, and the input terminal of the capacitor super plate voltage Vosc is connected to the start module 600, the start module 600 is configured to charge the corresponding input terminal during a pulse period of a start pulse signal en _ s, and the start pulse signal en _ s is obtained by processing the enable signal en by the start module 600.

In a specific operation, after the oscillator is powered on, the power supply VCC charges the operating capacitor C0, the capacitor upper plate voltage Vosc and the internal bias voltage Vbias are input to the comparator 200, and when the enable signal en of the oscillator arrives, the reference voltage Vref is also input to the comparator 200. The comparator 200 compares the capacitor super-board voltage Vosc with the reference voltage Vref, the logic processing module 300 outputs a clock signal Vosc _ clk according to the comparison result of the comparator 200, and the charging and discharging processes of the capacitor C0 are controlled by the clock signal Vosc _ clk, so as to form a closed-loop control: when the capacitor upper panel voltage Vosc is greater than the reference voltage Vref, the comparator 200 is turned to a high level, the clock signal Vosc _ clk output by the logic processing module 300 according to the comparison result is a high level signal, the charging module 400 is turned off, the discharging module 500 is turned on, and the working capacitor C0 performs a discharging process through the discharging module 500; when the working capacitor C0 discharges to a state where the capacitor top plate voltage Vosc is less than the reference voltage Vref, the comparator 200 is turned to a low level, the clock signal Vosc _ clk output by the logic processing module 300 according to the comparison result is a low level signal, at this time, the discharging module 500 is turned off, the charging module 400 is turned on, and the charging module 400 charges the capacitor, thereby repeating the above processes; meanwhile, the clock signal Vosc _ clk is output to the load to provide the load with the clock signal.

The working process of the oscillator is established only on the premise that each bias point in the oscillator can be established, according to the technical scheme, the enabling signal en is processed by setting the starting module 600 to generate a starting pulse signal en _ s, and during the pulse period of the starting pulse signal en _ s, the starting module 600 is effective, the power VCC can be switched on to charge the corresponding input end, the establishment of the corresponding bias point is accelerated, so that the oscillation starting time of the oscillator is effectively shortened, and the waiting time of a user for operating equipment is shortened. Specifically, the effective time of the start pulse signal en _ s may be adjusted by adjusting the pulse width of the start pulse signal en _ s according to the working requirement, and when the start pulse signal en _ s is ended, the power source VCC stops charging the corresponding input terminal.

Specifically, when a start module 600 is provided, it is preferable that an input terminal with the longest programming time is connected to the start module 600, so that the oscillator performs faster start-up as a whole. In the embodiment, the start module 600 is connected to an input terminal of the reference voltage Vref. In a preferred embodiment, in the comparator 200, the start module 600 is connected to an input terminal of the internal bias voltage Vbias, an input terminal of the reference voltage Vref, and an input terminal of the capacitor upper plate voltage Vosc. Specifically, the comparator 200 and the logic processing module 300 can adopt the existing technical means.

As shown in fig. 1, 2 and 3, in some preferred embodiments, the starting module 600 includes a pulse signal generating module 610 and a circuit module 620, one end of the circuit module 620 is connected to the power VCC, and the other end of the circuit module 620 is connected to a corresponding input terminal; the pulse signal generating module 610 includes an inverting unit 611, a delaying unit 612, and a combining unit 613 connected in sequence, the inverting unit 611 and the combining unit 613 are respectively connected to the enable signal en, the inverting unit 611 is configured to perform an inverting operation on the enable signal en and generate an inverted signal enb, the delaying unit 612 is configured to perform a delaying process on the inverted signal enb and generate a delayed signal enb _ delay, the combining unit 613 is configured to perform a combining operation on the enable signal en and the delayed signal enb _ delay and generate the start pulse signal en _ s, and the start pulse signal en _ s is input to the circuit module 620, so that the circuit module 620 charges a corresponding input terminal during a pulse period of the start pulse signal en _ s. Specifically, the inversion operation inverts the phase of the enable signal en by 180 °. In a specific application, the power VCC charges a corresponding input terminal through the circuit module 620, and whether the circuit module 620 is turned on or not is controlled by the start pulse signal en _ s, during a pulse period of the start pulse signal en _ s, the circuit module 620 is turned on, so that the corresponding input terminal can be charged, and specifically, the time of the delay unit 612 is adjusted, so as to adjust a pulse width of the start pulse signal en _ s. Specifically, the inverting unit 611, the delaying unit 612 and the combining unit 613 may adopt the existing technical means, for example, the inverting unit 611 adopts an inverter, the delaying unit 612 adopts a delay effector, and the combining unit 613 adopts an and gate.

As shown in fig. 1, in some preferred embodiments, the circuit module 620 includes a second NMOS transistor nm2 and a third NMOS transistor nm3 connected in series in sequence, a drain of the second NMOS transistor nm2 is connected to the power VCC, a source of the second NMOS transistor nm2 is connected to a drain and a gate of the third NMOS transistor nm3, a gate of the second NMOS transistor nm2 is used to receive the start pulse signal en _ s, and a source of the third NMOS transistor nm3 is connected to a corresponding input terminal. In specific application, the second NMOS transistor nm2 is biased by the start pulse signal en _ s, when the start pulse signal en _ s is valid, that is, the start pulse signal en _ s outputs a high level, the second NMOS transistor nm2 is turned on, so that the circuit module 620 is turned on, and when the start pulse signal en _ s outputs a low level, the second NMOS transistor nm2 is turned off, so that the circuit module 620 is turned off.

In some preferred embodiments, the circuit module 620 further includes at least one fourth NMOS transistor nm4, the at least one fourth NMOS transistor nm4 is connected in series between the third NMOS transistor nm3 and the corresponding input terminal, and the source of the previous fourth NMOS transistor nm4 is connected to the drain and the gate of the next fourth NMOS transistor nm 4. In specific application, the number of the fourth NMOS transistors nm4 is set according to current requirements, specifically, in this embodiment, a fourth NMOS transistor nm4 is set, a drain and a gate of the fourth NMOS transistor nm4 are connected with a source of the third NMOS transistor nm3, and a source of the fourth NMOS transistor nm4 is connected with a corresponding input terminal.

In some preferred embodiments, the reference module 100 includes a first resistor R1 and a second resistor R2 connected in series in sequence, the first resistor R1 and the second resistor R2 are connected to the comparator 200, the first resistor R1 is connected to the power VCC through a second PMOS transistor pm2, a source of the second PMOS transistor pm2 is connected to the power VCC, a drain of the second PMOS transistor pm2 is connected to the first resistor R1, and a gate of the second PMOS transistor pm2 is connected to the enable signal en. In specific application, the enable signal en biases the second PMOS transistor pm2, when the enable signal en arrives, the second PMOS transistor pm2 is turned on, and the power VCC is turned on with the reference module 100, so that the operation of the oscillator is controlled. Specifically, the power supply VCC inputs a reference current Iref to the reference module 100.

In some preferred embodiments, the reference module 100 further includes at least one third resistor R3, and the at least one third resistor R3 is connected in series with the second resistor R2. In a specific application, the number of the third resistors R3 is set according to the current requirement, specifically, in the embodiment, a third resistor R3 is provided, and the third resistor R3 is connected in series with the second resistor R2 and then grounded.

In some preferred embodiments, the charging module 400 includes a first PMOS transistor pm1, a drain of the first PMOS transistor pm1 is connected to the capacitor C0, a gate of the first PMOS transistor pm1 is connected to the logic processing module 300, and an emission set of the first PMOS transistor pm1 is connected to the power source VCC. Specifically, the power source VCC inputs the first operating current I1 to the charging module 400.

In some preferred embodiments, the discharge module 500 includes a first NMOS transistor nm1, a drain of the first NMOS transistor nm1 is connected to the capacitor C0, a gate of the first NMOS transistor nm1 is connected to the logic processing module 300, and a source of the first NMOS transistor nm1 is grounded.

In a specific application, the first PMOS transistor pm1 and the first NMOS transistor nm1 are biased by the upper clock signal Vosc _ clk, when the clock signal Vosc _ clk is a high level signal, the first NMOS transistor nm1 is turned on, and when the clock signal Vosc _ clk is a low level signal, the first PMOS transistor pm1 is turned on.

In some preferred embodiments, the circuit further includes a frequency adjustment module 700, and the frequency adjustment module 700 is connected to the power source VCC and connected to the charging module 400 through a switch S0. In specific application, when the oscillator has different frequency output requirements, whether the charging module 400 is connected with a plurality of paths of current or not can be controlled by switching on and off the switch S0, and the working capacitor C0 is charged by different charging currents, so that different frequency outputs can be obtained. Specifically, the frequency adjustment module 700 is connected to the power source VCC and inputs a second operating current I2 to the charging module 400.

In some preferred embodiments, the comparator 200 is connected in parallel with a bias capacitor Cbias, one end of the bias capacitor Cbias is connected to the power source VCC, and the other end is grounded. Specifically, the reference current Iref is input to the power supply VCC versus the comparator 200.

According to the circuit for accelerating the establishment of the oscillator, the starting module 600 is arranged at least one of the input end of the internal bias voltage Vbias of the comparator 200, the input end of the reference voltage Vref and the input end of the capacitor superior plate voltage Vosc, at least one bias point of the comparator 200 is charged through the starting module 600, the establishment of the corresponding bias point is accelerated, the oscillation starting time of the oscillator is effectively shortened, and the waiting time of a user for operating equipment is shortened. Fig. 4 and 5 show a diagram of a setup condition of an oscillator using an embodiment of the present application, in which osc _ clk1 is an output oscillation signal, and the oscillation starting time is t 1; FIG. 5 is a diagram of a prior art oscillator setup in which osc _ clk0 is the output oscillation signal and the attack time is t 0; as can be seen from fig. 4 and 5, the oscillation starting time t1 of the oscillator using the embodiment of the present application is significantly smaller than the oscillation starting time t0 of the oscillator of the prior art, specifically, t1=100ns, and t0=2 μ s.

In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It is to be understood that the utility model is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the utility model as defined by the appended claims.

Claims

1. A circuit for expediting oscillator set-up, comprising: the circuit comprises a reference module (100), a comparator (200), a logic processing module (300), a charging module (400), a discharging module (500) and at least one starting module (600), wherein the reference module (100), the comparator (200), the charging module (400) and the starting module (600) are respectively connected with a power supply VCC, the power supply VCC provides an internal bias voltage Vbias for the comparator (200), and the reference module (100) and the starting module (600) are respectively connected with an enabling signal en of an oscillator;

the reference module (100) is connected with the comparator (200) and used for providing a reference voltage Vref for the comparator (200), the charging module (400) is connected with the discharging module (500) in parallel, one end of the charging module (400) is connected with a working capacitor C0, the upper plate of the working capacitor C0 is connected with the comparator (200) and used for providing a capacitor upper plate voltage Vosc for the comparator (200), the other end of the charging module (400) is connected with the comparator (200) through the logic processing module (300), the comparator (200) is used for comparing whether the capacitor upper plate voltage Vosc is larger than the reference voltage Vref or not, the logic processing module (300) is used for outputting a clock signal Vosc _ clk according to the comparison result of the comparator (200), and the clock signal Vosc _ clk is used for controlling the charging module (400) to charge the working capacitor C0, or controlling the discharging module (500) to discharge the working capacitor C0 and output the working capacitor C0 to a load;

in the comparator (200), at least one of an input terminal of the internal bias voltage Vbias, an input terminal of the reference voltage Vref, and an input terminal of the capacitor super plate voltage Vosc is connected with the start module (600), the start module (600) is configured to charge the corresponding input terminal during a pulse period of a start pulse signal en _ s, and the start pulse signal en _ s is obtained by processing the enable signal en by the start module (600).

2. The circuit for accelerating oscillator setup according to claim 1, wherein the start-up module (600) comprises a pulse signal generation module (610) and a circuit module (620), one end of the circuit module (620) is connected to the power source VCC, and the other end of the circuit module (620) is connected to the corresponding input terminal;

the pulse signal generating module (610) comprises an inverting unit (611), a delay unit (612) and a merging unit (613) which are connected in sequence, the inversion unit (611) and the merging unit (613) are respectively connected to the enable signal en, the inversion unit (611) is used for performing inversion operation on the enable signal en, and generates an inverted signal enb, the delay unit (612) is configured to delay the inverted signal enb, and generates a delay signal enb _ delay, the combining unit (613) is configured to perform a combining operation on the enable signal en and the delay signal enb _ delay, and generating the start pulse signal en _ s, which is input to the circuit module (620), so that the circuit module (620) charges the respective input terminal during a pulse of the start pulse signal en _ s.

3. The circuit for accelerating the establishment of the oscillator according to claim 2, wherein the circuit module (620) comprises a second NMOS transistor nm2 and a third NMOS transistor nm3 which are sequentially connected in series, a drain of the second NMOS transistor nm2 is connected to the VCC power supply, a source of the second NMOS transistor nm2 is connected to a drain and a gate of the third NMOS transistor nm3, a gate of the second NMOS transistor nm2 is used for accessing the start pulse signal en _ s, and a source of the third NMOS transistor nm3 is connected to a corresponding input terminal.

4. The circuit for accelerating the oscillator building according to claim 3, wherein the circuit module (620) further comprises at least one fourth NMOS transistor nm4, the at least one fourth NMOS transistor nm4 is connected in series between the third NMOS transistor nm3 and the corresponding input terminal, and the source of the previous fourth NMOS transistor nm4 is connected with the drain and the gate of the next fourth NMOS transistor nm 4.

5. The circuit for accelerating the establishment of the oscillator according to claim 1, wherein the reference module (100) comprises a first resistor R1 and a second resistor R2 connected in series in sequence, the comparator (200) is connected between the first resistor R1 and the second resistor R2, the first resistor R1 is connected to the power VCC through a second PMOS pm2, the source of the second PMOS pm2 is connected to the power VCC, the drain of the second PMOS pm2 is connected to the first resistor R1, and the gate of the second PMOS pm2 is connected to the enable signal en.

6. The circuit for accelerating oscillator setup according to claim 5, wherein the reference module (100) further comprises at least one third resistor R3, the at least one third resistor R3 being connected in series with the second resistor R2.

7. The circuit for accelerating the oscillator to build up according to claim 1, wherein the charging module (400) comprises a first PMOS transistor pm1, the drain of the first PMOS transistor pm1 is connected to the capacitor, the gate of the first PMOS transistor pm1 is connected to the logic processing module (300), and the emission set of the first PMOS transistor pm1 is connected to the power VCC.

8. The circuit for accelerating the oscillator building according to claim 1, wherein the discharging module (500) comprises a first NMOS transistor nm1, the drain of the first NMOS transistor nm1 is connected to the capacitor, the gate of the first NMOS transistor nm1 is connected to the logic processing module (300), and the source of the first NMOS transistor nm1 is grounded.

9. The circuit for accelerating the oscillator setup according to claim 1, further comprising a frequency adjustment module (700), wherein the frequency adjustment module (700) is connected to the power source VCC and connected to the charging module (400) via a switch S0.

10. The circuit for accelerating oscillator setup according to claim 1, wherein the input terminal of the internal bias voltage Vbias, the input terminal of the reference voltage Vref and the input terminal of the capacitor super plate voltage Vosc are all connected to the start-up module (600) in the comparator (200).