CN215680696U - Display panel and display device - Google Patents

Abstract

The disclosure relates to a display panel and a display device, wherein the display panel is positioned on one side of an outermost cofferdam far away from a display area, a planarization layer group is arranged on one side of a first lead far away from a substrate base plate, and a second lead is arranged on one side of the planarization layer group far away from the substrate base plate. The second lead can be arranged on one side, far away from the display area, of the outer side cofferdam, so that the requirement that the frame of an OLED product is extremely narrowed is met. The planarization layer group enables one side, away from the substrate base plate, of the first routing line to be flat, the second lead wires can be uniformly arranged on one flat surface, and when the second lead wires are arranged on one side, away from the display area, of the outermost cofferdam, the risk that the second lead wires are not uniformly distributed and are possibly contacted with each other to cause short circuit due to the fact that one side, away from the display area, of the outermost cofferdam is uneven can be eliminated.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device including the same.

Background

With the continuous upgrade and update of products, customers have made a very narrow requirement on the bezel of an Organic electroluminescent Display (OLED) product, and the bezel narrowing also has made a higher requirement on the design.

At present, the touch leads are placed between the display area and the innermost cofferdam, however, after the frame is narrowed, the distance between the display area and the innermost cofferdam is reduced, all the touch leads cannot be placed between the display area and the innermost cofferdam, and the wiring mode between the innermost cofferdam and the display area cannot meet the requirement.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The disclosure aims to overcome the problem that the wiring mode between the innermost cofferdam and the display area in the prior art cannot meet the extremely narrow requirement of a frame, and provides a display panel and a display device which utilize the side, far away from the display area, of the outermost cofferdam for wiring.

According to one aspect of the present disclosure, a display panel is provided, which has a display area and a non-display area connected to the display area, a plurality of cofferdams are disposed in the non-display area, the cofferdams being sequentially distant from the display area, the display panel including a substrate, a first lead, a planarization layer group, and a second lead; the first lead is arranged on one side of the substrate base plate and extends to one side of the outermost cofferdam far away from the display area; the planarization layer group is arranged on one side of the first lead wire, which is far away from the substrate base plate, and is positioned on one side of the outermost cofferdam, which is far away from the display area; and the second lead is arranged on one side of the planarization layer group, which is far away from the substrate base plate, and the orthographic projection of at least part of the second lead on the substrate base plate is overlapped with the orthographic projection of the first lead on the substrate base plate and is positioned in the orthographic projection of the planarization layer group on the substrate base plate.

In one embodiment of the disclosure, a gap is provided between the set of planarization layers and the outermost bank.

In one embodiment of the present disclosure, the width of the gap is greater than or equal to 20 microns.

In one embodiment of the present disclosure, the second lead includes a first portion extending perpendicular to an extending direction of the dam and a second portion extending parallel to the extending direction of the dam; the orthographic projection of the first part on the substrate base plate is overlapped with the orthographic projection of the cofferdam on the substrate base plate, and the orthographic projection of the second part on the substrate base plate is positioned in the orthographic projection of the planarization layer group on the substrate base plate.

In one embodiment of the disclosure, the distance between the outermost edge of the second portion away from the display area and the outermost edge of the planarization layer group away from the display area is 10-20 um.

In one embodiment of the present disclosure, the display panel includes a plurality of thin film transistors arranged in an array on one side of the substrate, the thin film transistors including a first source electrode, and a fourth planarization layer disposed on one side of the first source electrode away from the substrate.

In one embodiment of the present disclosure, the planarization layer group includes a first planarization layer, and the first planarization layer and the fourth planarization layer are disposed in the same layer and the same material.

In one embodiment of the present disclosure, the display panel further includes a second source electrode and a fifth planarization layer in the display region, the second source electrode is disposed on a side of the fourth planarization layer away from the substrate base plate, and the fifth planarization layer is disposed on a side of the second source electrode away from the substrate base plate.

In one embodiment of the present disclosure, the planarization layer group further includes a second planarization layer, the second planarization layer is disposed on a side of the first planarization layer away from the substrate base plate, and the second planarization layer and the fifth planarization layer are disposed in the same layer and the same material.

In one embodiment of the present disclosure, the display panel further includes a pixel defining layer disposed on a side of the fifth planarization layer away from the substrate.

In one embodiment of the present disclosure, the planarization layer group further includes a third planarization layer disposed on a side of the second planarization layer or the first planarization layer away from the substrate, and the third planarization layer and the pixel defining layer are disposed in the same layer and the same material.

The display panel further comprises a light-emitting device, an encapsulation layer and a touch layer; the packaging layer covers the cofferdam; the touch layer is arranged on the packaging layer and comprises a touch electrode and a touch lead connected with the touch electrode.

In one embodiment of the present disclosure, the first lead includes one or both of a gate driving line, a data line.

In one embodiment of the present disclosure, the second lead includes at least one of a plurality of touch leads, a plurality of shield lines, and a plurality of ground lines.

According to another aspect of the present disclosure, there is provided a display device including the display panel according to one aspect of the present disclosure.

According to the display panel, the cofferdam is located on the outermost side, the side, far away from the display area, of the cofferdam, the first lead is provided with the planarization layer set on the side, far away from the substrate base plate, of the first lead, and the second lead is provided on the side, far away from the substrate base plate, of the planarization layer set. The second lead can be arranged on one side, far away from the display area, of the outer side cofferdam, so that the requirement that the frame of an OLED product is extremely narrowed is met. The planarization layer group enables one side, away from the substrate base plate, of the first routing line to be flat, the second lead wires can be uniformly arranged on one flat surface, and when the second lead wires are arranged on one side, away from the display area, of the outermost cofferdam, the risk that the second lead wires are not uniformly distributed and are possibly contacted with each other to cause short circuit due to the fact that one side, away from the display area, of the outermost cofferdam is uneven can be eliminated.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic cross-sectional structure outside a display area of a display panel according to an embodiment of the disclosure.

Fig. 2 is a schematic cross-sectional structure diagram of a first display panel according to an embodiment of the disclosure.

Fig. 3 is a schematic cross-sectional structure diagram of a second display panel according to an embodiment of the disclosure.

Fig. 4 is a schematic cross-sectional structure diagram of a third display panel according to an embodiment of the disclosure.

Fig. 5 is a schematic cross-sectional structure diagram of a fourth display panel according to an embodiment of the disclosure.

Fig. 6 is a schematic plan view of a partial structure of a display panel according to an embodiment of the present disclosure.

In the figure: 1-display region, 10-substrate, 111-active layer, 112-gate insulating layer, 113-gate electrode, 114-dielectric layer, 1141-interlayer insulating layer, 1142-interlayer dielectric layer, 115-first source electrode, 116-drain electrode, 117-second source electrode, 12-light emitting layer, 121-first electrode, 122-light emitting element, 123-second electrode, 13-fourth planarizing layer, 14-fifth planarizing layer, 15-pixel defining layer, 16-encapsulating layer, 17-buffer layer, 18-touch control layer, 181-first touch control layer, 182-second touch control layer, 183-first insulating layer, 184-second insulating layer, 19-protective layer, 2-non-display region, 20-bank, 201-first bank, 202-second bank, 2001-first filling layer, 2002-second filling layer, 2003-third filling layer, 21-first lead, 211-gate line, 22-first planarization layer, 23-second planarization layer, 24-third planarization layer, 25-second lead, 26-third insulation layer, 27-power supply line.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

As shown in fig. 1, the display panel may dispose the second lead on a side of the non-display area 2 away from the display area, so as to satisfy the requirement of the OLED product that the frame is extremely narrow. However, it can be seen that when the first leads 21 extend to the non-display area 2, irregularities are formed on the side of the first leads 21 away from the substrate, and the second leads 25 are disposed on the irregular surface, for example, when the second leads 25 are disposed on the concave surface as shown in the figure, the concave surface is likely to cause short circuit of the second leads 25 above. Note that the first lead 21 may include a gate line 211.

The disclosed embodiments provide a display panel. As shown in fig. 2 to 6, the display panel has a display region 1 and a non-display region 2 connected to the display region 1, the non-display region 2 is provided with a plurality of banks sequentially distant from the display region, and the display panel includes a substrate 10, a first lead 21, a planarization layer group, and a second lead 25; the first lead 21 is arranged at one side of the substrate base plate 10 and extends to one side of the outermost cofferdam 20 far away from the display area; the planarization layer group is arranged on one side of the first lead 21 far away from the substrate base plate 10 and is positioned on one side of the outermost cofferdam 20 far away from the display area; the second lead is provided on the side of the planarization layer group away from the base substrate 10, and the orthographic projection of the second lead 25 on the base substrate 10 is located within the orthographic projection of the planarization layer group on the base substrate 10.

The second leads 25 may be disposed on a side of the outermost bank 20 away from the display area, the planarization layer set planarizes a side of the first traces 21 away from the substrate 10, the second leads 25 may be uniformly arranged on a planar surface, and when the second leads 25 are disposed on a side of the outermost bank away from the display area 1, a risk of short circuit caused by uneven distribution of the second leads 25 and possible contact between the second leads 25 due to uneven distribution of the second leads 25 caused by uneven side of the outermost bank 20 away from the display area 1 may be eliminated. Therefore, the second lead 25 can be disposed on the side of the outermost bank 20 away from the display region 1, thereby meeting the requirement of the OLED product that the frame is extremely narrow.

As shown in fig. 2 to 5, the display region 1 has a display layer group including an array substrate and a light emitting layer 12; wherein, the array substrate is arranged at one side of the substrate 10; the light-emitting layer 12 is arranged on one side of the array substrate far away from the substrate 10; the light emitting layer 12 may be provided with light emitting units distributed in an array.

A fourth planarization layer 13 is disposed between the array substrate and the light emitting layer 12, a fifth planarization layer 14 may be disposed on a side of the fourth planarization layer 13 away from the substrate 10, and a pixel defining layer 15 may be disposed on a side of the fifth planarization layer 14 away from the substrate 10.

The display layer is arranged on the substrate 10 and can be directly laminated on the surface of the substrate 10; alternatively, the buffer layer 17 may be provided on the surface of the base substrate 10, a display layer group may be laminated on the surface of the buffer layer 17 away from the base substrate 10, and the buffer layer 17 may be made of an insulating material.

The array substrate may include a plurality of thin film transistors, which may be of a top gate type or a bottom gate type, and taking the top gate type thin film transistor as an example, the thin film transistors may include an active layer 111, a gate insulating layer 112, a gate electrode 113, and source and drain electrodes, where:

the active layer 111 is disposed on one side of the substrate 10, and may be made of polysilicon, amorphous silicon, or the like, and the active layer 111 may include a channel region and two doped regions of different doping types located on both sides of the channel region.

The gate insulating layer 112 may cover the active layer 111 and the substrate base plate 10, and the material of the gate insulating layer 112 is an insulating material such as silicon oxide.

The gate electrode 113 is disposed on a side of the gate insulating layer 112 away from the substrate 10, and is opposite to the active layer 111, that is, a projection of the gate electrode 113 on the substrate 10 is located within a projection range of the active layer 111 on the substrate 10, for example, the projection of the gate electrode 113 on the substrate 10 is overlapped with a projection of a channel region of the active layer 111 on the substrate 10.

The thin film transistor further includes a dielectric layer 114, the dielectric layer 114 covers the gate 113 and the gate insulating layer 112, for example, the dielectric layer 114 may include an interlayer insulating layer 1141 and an interlayer dielectric layer 1142 sequentially stacked in a direction away from the substrate 10, and the interlayer insulating layer 1141 and the interlayer dielectric layer 1142 are insulating materials, but the materials of the two may be different. Of course, the dielectric layer 114 may have a single-layer structure.

The source and drain are disposed on the surface of the dielectric layer 114 away from the substrate 10, and the source and drain includes a first source 115 and a drain 116, the first source 115 and the drain 116 are connected to the active layer 111, for example, the first source 115 and the drain 116 are respectively connected to two doped regions of the corresponding active layer 111 through vias.

As shown in fig. 2 and fig. 3, the source and drain electrodes may include a first source electrode 115, a fourth planarization layer 13 is disposed on a side of the source and drain electrodes away from the substrate 10, and a surface of the fourth planarization layer 13 away from the substrate 10 is a plane. As shown in fig. 4 and 5, the source and drain electrodes may further include a second source electrode 117, and the second source electrode 117 is connected to the first source electrode 115. A fifth planarization layer is arranged on the side of the second source electrode 117 away from the substrate 10, and covers the second source electrode 117 and the fourth planarization layer 13. A protective layer may be further disposed on a side of the first source electrode 115 away from the substrate base plate 10, and the protective layer covers the first source electrode 115 and the drain electrode 116. The fourth planarizing layer 13 covers the protective layer.

The display panel may further include a light emitting unit layer disposed on a side of the fourth planarization layer 13 or the fifth planarization layer 14 away from the array substrate. The light emitting unit layer may include a plurality of light emitting units, each of which may include a first electrode 121, a light emitting element 122, a second electrode 123, and a pixel defining layer 15, the first electrode 121 is located on a surface of the array substrate away from the substrate 10, the light emitting element 122 is located on a surface of the first electrode 121 away from the substrate 10, and the second electrode 123 is located on a surface of the light emitting element 122 away from the substrate 10. The light emitting layer 12 can be driven to emit light by the first electrode 121 and the second electrode 123 to display an image.

The first electrode 121 is connected to the first source 115 or the second source 117. The side of the first electrode 121 away from the substrate 10 is provided with a pixel defining layer 15. When the thin film transistor includes only the first source electrode 115, the first electrode 121 is connected to the first source electrode 115, and the pixel defining layer 15 is disposed to cover the first electrode 121 and the fourth planarizing layer 13. When the thin film transistor further includes the second source electrode 117, the first electrode 121 is connected to the second source electrode 117, and the pixel defining layer 15 is disposed to cover the first electrode 121 and the fifth planarizing layer 14.

The second electrode 123 can serve as a cathode, the first electrode 121 can serve as an anode, and the light emitting element 122 can be driven to emit light by applying a signal to the first electrode 121, and the specific light emitting principle is not described in detail herein. The light emitting element 122 may include an organic electroluminescent material, and may be formed by a process such as evaporation. For example, the light emitting element 122 may include a hole injection layer, a hole transport layer, a light generation layer, an electron transport layer, and an electron injection layer, which are sequentially stacked on the first electrode 121 layer.

In addition, the display panel of the present disclosure may further include an encapsulation layer 16, which may be disposed on the light emitting unit; the encapsulation layer 16 is disposed on the side of the light-emitting layer 12 away from the substrate 10 to encapsulate the light-emitting layer and prevent water and oxygen corrosion. The encapsulation layer may be a single layer or a multi-layer structure, and the material thereof may include organic or inorganic materials, which is not particularly limited herein.

The display region 1 further includes a touch control layer 18, and the touch control layer 18 may be a mutual capacitance type touch control, wherein the touch control layer 18 includes a first touch control layer 181 and a second touch control layer 182, the first touch control layer 181 is a Metal Mesh (MM), and the second touch control layer 182 is a Bridge Metal layer (BM). The metal mesh is located in the display area and can be divided into a touch driving (Tx) metal mesh and a touch sensing (Rx) metal mesh according to the horizontal and vertical directions, wherein one of the touch sensing (Rx) metal mesh and the touch driving (Tx) metal mesh is connected with each other, and the other one is connected through a bridging metal layer. A first insulating layer 183 is disposed on a side of the first tactile control layer 181 away from the base substrate 10, and a second insulating layer 184 is disposed on a side of the second tactile control layer 182 away from the base substrate 10. The side of the second insulating layer 184 remote from the base substrate 10 is provided with a protective layer 19.

A plurality of cofferdams 20 which are sequentially far away from the display area 1 are arranged in the non-display area 2, the plurality of cofferdams 20 comprise a first cofferdam 201 and a second cofferdam 202, and the first cofferdam 201 is arranged around the display area 1; second cofferdam 202 is disposed around first cofferdam 201; the stacked pattern of the first bank 201 and the second bank 202 includes at least one filling layer provided with one or more layers of the same layer material of the fourth planarizing layer 13, the fifth planarizing layer 14, and the pixel defining layer 15. The side of the first cofferdam 201 and the second cofferdam 202 far away from the substrate base plate 10 is provided with a packaging layer 16 and a protective layer 19 in sequence.

As shown in fig. 2 to 4, the lamination pattern of the first bank 201 and the lamination pattern of the second bank 202 may be disposed to be the same. As shown in fig. 2 to 6, each of the stacked patterns of the first bank 201 and the second bank 202 includes a first filling layer 2001, and the first filling layer 2001 and the fourth planarizing layer 13 are provided in the same layer and the same material. A second filling layer 2002 may be provided on the first filling layer 2001, and the second filling layer 2002 may be provided in the same material as the fifth planarizing layer 14. A third filling layer 2003 may be further provided on the second filling layer 2002, and the third filling layer 2003 is provided in the same material as the pixel defining layer 15.

As shown in fig. 5, the lamination pattern of the first bank 201 and the lamination pattern of the second bank 202 may be set to be different. For example: the stacked pattern of the first bank 201 includes a first filling layer 2001 and a second filling layer 2002, the first filling layer 2001 is provided in the same layer as the fourth planarizing layer 13, and the second filling layer 2002 is provided in the same layer as the fifth planarizing layer 14. The stacked layer pattern of the second bank 202 includes a first filling layer 2001, a second filling layer 2002, and a third filling layer 2003, the first filling layer 2001 is provided of the same material as the fourth planarizing layer 13, the second filling layer 2002 is provided of the same material as the fifth planarizing layer 14, and the third filling layer 2003 is provided of the same material as the pixel defining layer 15. Since the first bank 201 is smaller than the second bank 202 in the film layer pattern of the third filling layer 2003, the height of the first bank 201 relative to the substrate 10 is lower than the height of the second bank 202 relative to the substrate 10, so that the path of external moisture and oxygen entering the display area 1 is lengthened, the difficulty of entering the display area 1 is increased, and the blocking capability of the bank 20 is further improved.

In some embodiments, the width of first bank 201, the width of second bank 202, and the spacing between first bank 201 and second bank 202 may be substantially the same, for example, 30 μm each. The cross-sectional shapes of the first bank 201 and the second bank 202 may be rectangular as shown in the figure, or may be trapezoidal, and at this time, the side of at least one of the first bank 201 and the second bank 202 close to the display area 1 is an inclined surface, which is not limited herein.

As shown in fig. 6, the non-display region 2 is provided with a first lead 21, and the first lead 21 is located on the substrate base 10 side and extends to the side of the outermost bank 20 away from the display region 1.

Therefore, the non-display region 2 is further provided with a planarization layer group, which is disposed on the side of the first lead 21 away from the substrate base plate 10 and on the side of the outermost bank 20 away from the display region 1.

The non-display region 2 is further provided with a second lead 25, the second lead 25 is arranged on the side of the planarization layer group away from the substrate base plate 10, and the orthographic projection of the second lead 25 on the substrate base plate 10 is positioned in the orthographic projection of the planarization layer group on the substrate base plate 10.

The planarization layer group enables the first trace to be flat on the side away from the substrate base plate 10, the second leads 25 can be uniformly arranged on a flat surface, and when the second leads 25 are arranged on the side of the outermost cofferdam 20 away from the display area, the risk that the second leads 25 are unevenly distributed and the second leads 25 are possibly in contact with each other to cause short circuit due to uneven distribution of the second leads 25 caused by uneven side of the outermost cofferdam 20 away from the display area 1 can be eliminated.

Note that, in order to planarize the recessed region, a part or all of the planarization layer may be remained, but it is necessary to ensure that the orthographic projection of the second lead 25 on the base substrate 10 is located within the orthographic projection of the planarization layer on the base substrate 10. In general, the orthographic projection of the second lead 25 in the width direction thereof is smaller than the orthographic projection of the planarization layer group in the width direction thereof, and the orthographic projection of the second lead 25 in the length direction thereof is equal to the orthographic projection of the planarization layer group in the length direction thereof. The extra width is to ensure that the second trace is located right above the planarization layer group. Specifically, the difference between the width of the planarization layer group and the width of the second lead 25 may be 10 to 20 micrometers, that is, the width of the planarization layer group is 10 to 20 micrometers greater than the width of the second lead 25, and the widths of the two sides of the planarization layer group that are more than the width of the second lead 25 may be set to be equal to each other, so as to ensure that the second trace is located in the middle of the planarization layer group.

In one embodiment, as shown in fig. 2, when the source and drain electrodes include only the first source electrode 115, the planarization layer set may include the first planarization layer 22. The first planarizing layer 22 and the fourth planarizing layer 13 are provided in the same layer of the same material. It should be noted that the first planarizing layer 22 may also be provided with the same material as the pixel defining layer 15.

On the basis of the above embodiment, as shown in fig. 3, the planarization layer set may further include a second planarization layer 23, and the second planarization layer 23 is provided on the side of the first planarization layer 22 away from the base substrate 10. When the first planarizing layer 22 and the fourth planarizing layer 13 are provided in the same layer as the material, the second planarizing layer 23 may be provided in the same layer as the pixel defining layer 15.

As shown in fig. 4, when the source/drain further includes the second source 117, the first planarization layer 22 may be disposed in the same layer as the fourth planarization layer 13, or in the same layer as the fifth planarization layer 14. When the first planarizing layer 22 and the fourth planarizing layer 13 are disposed in the same layer as the material, the second planarizing layer 23 may be disposed in the same layer as the pixel defining layer 15. The second planarizing layer 23 may also be provided of the same material as the fifth planarizing layer 14. When the first planarizing layer 22 and the fifth planarizing layer 13 are disposed in the same layer as the material, the second planarizing layer 23 may be disposed in the same layer as the pixel defining layer 15.

As shown in fig. 5, on the basis of the above embodiment, the planarization layer set may further include a third planarization layer 24, and the third planarization layer 24 is disposed on the side of the second planarization layer 23 away from the substrate base plate 10. The first planarizing layer 22 may be disposed in the same layer as the fourth planarizing layer 13, the second planarizing layer 23 may be disposed in the same layer as the fifth planarizing layer 14, and the third planarizing layer 24 may be disposed in the same layer as the pixel defining layer 15.

It is understood that the second lead 25 may be disposed on a side of the first planarization layer 22 away from the substrate base plate 10, on a side of the second planarization layer 23 away from the substrate base plate 10, or on a side of the third planarization layer 24 away from the substrate base plate 10.

It will be appreciated that the remaining of one planarization layer is often not very effective in achieving planarization, and that the area of the planarization layer that is too thick increases the risk of display failure due to moisture ingress, and it is preferred to select two planarization layers to planarize the side of the outermost bank 20 away from the display area 1. Namely: a first planarizing layer 22 and a second planarizing layer 23 are provided on the outermost bank 20 on the side away from the display region 1, and a second lead 25 is provided on the second planarizing layer 23 on the side away from the base substrate 10.

Note that the first lead 21 includes a gate line 211. The gate line 211 and the gate electrode 113 of the thin film transistor in the array substrate are distributed in the same layer. An insulating layer is provided on a side of the gate line 211 remote from the substrate 10 to insulate the gate line 211. When the thin film transistor adopts the dual-gate structure, two gate lines 211 extending to the side of the second bank 202 away from the display region 1 are correspondingly set, and two insulating layers are arranged to cover the sides of the two gate lines 211 away from the substrate 10. In addition, the first lead 21 may further include a data line (not shown), and the data line is distributed in the same layer as the first source 115 or the second source 117 and the drain 116 of the thin film transistor in the array substrate. Further, a power supply line 27, for example, a positive connection line and a ground connection line, is provided on the side of the insulating layer remote from the base board 10. The planarization layer group may be provided on the side of the power supply line 27 away from the substrate base plate 10.

When the thin film transistor includes only the first source electrode 115 and the display region includes only the fourth planarizing layer 13, the first planarizing layer 22 of the same material as the fourth planarizing layer 13 may be provided to planarize the side of the second bank 202 away from the display region 1. Of course, a third planarization layer 24 of the same material as the pixel defining layer 15 may be disposed on the first planarization layer 22 away from the substrate base plate 10, so as to further planarize the second bank 202 away from the display region 1.

When the thin film transistor includes the first source electrode 115 and the second source electrode 117, the display region includes the fourth planarizing layer 13 and the fifth planarizing layer 14, and the first planarizing layer 22 of the same material as the fourth planarizing layer 13 and the second planarizing layer 23 of the same material as the fifth planarizing layer 14 may be sequentially provided to planarize the side of the second bank 202 away from the display region 1. Of course, a third planarization layer 24 of the same material as the pixel defining layer 15 may be disposed on the side of the fifth planarization layer 14 away from the substrate base plate 10, so as to further planarize the side of the second bank 202 away from the display region 1.

The second lead 25 may be a touch lead. The touch signal lines are respectively and correspondingly electrically connected with the touch driving metal grid and the touch sensing metal grid. It can be seen that the touch lead is provided with the double-layer trace, and the double-layer trace can load the touch control signal to the touch control layer 18 through the other layer of trace after one layer of trace is partially broken, so that the problem that the touch control failure is easily caused by the breakage of the single-layer trace is effectively solved; in addition, compared with the design of single-layer wiring, the resistance value of the touch lead can be reduced by the double-layer wiring. The touch control leads may be disposed on the same layer as the touch control layer 18, specifically, one touch control lead may be disposed on the same layer as the first touch control layer 181, and the other touch control lead may be disposed on the same layer as the second touch control layer 182.

The height difference to the first wiring is generally 0.5 to 1 μm, and therefore the thickness of the first planarizing layer 22, the second planarizing layer 23, and the third planarizing layer 24 is generally at least greater than 1 μm, and the single layer thickness of the general planarizing layer group is set to 1 to 2 μm.

In one embodiment, a gap is provided between the planarization layer group and the outermost bank 20, and the gap is used to prevent water and oxygen from invading the display region 1. For example: may be located between the orthographic projection of the outermost dam 20 on the substrate base plate 10 and the orthographic projection of the second trace on the substrate base plate 10. The width H of the gap is 20 μm or more.

It is to be noted that the two second leads 25 are provided, the non-display region 2 may have the encapsulation layer 16 disposed between the pixel defining layer 15 and one of the second leads 25 disposed near one side of the substrate 10, the third insulating layer 26 disposed at the other side of the one of the second leads 25 disposed near one side of the substrate 10, and the non-display region 2 may have the protection layer 19 disposed at one side of the other of the second leads 25 away from the substrate 10, and the two second leads 25, that is, the touch leads, are respectively insulated by the third insulating layer 26 and the protection layer 19.

In addition, the non-display region 2 also includes a buffer layer 17. It should be understood that other essential components of the display substrate are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

The disclosed embodiments provide a display device. The display device may comprise a display panel as described in any of the above.

It should be noted that the display device includes other necessary components and components besides the display panel, taking the display as an example, specifically, such as a housing, a circuit board, a power line, and the like, and those skilled in the art can supplement the display device accordingly according to the specific use requirements of the display device, and details are not described herein.

The display device may be a conventional electronic device, for example: cell phones, computers, televisions, video recorders and video players, as well as emerging wearable devices such as VR glasses, not to mention here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (15)

1. A display panel is provided with a display area and a non-display area connected with the display area, wherein a plurality of cofferdams which are sequentially far away from the display area are arranged in the non-display area, and the display panel is characterized by comprising:

a substrate base plate;

the first lead is arranged on one side of the substrate base plate and extends to one side, far away from the display area, of the cofferdam on the outermost side;

the planarization layer group is arranged on one side, away from the substrate base plate, of the first lead and is positioned on one side, away from the display area, of the cofferdam on the outermost side;

and the second lead is arranged on one side of the planarization layer group, which is far away from the substrate base plate, and the orthographic projection of at least part of the second lead on the substrate base plate is overlapped with the orthographic projection of the first lead on the substrate base plate and is positioned in the orthographic projection of the planarization layer group on the substrate base plate.

2. The display panel according to claim 1, wherein a gap is provided between the planarization layer group and the outermost bank.

3. The display panel according to claim 2, wherein the width of the gap is 20 μm or more.

4. The display panel according to claim 1, wherein the second lead line includes a first portion extending perpendicular to an extending direction of the bank and a second portion extending parallel to the extending direction of the bank; the orthographic projection of the first part on the substrate base plate is overlapped with the orthographic projection of the cofferdam on the substrate base plate, and the orthographic projection of the second part on the substrate base plate is positioned in the orthographic projection of the planarization layer group on the substrate base plate.

5. The display panel according to claim 4, wherein a distance between an outermost edge of the second portion away from the display area and an outermost edge of the planarization layer group away from the display area is 10-20 um.

6. The display panel according to claim 1, wherein the display panel comprises, in the display region:

the array of the thin film transistors is arranged on one side of the substrate base plate, and the thin film transistors comprise first source electrodes;

and the fourth planarization layer is arranged on one side of the first source electrode, which is far away from the substrate base plate.

7. The display panel of claim 6, wherein the set of planarization layers comprises a first planarization layer disposed in the same material as the fourth planarization layer.

8. The display panel according to claim 7, wherein the display panel further comprises, in the display region:

the second source electrode is arranged on one side, far away from the substrate base plate, of the fourth planarization layer;

and the fifth planarization layer is arranged on one side of the second source electrode, which is far away from the substrate base plate.

9. The display panel of claim 8, wherein the planarization layer group further comprises:

and the second planarization layer is arranged on one side of the first planarization layer, which is far away from the substrate base plate, and the second planarization layer and the fifth planarization layer are arranged on the same layer and made of the same material.

10. The display panel according to claim 9, wherein the display panel further comprises, in the display region:

and the pixel defining layer is arranged on one side of the fifth planarization layer far away from the substrate base plate.

11. The display panel of claim 10, wherein the planarization layer group further comprises:

and the third planarization layer is arranged on one side of the second planarization layer or the first planarization layer, which is far away from the substrate base plate, and the third planarization layer and the pixel defining layer are arranged in the same layer and made of the same material.

12. The display panel according to claim 1, characterized in that the display panel further comprises:

a light emitting device;

the packaging layer covers the cofferdam;

and the touch layer is arranged on the packaging layer and comprises a touch electrode and a touch lead connected with the touch electrode.

13. The display panel according to claim 1, wherein the first lead comprises one or both of a gate driving line and a data line.

14. The display panel according to claim 1, wherein the second lead comprises at least one of a plurality of touch leads, a plurality of shield lines, and a plurality of ground lines.

15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.

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