CN215495608U

CN215495608U - FPGA-based teaching instrument for analyzing digital signal transmission performance

Info

Publication number: CN215495608U
Application number: CN202121706329.1U
Authority: CN
Inventors: 黄武云; 林燕鹏; 刘伟潮
Original assignee: Huang Wuyun
Current assignee: Huang Wuyun
Priority date: 2021-07-26
Filing date: 2021-07-26
Publication date: 2022-01-11
Anticipated expiration: 2031-07-26

Abstract

The utility model discloses a teaching instrument based on FPGA digital signal transmission performance analysis, which comprises a power supply module, a signal generation module, a channel module, a digital signal analysis module and an oscilloscope, wherein the signal generation module comprises a noise generator and a digital signal generator; the noise generator is input into the adder after passing through the amplitude regulator, the digital signal generator is input into the adder after sequentially passing through the three filters and the gain regulator, the output of the adder enters the FPGA analyzer after passing through the shaping filter, the synchronous signal end of the oscilloscope is connected with the signal generation module or the digital signal analysis module, and the test channel signal end of the oscilloscope is connected with the output end of the adder or the shaping filter. The utility model is used for teaching experiments, has strong signal anti-interference performance and high accuracy, and has simple and stable system structure.

Description

FPGA-based teaching instrument for analyzing digital signal transmission performance

Technical Field

The utility model belongs to the technical field of digital signal transmission performance analysis and education instruments, and particularly relates to a teaching instrument based on FPGA digital signal transmission performance analysis.

Background

The circuit structure adopted by a common simple digital signal transmission performance analyzer is generally the same as that disclosed in chinese patent CN202872801U, a DDS signal generating module and a single chip microcomputer are adopted to control and generate signals, the phase of pseudo-random signals is not accurate enough, the signal noise before data analysis is large, the anti-interference performance of the signals is poor, the accuracy of digital transmission performance detection is affected, and the system structure is complex. However, the chinese patent CN204103930U adopts the FPGA to complete digital signal generation, pseudo-random signal generation, and digital signal analysis, but the voltage range of the channel of the system channel is small, the signal gain is not adjustable, and it is not suitable for acquiring more data and performing comparison experiments in teaching experiments.

Disclosure of Invention

In view of the defects of the prior art, the utility model aims to provide a teaching instrument based on FPGA digital signal transmission performance analysis, which simplifies the system structure and is more suitable for teaching experiment.

In order to solve the technical problems, the technical scheme adopted by the utility model is as follows:

the utility model relates to a teaching instrument based on FPGA digital signal transmission performance analysis, which comprises a power supply module, a signal generation module, a channel module, a digital signal analysis module and an oscilloscope, wherein the signal generation module comprises a noise generator and a digital signal generator; the noise generator is input into the adder after passing through the amplitude regulator, the digital signal generator is input into the adder after sequentially passing through the three filters and the gain regulator, the output of the adder enters the FPGA analyzer after passing through the shaping filter, the synchronous signal end of the oscilloscope is connected with the signal generating module or the digital signal analyzing module, and the test channel signal end of the oscilloscope is connected with the output end of the adder or the shaping filter.

The power module of the utility model is respectively connected with the signal generation module, the channel module and the digital signal analysis module.

The power module of the utility model provides direct current + -15V and direct current 5V output.

The signal generating module and the digital signal analyzing module are both composed of a single FPGA chip.

The utility model has the beneficial effects that:

1. the signal generation module and the digital signal analysis module are both completed by a single FPGA chip, so that the system structure is greatly simplified; 2. a gain regulator is introduced, so that the gain of a signal channel can be changed between 0.2 and 4 times, different attenuation conditions and interference conditions of signals in the channel transmission process are simulated, and the method is more suitable for data acquisition in teaching experiments and is needed for comparison experiments;

3. the operational amplifier chips used in the channel all adopt ultra-low voltage noise and high-speed voltage feedback operational amplifier, so that the system noise can be greatly reduced, the anti-interference capability of the system can be improved, the accuracy of experimental data can be ensured, all the operational amplifiers adopt +/-15V power supply, and the voltage range of a digital signal transmission channel is wider;

4. the signal source of the oscilloscope detection channel can be switched between the interference signal and the signal after shaping and filtering through the change-over switch, so that different eye diagrams can be obtained, and bright contrast can be formed, and the oscilloscope detection channel is more suitable for teaching experiment requirements.

Description of the drawings:

FIG. 1 is a basic block diagram of a system related to the present invention;

FIG. 2 is a circuit diagram of a power module according to the present invention;

FIG. 3 is a circuit diagram of the signal generation module FPGA according to the present invention;

FIG. 4 is a circuit diagram of a frequency adjustment key according to the present invention;

FIG. 5 is a circuit diagram of the key reading FPGA of the present invention;

FIG. 6 is a circuit diagram of a channel block filter according to the present invention;

FIG. 7 is a circuit diagram of a channel block gain adjuster according to the present invention;

FIG. 8 is a circuit diagram of a channel block summer in accordance with the present invention;

fig. 9 is a circuit diagram relating to a shaping circuit of a signal analyzing module in the present invention;

the specific implementation mode is as follows:

the utility model will be further described with reference to the accompanying drawings.

Referring to fig. 1, the utility model relates to a teaching instrument based on FPGA digital signal transmission performance analysis, which comprises a power module, a signal generation module, a channel module, a digital signal analysis module and an oscilloscope, wherein the power module is respectively connected with the signal generation module, the channel module and the digital signal analysis module, the signal generation module comprises a noise generator and a digital signal generator, the channel module comprises an amplitude regulator, three filters, a gain regulator and an adder, and the digital signal analysis module comprises a shaping filter and an FPGA analyzer; the noise generator is input into the adder after passing through the amplitude regulator, the digital signal generator is input into the adder after sequentially passing through the three filters and the gain regulator, the output of the adder enters the FPGA analyzer after passing through the shaping filter, the synchronous signal end of the oscilloscope is connected with the signal generating module or the digital signal analyzing module, and the test channel signal end of the oscilloscope is connected with the output end of the adder or the shaping filter.

Specifically, the system signal generation module generates two paths of signals by an FPGA, wherein one path of signals is an M sequence with adjustable baud rate of 10K-100K, can output a synchronous pulse and a Manchester code of the M sequence, and simultaneously generates a pseudo-random code with the baud rate of 10M as a noise interference signal; then inputting the two paths of signals into a digital channel composed of an active low-pass filter, a gain regulator and the like, and superposing the digital signal and an interference signal which is simulated by a pseudo-random code and attenuated by the gain regulating circuit at an output port of the channel by using an adder to generate an interfered digital signal; then, the output signal of the channel is input into a shaping filter of a digital signal analysis module for shaping, finally, an FPGA is adopted to manufacture a self-adaptive PLL to display the synchronous pulse of the digital signal, and the eye pattern of the digital signal is completely displayed on an oscilloscope by utilizing the synchronous pulse.

The power supply module provides direct current +/-15V and direct current 5V output, and comprises two parts, as shown in fig. 2, the first part is direct current +/-15V and provides working voltage for an operational amplifier circuit in the system, and the second part is direct current 5V and provides working voltage for an FPGA small system board in the system. The two parts all adopt direct current linear power supplies, the power supply generally comprises 4 links, namely transformation, rectification, filtering and voltage stabilization, wherein the voltage stabilization chip respectively adopts LM7815, LM7915 and LM7805 series chips.

The signal generation module and the digital signal analysis module are both composed of a single FPGA chip, the signal generation module is completed by the single FPGA chip, an external circuit realizes the input of addition and subtraction signals through buttons shown in fig. 4, key values are read by an FPGA internal key reading circuit shown in fig. 5, key information is converted into 32-bit control words and is transmitted to a signal generation circuit shown in fig. 3, and the signal generation circuit generates an m-sequence signal with fixed frequency of 10MHz, an m-sequence signal with adjustable frequency of 10K-100K and corresponding Manchester codes. And inputting the m-sequence signal of 10MHz as a noise signal into a channel, and inputting the m-sequence of 10K-100K and the corresponding Manchester code into the channel as digital signals.

The channel module filter is composed of a three-way Sallen-key type, 4-order butterworth low-pass filter, a circuit of the channel module filter is shown in fig. 6, and specific parameters of the circuit are as follows: the parameters of the low-pass filter with the cut-off frequency of 100KHz are as follows: r1=16K, R2=8.2K, R3=8.2K, C1=100pF, C2=400pF, C3=100 pF; the parameters of the low-pass filter with the cut-off frequency of 200KHz are as follows: r1=8.2K, R2=3.9K, R3=3.9K, C1=100pF, C2=400pF, C3=100 pF; the parameters of the low-pass filter with the cut-off frequency of 500KHz are as follows: r1=3K, R2=1.6K, R3=1.6K, C1=100pF, C2=400pF, C3=100 pF; the channel block gain adjuster circuit is shown in fig. 7, where RP1=25K, R1=1K, R2=4K, R3=1K, according to the formula of resistive voltage division: u shape_P/U_in= R3/R2+ R3, can get the forward input voltage Up 0.2 times the input voltage, adjust RP1 can adjust the inverse proportional operator amplification factor to 1, then the output voltage is 0.2 times the input voltage, if adjust RP1 to make its resistance value 19K, then the inverse proportional operator amplification factor will be20 times, then the output voltage is 4 times the input voltage. I.e., adjusting the tissue of RP1, can cause the output voltage to vary from 0.2 to 4 times.

The adder circuit in the channel module is shown in fig. 8, and needs to add square wave noise of 10M and low frequency signal with the highest frequency of 100K. Considering that if the resistance-capacitance coupling is adopted, certain attenuation is caused, if restoration is needed, amplification is also needed, and therefore a direct coupling addition circuit is adopted. Because the signal contains 10M high-frequency signal, and the higher harmonic component is considered, in order to ensure the synthesis quality, an amplifier with higher gain bandwidth product is needed, wherein THS3091 of TI company is used as the amplifier, the power supply voltage is 36V, the 5-fold gain bandwidth product is nearly 100M, the slew rate is 7300V/us, and the superposition of the signal can be well completed.

The digital signal analysis module is composed of an FPGA analyzer and a shaping filter, because a signal sent by a signal generator can generate certain deformation after being processed by links in a channel, if the signal is directly sent to the signal analysis and processing, the signal is not beneficial to the processing of the FPGA on the signal, the digital signal needs to be shaped and filtered to a certain extent before a signal processor, the structure of a filter circuit is the same as that of the filter circuit shown in the figure 6, but the shape of a waveform needs to be shaped by the shaping circuit, the leading edge gradient of the signal is steeper, and the amplitude of the signal is limited. The circuit is shown in fig. 9, and the principle of the circuit is that an LM311 is used to form a comparator circuit, a digital signal enters from the reverse comparison end of the LM311, and is compared with the potential of the forward comparison end, and a shaped square wave is output from the output pin of the LM 311. The duty ratio of the output wave can be adjusted by adjusting the potentiometer RP3 in the circuit, and the amplitude of the output square wave can be adjusted by adjusting the potentiometer RP 1. Meanwhile, the circuit is an inverse comparator, the phase difference between the output square wave signal and the original signal is 180 degrees, so that the same inverse comparator is added at the back, the phase is inverted, and the output signal is in phase with the original signal.

The FPGA analyzer is characterized in that according to the principle characteristic of the Manchester code, each transmission of a data pulse of the Manchester code can always generate one inversion, by utilizing the characteristic of the Manchester code, the time of two inversions before and after can be captured and collected for multiple times, and the time with the shortest period among the times before and after is taken as the inversion time of a synchronous pulse, so that a pulse with the same period as the synchronous pulse can be obtained, but the phases of the pulses are possibly different, therefore, a phase-locked loop is added in a module, the phase of a pulse signal generated in the front is the same as that of a signal of a received code source, and the synchronous pulse which can be used for decoding is obtained.

The oscilloscope synchronizing signal can select the synchronizing signal generated by the signal generating module or the synchronizing signal generated by the digital signal analyzing module through the change-over switch; through the change-over switch, the test channel signal can select the interference signal output by the adder and also can select the signal after shaping and filtering.

It is to be understood that the technical scope of the present invention is not limited to the content of the specification, and that modifications or changes may be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims.

Claims

1. The utility model provides a teaching instrument based on FPGA digital signal transmission performance analysis which characterized in that: the device comprises a power supply module, a signal generation module, a channel module, a digital signal analysis module and an oscilloscope, wherein the signal generation module comprises a noise generator and a digital signal generator, the channel module comprises an amplitude regulator, three filters, a gain regulator and an adder, and the digital signal analysis module comprises a shaping filter and an FPGA analyzer; the noise generator is input into the adder after passing through the amplitude regulator, the digital signal generator is input into the adder after sequentially passing through the three filters and the gain regulator, the output of the adder enters the FPGA analyzer after passing through the shaping filter, the synchronous signal end of the oscilloscope is connected with the signal generating module or the digital signal analyzing module, and the test channel signal end of the oscilloscope is connected with the output end of the adder or the shaping filter.

2. The teaching instrument based on FPGA digital signal transmission performance analysis of claim 1, characterized in that: and the power supply module is respectively connected with the signal generation module, the channel module and the digital signal analysis module.

3. The teaching instrument based on FPGA digital signal transmission performance analysis of claim 1 or 2, characterized in that: the power supply module provides direct current +/-15V and direct current 5V output.

4. The teaching instrument based on FPGA digital signal transmission performance analysis of claim 1, characterized in that: the signal generation module and the digital signal analysis module are both composed of a single FPGA chip.