CN215494431U - Array substrate, display panel and display device - Google Patents

Abstract

The utility model discloses an array substrate, a display panel and display equipment, wherein the array substrate comprises: the array grid drives the GOA module and a plurality of clock signal lines. Each clock signal line is connected with the GOA module through a wire and used for providing clock signals for the GOA module; at least one wire is provided with a compensation section for compensating the load difference of different clock signal wires. Therefore, the load difference among different clock signal lines of the GOA module can be effectively reduced, and the display defects such as horizontal stripes caused by the driving difference in the panel can be improved.

Description

Array substrate, display panel and display device

Technical Field

The utility model relates to the technical field of display, in particular to an array substrate, a display panel and display equipment.

Background

With the development of electronic technology, displays are widely used in various industries and scenes, and the requirements for displays are higher and higher. The Gate On Array (GOA) technology is a technology for integrating a Gate Integrated Circuit (Integrated Circuit) of a liquid crystal display On an Array substrate. The GOA products are the mainstream trend of panel factories, and most of the products in the market are switched to the GOA products. However, the GOA products still have problems of poor display such as horizontal streaks, and the targeted improvement of the poor display is an important approach to improve the product quality.

SUMMERY OF THE UTILITY MODEL

In view of the foregoing problems, embodiments of the present disclosure provide an array substrate, a display panel, and a display device, which can effectively reduce a load difference between different clock signal lines of a GOA module, thereby being beneficial to improving poor display such as horizontal stripes caused by a driving difference inside the panel.

In a first aspect, an embodiment of the present specification provides an array substrate, including:

the array grid electrode drives the GOA module;

each clock signal line is connected with the GOA module through a routing line and used for providing clock signals for the GOA module;

at least one of the wires is provided with a compensation section, and the compensation section is used for compensating the load difference of different clock signal lines.

Furthermore, the compensation section is used for compensating the routing length, and the distance between the clock signal line and the GOA module is inversely related to the length of the compensation section, so as to reduce the routing resistance difference of different clock signal lines.

Furthermore, the routing lengths between the clock signal lines and the GOA modules are equal.

Further, the compensation section is used for compensating the overlapping area of a trace and a color film substrate, and the overlapping areas of the trace and the color film substrate of different clock signal lines are equal, so as to reduce the difference between the trace coupling capacitances of different clock signal lines.

Further, the compensation section is a zigzag-shaped winding.

Further, the plurality of clock signal lines are disposed on a signal layer in the array substrate, the traces are disposed on a trace layer in the array substrate, the compensation segments are disposed in a non-overlapping area in the trace layer, and the non-overlapping area is an area where there is no overlap with the signal lines in the signal layer.

Furthermore, the plurality of clock signal lines are disposed on a signal layer of the array substrate, the trace is disposed on a trace layer of the array substrate, and a gap is disposed in an overlapping region of at least one target signal line in the signal layer, where the overlapping region is an overlapping region of the target signal line and the trace.

Further, the same type of signal lines of the signal layer are equally spaced apart and provided with the slits having the same shape and size.

In a third aspect, embodiments of the present specification provide a display panel, including the array substrate according to the second aspect.

In a fourth aspect, embodiments of the present specification provide a display device including the display panel of the third aspect.

The technical scheme provided in the embodiment of the specification at least has the following technical effects or advantages:

the array substrate, the display panel and the display device provided by the embodiments of the present specification, the compensation section is disposed through at least one routing line between the GOA module and the corresponding clock signal line, so as to compensate for load differences between different clock signal lines, effectively reduce load differences between different clock signal lines of the GOA module, and enhance uniformity of driving in an opposite direction by the GOA module, thereby being beneficial to improving poor display such as horizontal stripes caused by driving differences in the panel.

The above description is only an outline of the technical solution of the present specification, and the embodiments of the present specification are described below in order to make the technical means of the present specification more clearly understood, and the present specification and other objects, features, and advantages of the present specification can be more clearly understood.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the specification. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a schematic structural diagram of an array substrate;

fig. 2 is a schematic structural diagram of an exemplary array substrate in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an exemplary signal layer in an embodiment of the present disclosure;

FIG. 4 is a schematic view of an exemplary overlap area in an embodiment of the present disclosure;

FIG. 5 is a schematic view of an exemplary gap distribution in an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a display device in an embodiment of this specification.

Detailed Description

As shown in fig. 1, in the liquid crystal display panel using the GOA technology, the array substrate 10 includes: a display area 100 and a driving circuit area. The driving circuit region includes: the array gate drives the GOA module 101 and a plurality of clock signal lines 102 for providing clock signals to the GOA module 101, where the plurality of clock signal lines 102 are connected to the GOA module 101 through routing lines (e.g., L1, L2, L3, L4, L5, and L6 shown in fig. 1). It should be noted that, in fig. 1, 6 clock signal lines are taken as an example to show routing of 6 clock signal lines and a group of GOA cells (not shown in the figure) in the GOA module 101, and the specific number of the routing is determined according to the group number of the GOA cells in the real GOA module 101.

Specifically, the GOA module 101 is disposed at a side of a display area of the display panel, and configured to sequentially output high-level square waves to gate lines of pixels in each row within a frame time, and turn on pixel Thin Film Transistors (TFTs) corresponding to the gate lines row by row, so that the data lines perform one charge refresh on all sub-pixels in the pixel area. The GOA module 101 includes a plurality of cascaded GOA units, where each level of GOA unit correspondingly drives one row of horizontal scan lines. Each GOA unit has a clock signal input end and a signal output end, the signal output end outputs signals under the drive of input signals, and signals output by the signal output end are simultaneously used as gate drive signals of the same row and input signals of a next-stage GOA unit.

The inventors have conducted long-term studies to solve the problem of defective display, and found that carelessness in design details of the GOA section at the beginning of panel design is liable to cause defects in the following products. One of the details to be noted is that in order to minimize the trace load, the traces are laid according to the shortest path, and as shown in fig. 1, the traces extend in a direction perpendicular to the clock signal line 102. Since the distances between the different clock signal lines 102 and the GOA modules 101 are different, the lengths of the corresponding traces are different, the closer the clock signal line 102 is to the GOA module 101, the shorter the trace length between the clock signal line 102 and the GOA module 101 is, and the farther the clock signal line 102 is from the GOA module 101, the longer the trace length between the clock signal line 102 and the GOA module 101 is. That is, there is a difference in the trace length from the clock signal line (CLK) to the GOA module 101, as shown in fig. 1: l1 > L2 > L3 > L4 > L5 > L6, and this difference results in at least the following two load differences of CLK:

(1) the resistance difference of the routing, namely the longest routing length and the largest resistance of the CLK which is farthest away from the GOA module and is connected to the GOA module;

(2) the capacitance difference, namely the overlapping area between the trace length corresponding to the CLK on the outermost side and the color film substrate (CF) side is large, and the coupling capacitance generated therewith is also larger.

The difference between the two aspects can affect the rising and falling edges of the input waveform of the GOA module 101, so that the rising and falling edges of the output signals of different GOA units in the GOA module 101 have different delays, which causes different delays in the turn-on and turn-off times of the gate lines of corresponding pixel rows, and thus causes the charging of the pixel rows to have different differences, i.e., the brightness to have different differences, and finally causes the display to have defects such as horizontal stripes.

In view of the above, to solve or partially solve the above problems, embodiments of the present disclosure provide an array substrate, a display panel and a display device. Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Fig. 2 is a structural diagram of an array substrate 20 in an embodiment of the present disclosure. As shown in fig. 2, the array substrate 20 includes: the array gate drives the GOA module 201 and a plurality of clock signal lines (e.g., CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6 shown in fig. 2). It should be noted that, in order to further highlight the technical solutions provided by the embodiments of the present disclosure, other components, such as display area components, in the array substrate 20 except the GOA modules 201 and the clock signal lines are not shown in fig. 2, and only the GOA modules 201 and the corresponding clock signal lines on one side of the display panel are shown.

Specifically, the number of clock signal lines is even, and the number of clock signal lines can be set according to the needs of the actual application scenario, for example, 2, 4, 6, or 8, etc. (6 CLK, i.e., 6 clock signal lines are shown in fig. 2 as an example, and the line widths of the clock signal lines and the corresponding routing lines are ignored). Each clock signal line is connected to the GOA module 201 through a trace, and is configured to provide a clock signal for the GOA module 201.

At least one wire is provided with a compensation section, and the compensation section is used for compensating the load difference of different clock signal lines. Therefore, the load difference between different clock signal lines of the GOA module 201 can be effectively reduced, the uniformity of the opposite internal driving of the GOA module 201 is enhanced, and the display defects such as transverse striations caused by the driving difference in the display panel are favorably improved.

In an alternative embodiment, the compensation segment may be disposed in the path direction of the traces, and is used for compensating the trace length to reduce the difference in resistance of the traces of different clock signal lines. Specifically, the length of the compensation section is determined based on the distance between the clock signal line and the GOA module 201, which is inversely related to the length of the compensation section. That is, when the compensation segment is provided on the route of two or more different clock signal lines, the length of the compensation segment decreases sequentially from the clock signal line closest to the GOA module 201 to the clock signal line farthest therefrom. For design convenience, the line width of the compensation section can be set to be the same as the line width of other sections in the routing.

For example, the compensation section compensates the trace length, so that the trace lengths between different clock signal lines and the GOA module 201 can be equal. It should be noted that "equal" here is equal in a broad sense, that is, the maximum difference value between the routing lengths of the different clock signal lines and the GOA module 201 is within an acceptable error range, and at this time, it can be considered that the routing lengths between the different clock signal lines and the GOA module 201 are equal, and the routing resistance difference between the different clock signal lines is close to zero, so that the routing resistance difference between the different clock signal lines is eliminated.

In an alternative embodiment, the remaining track segments of the track provided with the compensation segments are called as reference segments. That is to say, the above-mentioned wiring provided with the compensation section may include a reference section and a compensation section, one end of the reference section is connected with one end of the compensation section, and the corresponding clock signal line is connected with the GOA module 201 through the reference section wiring and the compensation section wiring. The extending direction of the compensation segment trace is different from the extending direction of the reference segment trace, for example, the reference segment may extend along the shortest path of the trace, for example, the reference segment may extend along a direction perpendicular to the clock signal line, and the compensation segment is a trace arranged relative to the extending direction of the reference segment, so as to increase the length of the whole trace, so that the trace lengths of the clock signal lines are equivalent, thereby reducing the resistance difference of the traces.

For example, the length of the trace between the outermost clock signal line and the GOA module 201 may be used as a reference length, and a compensation segment (e.g., Lc2, Lc3, Lc4, Lc5, and Lc6 in fig. 2) may be disposed on the trace between each clock signal line other than the outermost clock signal line and the GOA module 201. For example, as shown in fig. 2, taking 6CLK as an example, the distance from CLK1 to CLK6 to the GOA module 201 is smaller. For example, traces between CLK1 and GOA module 201 may be routed in a direction perpendicular to CLK1 to minimize the trace length and thereby reduce the load of CLK1, while traces between CLK 2-CLK 6 and GOA module 201 each include a reference segment and a compensation segment, and the reference segment may be routed in a direction perpendicular to CLK 2-CLK 6. The compensation segment and the reference segment are connected to form a complete trace, the compensation segment may be disposed at a position between the GOA module 201 and the corresponding clock signal line, for example, Lc2 may be disposed between CLK2 and CLK3, Lc3 may be disposed between CLK3 and CLK4, Lc4 may be disposed between CLK4 and CLK5, Lc5 may be disposed between CLK5 and CLK6, and Lc6 may be disposed between CLK6 and the GOA module 201 or between CLK6 and other signal lines, and the specific position may be set according to actual needs, which is not limited herein.

Or, a reference length may be additionally set according to actual needs, and a compensation section is set on the trace between each clock signal line and the GOA module 201, so that the trace between each clock signal line and the GOA module 201 reaches the reference length.

In addition, the compensation section is used for compensating the overlapping area of the trace and a Color Filter (CF) substrate besides the trace length, namely the trace resistance, so as to reduce the difference between the trace of different clock signal lines and the CF side coupling capacitance. It can be understood that, under the condition that the trace line widths of the clock signal lines are the same, the trace lengths of the clock signal lines are equal, and the corresponding trace surface areas are also equal, that is, the corresponding trace surface areas are equivalent to the overlapping areas on the CF side. Therefore, for clock signal wires with relatively short original wire length, after the compensation sections are arranged in the wires, on one hand, the wire length is increased, namely, the wire resistance difference with other clock signal wires is compensated, on the other hand, the overlapping area with the CF side is also increased, so that the difference of the overlapping areas of the wires of different clock signal wires and the GOA module and the CF side is within an acceptable error range, the overlapping areas of the wires of different clock signal wires and the CF side can be considered to be equal, and the coupling capacitance difference between the wires of different lengths and the CF side can be compensated.

For example, the compensation segments can be any shape of wire wrap that can be routed when routing the traces. It should be noted that the routing is relative to the shortest routing path, that is, the routing does not extend along the shortest routing path of the corresponding clock signal line and the GOA module 201, but represents a segment in a routing state, as shown in fig. 2. For example, the compensation segments may be zigzag windings or windings with other shapes, such as irregular bending lines, and the winding shape shown in fig. 2 is only for illustration and not for limitation, and the compensation of the difference of the trace length and the difference of the overlapped area with the CF side can be realized. In addition, the compensation section may be a winding, or may include multiple windings, and when the compensation section includes multiple windings, the multiple windings may be disposed at equal intervals or unequal intervals, which is not limited in this embodiment.

It should be noted that, the positions and shapes of the routing path and the compensation segment included between the clock signal line and the GOA module 201 can be set according to actual requirements. After the routing path and the position, length and shape of the corresponding compensation section are designed as required, the processing of each routing can be completed through the processes of etching and the like.

Of course, in other embodiments of the present disclosure, in addition to the compensation segments disposed in the trace path direction to reduce the load difference of different clock signal lines, the compensation segments may also be disposed in other manners, for example, the compensation segments may also be disposed in the width direction of the trace, for example, a bump wiring may be disposed as the compensation segments to compensate the trace length difference and/or the overlap area difference between the trace and the CF side.

In a specific implementation, in order to facilitate the wiring, the plurality of clock signal lines and the traces are disposed in different layers of the array substrate. For example, the plurality of clock signal lines may be disposed on a signal layer in the array substrate, and the routing between the clock signal lines and the GOA modules 201 is disposed on a routing layer in the array substrate. Of course, as shown in fig. 3, the signal layer 300 may be wired with other signal lines 302 such as a power supply signal line and other control signal lines, etc., in addition to the clock signal line 301. Coupling capacitance is generated due to the fact that transverse routing lines in the routing layer are overlapped with longitudinal signal lines in the array substrate.

Therefore, in an alternative embodiment, in order to avoid as much as possible that the disposed compensation segments increase the overlapping area with each signal line in the signal layer while compensating the difference in the trace length, thereby increasing the coupling capacitance with the signal layer and affecting the driving capability of the GOA module 201, as shown in fig. 3, the compensation segments may be disposed in the non-overlapping area in the trace layer. The non-overlapping region is a region where there is no overlap with the signal lines (including the clock signal line 301 and the other signal lines 302) in the signal layer 300. Thus, the signal lines in the signal layer 300 can be avoided, and the increase of coupling capacitance caused by the overlapping of the signal lines can be avoided.

It should be noted that the layout position of the compensation segment of each trace in the non-overlapping area may be determined according to actual needs, which is not limited in this embodiment. For example, in the example shown in fig. 2, in addition to the arrangement of Lc2 to Lc5 at the arrangement positions shown in fig. 2, Lc2 to Lc5 may also be arranged at a non-overlapping region between CLK6 and the GOA module or CLK6 and other signal lines.

Further, the inventor has found in research that the load of the clock signal line affects on one hand the turn-on effect of the TFT and on the other hand the delay of the falling edge of the driving signal, and the larger the delay, the worse the charging effect. That is, the load of the clock signal line affects the driving capability of the GOA module 201, and the charging rate of the in-plane pixels is affected, which may cause a defect such as a display afterimage.

Therefore, in order to reduce the load of the clock signal lines, in the array substrate provided in this embodiment of the present disclosure, a slit (slit) may be further formed at an overlapping portion between the signal line in the signal layer and the trace, for example, a slit may be formed in a region of the corresponding signal line that passes through (Cross) the trace, and/or a slit may be formed in a region of the corresponding trace that intersects with the signal line. Therefore, the overlapping area of the wiring and the signal line in the signal layer can be reduced, so that the coupling capacitance generated at the overlapping position is reduced, the load of the clock signal line is reduced, the driving capability of the GOA module 201 is enhanced, the pixel charging rate is improved, and the display residual image and other defects are improved.

In specific implementation, considering that the line width of the signal line is relatively large, and the gap is more conveniently processed, as an implementation manner, in the signal layer of the array substrate, a gap is formed in an overlapping region of at least one target signal line. The target signal line is a signal line overlapped with the routing line, and the overlapping area is the overlapping area of the target signal line and the routing line. The opened gap covers a part of the overlapping area to eliminate the coupling capacitance formed at the part of the overlapping area, so that the load of the corresponding clock signal line can be effectively reduced. In specific implementation, in order to reduce the load of the clock signal lines as much as possible and enhance the driving capability of the GOA module 201, the above-mentioned gap may be formed in the overlapping region of each target signal line. Of course, according to actual needs, a gap may be selectively opened on some target signal lines in the signal layer, for example, the clock signal line overlapped with the trace line, which is not limited in this embodiment.

It should be noted that the shape of the slit may be set according to actual needs and process difficulty, for example, the shape of the slit may be set to be rectangular, circular, or elliptical, and the present embodiment does not limit this. The size of the gap can be determined according to the distribution of actual wiring and the line width of the wiring, and the size of the gap is not more than the line width of the signal line, so that the disconnection of the signal line is avoided. For example, the processing of the gap may be implemented by etching the conductive material at the corresponding position on the signal line through an etching process, or other processing manners may also be adopted, which is not limited herein.

For example, taking a rectangular slit as an example, as shown in fig. 4, a signal line 400Cross in a signal layer has three traces (411, 412, and 413 shown in fig. 4), and then a slit 420 formed on the signal line 400 may penetrate through Cross regions of the three traces to reduce coupling capacitance formed by the three traces and the signal line 400.

Further, as an embodiment, the same type of signal lines of the signal layer are equally spaced and provided with gaps of the same shape and size. That is, while it is ensured that the target signal line has a gap in the overlap region, gaps of the same shape and size may be formed at equal intervals in the target signal line in a region other than the overlap region and in the same type of signal line as the target signal line in the signal layer. Therefore, gaps can be uniformly distributed on the same type of signal lines in the signal layer, processing is facilitated, the uniform distribution of the resistance per unit length on the same type of signal lines is guaranteed, and sudden change is avoided. For example, as shown in fig. 5, the slots 520 having the same shape and size may be provided at equal intervals in all the clock signal lines 500 in the signal layer.

In addition, the embodiment of the specification also provides a display panel. As shown in fig. 6, the display panel 60 includes the array substrate 20. The same structure and advantageous effects as those of the array substrate 20 provided as described above are also provided.

Since the array substrate 20 included in the display panel 60 described in the embodiments of the present disclosure is described above, based on the array substrate 20 described in the embodiments of the present disclosure, a person skilled in the art can understand the specific structure and effect principle of the display panel 60, and thus the description is omitted here. All the display panels 60 including the array substrate 20 of the embodiments of the present disclosure are within the scope of the present disclosure.

Further, embodiments of the present specification also provide a display device, as shown in fig. 7, the display device 70 includes the display panel 60 described above. The same structure and advantageous effects as those of the array substrate 20 provided as described above are also provided.

It should be noted that the display device 70 may be: any product or component with a display function, such as a mobile phone, a liquid crystal panel, electronic paper, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, and the like.

Since the array substrate 20 included in the display device 70 described in the embodiments of the present disclosure is described above, based on the array substrate 20 described in the embodiments of the present disclosure, a person skilled in the art can understand the specific structure and effect principle of the display device 70, and thus the description is omitted here. All the display devices 70 including the array substrate 20 of the embodiments of the present disclosure are within the scope of the present disclosure.

The technical scheme provided in the embodiment of the specification at least has the following technical effects or advantages:

the compensation lines are arranged through at least one routing line between the GOA module and the corresponding clock signal line and used for compensating load difference between different clock signal lines, so that the load difference between different clock signal lines of the GOA module can be effectively reduced, the uniformity of internal drive opposite to the GOA module is enhanced, and the display defects such as transverse stripes caused by the drive difference in the panel are favorably improved.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present description may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the specification, various features of the specification are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various embodiments. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the present specification as claimed requires more features than are expressly recited in each claim. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this specification.

Those skilled in the art will appreciate that the modules in the apparatus of an embodiment may be adaptively changed and disposed in one or more apparatuses other than the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the description and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the specification, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The description may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Claims (10)

1. An array substrate, comprising:

the array grid electrode drives the GOA module;

each clock signal line is connected with the GOA module through a routing line and used for providing clock signals for the GOA module;

at least one of the wires is provided with a compensation section, and the compensation section is used for compensating the load difference of different clock signal lines.

2. The array substrate of claim 1, wherein the compensation segments are used for compensating a trace length, and a distance between the clock signal line and the GOA module is inversely related to the length of the compensation segments to reduce a trace resistance difference between different clock signal lines.

3. The array substrate of claim 2, wherein the trace lengths between the clock signal lines and the GOA modules are equal.

4. The array substrate of claim 1, wherein the compensation segment is configured to compensate an overlapping area of a trace and a color filter substrate, and overlapping areas of the trace and the color filter substrate of different clock signal lines are equal to reduce a difference between trace coupling capacitances of different clock signal lines.

5. The array substrate of claim 1, wherein the compensation segments are Zig-zag shaped windings.

6. The array substrate of claim 1, wherein the plurality of clock signal lines are disposed in a signal layer in the array substrate, the traces are disposed in a trace layer in the array substrate, and the compensation segments are disposed in a non-overlapping area in the trace layer, the non-overlapping area being an area where there is no overlap with the signal lines in the signal layer.

7. The array substrate of claim 1, wherein the plurality of clock signal lines are disposed on a signal layer in the array substrate, the traces are disposed on a trace layer in the array substrate, and an overlapping area of at least one target signal line in the signal layer is provided with a gap, wherein the overlapping area is an overlapping area of the target signal line and the trace.

8. The array substrate of claim 7, wherein the same type of signal lines of the signal layer are equally spaced with the same shape and size of the slits.

9. A display panel comprising the array substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.

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