CN215493963U

CN215493963U - Chip testing board

Info

Publication number: CN215493963U
Application number: CN202121202354.6U
Authority: CN
Inventors: 刘峻峰; 顾标琴
Original assignee: Jiangsu Yangjierunao Semiconductor Co ltd
Current assignee: Jiangsu Yangjierunao Semiconductor Co ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2022-01-11
Anticipated expiration: 2031-05-31

Abstract

The utility model belongs to the technical field of semiconductor manufacturing equipment, and particularly relates to a chip test board. Be applied to on the chip testing arrangement, the chip testing arrangement includes the transmission box, offers the recess that is used for placing the chip on the transmission box, and the chip is surveyed the board and is included conductive substrate, and conductive substrate is last the array and offered the test groove that corresponds with transmission box upper groove. The utility model is used for solving the problem of low chip testing efficiency. The array sets up a plurality of test grooves that correspond with transmission box upper groove on the conducting substrate, when testing the chip, only needs to overturn the conducting substrate and aim at the transmission box, will transmit the whole upsets of box in the chip and place in the test groove, later can accomplish the test to all test grooves in the chip simultaneously, improve efficiency of software testing.

Description

Chip testing board

Technical Field

The utility model belongs to the technical field of semiconductor manufacturing equipment, and particularly relates to a chip test board.

Background

Generally, after a semiconductor chip is processed, in order to ensure the quality of the chip, the chip needs to be tested to determine whether the chip is good or bad.

At present, when testing the sintered chip, what adopted is a monoblock ordinary aluminum plate, only need take out the chip from the transparent transmission box of PVC during the test, in only putting back the PVC transmission box after surveying again, test operation step is wasted time and energy, leads to the efficiency of software testing low.

SUMMERY OF THE UTILITY MODEL

The technical problem that this application embodiment will solve lies in overcoming prior art not enough, provides a chip testing board for solve the problem that chip efficiency of software testing is low.

The technical scheme for solving the technical problems in the embodiment of the application is as follows: a chip testing board is applied to a chip testing device, the chip testing device comprises a transfer box, a groove used for placing a chip is formed in the transfer box, the chip testing board comprises a conductive substrate, and a testing groove corresponding to the groove in the transfer box is formed in the conductive substrate in an array mode.

Compared with the prior art, the technical scheme has the following beneficial effects:

the array sets up a plurality of test grooves that correspond with transmission box upper groove on the conducting substrate, when testing the chip, only needs to overturn the conducting substrate and aim at the transmission box, will transmit the whole upsets of box in the chip and place in the test groove, later can accomplish the test to all test grooves in the chip simultaneously, improve efficiency of software testing.

Further, the test groove is concentrically provided with a boss.

The periphery of the compression joint type chip is coated with glue protruding out of the table board, so that the periphery of the compression joint type chip is thicker than the middle part, the compression joint type chip cannot be in contact with the conductive substrate to be tested when being directly placed into the test slot, and the boss concentrically arranged in the test slot can avoid the contact of silica gel at the edge and the table board at the center of the chip, so that the compression joint type chip is ensured to have a good test environment; meanwhile, during the test of the crimping type chip, the concentric alignment of the chip to be tested and the molybdenum sheet for testing can be realized through the test groove, so that the problems of complexity and difficulty in alignment of molybdenum sheets placed one by one during manual testing are solved.

Further, the periphery of the top of the boss is provided with a round chamfer.

The periphery of the top of the boss is set to be a round chamfer, so that the damage of the chip caused by the scratch of the edge of the boss on the surface of the chip table is avoided.

Furthermore, the depth of the test groove is smaller than the thickness of the chip to be tested.

The depth of the test slot is set to be that after the chip to be tested is placed into the test slot, the chip can protrude out of the surface of the conductive substrate, and the test chip is prevented from being difficult to take out after being embedded into the test slot.

Specifically, the depth of the test groove is set to 3-5 mm.

Further, the boss height is set to be 2-4 mm.

And the height of the boss is limited, so that the whole chip is enabled to protrude out of the surface of the conductive substrate when the compression joint type chip is tested, and the chip is placed and embedded into the conductive substrate and is difficult to take out.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a top view of a structure according to an embodiment of the utility model.

Fig. 2 is a side view of fig. 1.

Fig. 3 is a top view of another embodiment of the present invention.

Fig. 4 is a side view of the structure of fig. 3.

Reference numerals:

1. a conductive substrate;

2. a test slot;

3. a boss;

4. and (6) rounding and chamfering.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.

It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the utility model pertains.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

As shown in fig. 1, the chip testing board provided in the embodiment of the present invention is applied to a chip testing device, the chip testing device includes a transfer box, a groove for placing a chip is formed on the transfer box, the chip testing board includes a conductive substrate 1, a test slot 2 corresponding to the groove on the transfer box is formed on the conductive substrate 1, wherein the conductive substrate 1 may be made of copper, aluminum, or the like, and the conductive substrate 1 is preferably made of aluminum.

The test slots 2 corresponding to the upper grooves of the transmission boxes are arranged on the conductive substrate 1 in an array mode, when chips are tested, the transmission boxes are aligned to the conductive substrate 1 in an overturning mode, the chips in the transmission boxes are all overturned and placed in the test slots 2, then testing of the chips in all the test slots 2 can be completed simultaneously, the test slots 2 arranged on the conductive substrate 1 in the array mode can meet the requirement of testing multiple chips in sequence, and testing efficiency is improved.

In another embodiment, as shown in fig. 3, the test slot 2 is concentrically provided with a boss 3, and the diameter of the boss 3 is smaller than that of the non-gluing table-board of the press-fit chip, so as to ensure that the boss 3 can contact with the non-gluing table-board of the press-fit chip.

The periphery of the pressure welding type chip is coated with glue protruding out of the table board, so that the periphery of the pressure welding type chip is thicker than the middle part, the pressure welding type chip is directly placed in the test groove 2 and cannot be in contact with the conductive substrate 1 for testing, the boss 3 concentrically arranged in the test groove 2 can avoid the contact of silica gel at the edge and the table board at the center of the chip, the pressure welding type chip is ensured to have a good test environment, and the pressure welding type chip with the periphery coated with the glue can be tested;

the original compression joint type chip test adopts that the corresponding molybdenum sheets are placed on a common flat aluminum plate, then the chip to be tested and the molybdenum sheets are concentrically placed flat, only 1 molybdenum sheet can be tested at one time, and if a plurality of molybdenum sheets need to be tested at one time, a plurality of molybdenum sheets are needed, so that the efficiency is low, and the placing and management of the molybdenum sheets on site are also a problem; the chip testing board provided by the embodiment solves the action of taking and placing chips one by one, can be directly aligned and turned over, saves the problem of concentric placement of molybdenum sheets, and obviously improves the production efficiency.

Further, as shown in fig. 4, the top periphery of the boss 3 is provided with a round chamfer 4.

Set up 3 top peripheries of boss into round chamfer 4, avoid 3 edges of boss to the fish tail of chip mesa, lead to the damage of chip.

In this embodiment, the depth of the test slot 2 is smaller than the thickness of the chip to be tested;

specifically, as shown in FIG. 2, the test slot 2 is provided with a depth H1, wherein the range of H1 is 3-5mm, and preferably, the depth H1 of the test slot 2 is 4 mm.

The depth of the test slot 2 is set to be that after a chip to be tested is placed in the test slot 2, the chip can protrude out of the surface of the conductive substrate 1, and the test chip is prevented from being difficult to take out after being embedded into the test slot.

As shown in FIG. 4, the height of the boss 3 is set to H2, wherein H2 is in the range of 2-4 mm.

Similarly, the height of the boss 3 is limited, so that when the compression joint type chip is tested, the whole chip is enabled to be protruded out of the surface of the conductive substrate 1, and the chip is placed to be embedded into the conductive substrate and is difficult to take out.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. The chip testing board is applied to a chip testing device, the chip testing device comprises a transfer box, and a groove for placing a chip is formed in the transfer box.

2. The chip testing board of claim 1, wherein the test slots have bosses concentrically disposed therein.

3. The chip test board according to claim 2, wherein the top periphery of the bosses is provided with a rounded chamfer.

4. The chip testing board according to claim 1, wherein the depth of the testing groove is smaller than the thickness of the chip to be tested.

5. The chip test board according to claim 4, wherein the test groove depth is set to 3-5 mm.

6. The chip test board according to claim 2, wherein the height of the projections is set to 2-4 mm.