CN215452936U

CN215452936U - Wireless transceiver supporting Wi-SUN protocol

Info

Publication number: CN215452936U
Application number: CN202121399920.7U
Authority: CN
Inventors: 游雪城; 孙香涛; 刘建; 廖先仪; 成锋; 张影
Original assignee: Lierda Science & Technology Group Co ltd
Current assignee: Lierda Science & Technology Group Co ltd
Priority date: 2021-06-23
Filing date: 2021-06-23
Publication date: 2022-01-07
Anticipated expiration: 2031-06-23

Abstract

The utility model discloses a wireless transceiver supporting a Wi-SUN protocol, which comprises a main control chip, wherein the main control chip is respectively connected with a power circuit, a clock circuit, a transmitting circuit, a receiving circuit and a high-frequency switch control circuit, and the receiving circuit and the transmitting circuit are respectively connected with the high-frequency switch control circuit. Based on the IEEE802.15.4 specification, the wireless transceiver has the advantages that large-scale networking can be realized, the working frequency band is 863 MHz-870 MHz, the transmitting power is up to 20dBm, the Wi-SUN protocol is supported, the wireless transceiver has high transceiving performance, and the wireless transceiver is suitable for low-power consumption, long-distance and large-scale networking.

Description

Wireless transceiver supporting Wi-SUN protocol

Technical Field

The utility model relates to the technical field of Internet of things, in particular to a wireless transceiver supporting a Wi-SUN protocol.

Background

The internet of things, namely the internet connected with everything, is an extended and expanded network on the basis of the internet, various information sensing devices and the network are combined to form a huge network, and the interconnection and intercommunication of people, machines and things at any time and any place are realized. Since the core technology of LoRaWAN is in the hands of SEMTECH, a company of LoRaWAN, and users of loran are bound to LoRa technology in this form, development and updating of the technology and changes in policy affect users of LoRaWAN. Although ZigBee is a standard mature networking technology, the network range of ZigBee is far from the requirement of the current Internet of things.

For example, a "wireless transceiver" disclosed in chinese patent literature, which is disclosed under a publication number CN101841346B, includes an antenna, a filter, a radio frequency signal processing circuit, a common amplifier circuit, a first switch circuit, a second switch circuit, a transmission power amplifier, and a single-pole double-throw switch. The filter is connected between the antenna and the single-pole double-throw switch. The radio frequency signal processing circuit is used for outputting a first control signal when sending a radio frequency signal and outputting a second control signal when receiving the radio frequency signal. The first switch circuit is connected between the common amplifier circuit and the transmission power amplifier and is used for being switched on or switched off according to a first control signal. The second switch circuit is connected between the common amplifier circuit and the single-pole double-throw switch and used for being switched on or switched off according to a second control signal. The single-pole double-throw switch is used for selectively connecting the filter and the transmitting power amplifier or connecting the filter and the second switch circuit. Although the transmitting end and the receiving end of the wireless transceiver can share the common amplifier circuit, thereby simplifying the circuit, reducing occupied space and lowering cost, the wireless transceiver has the defects of low transmitting and receiving performance and insufficient communication range meeting the requirements of the existing Internet of things. At present, the charging mode of NB-IOT and the like is not clear, so that the use cost of a user is higher. Another limitation is that the user data is run on the public network, which is a challenge for data security.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the problems of small contact range and low transceiving performance in the prior art, and provides a high-performance wireless transceiver which has high transceiving performance, can support a standard, normative and unbound network, can realize large-scale networking, has the working frequency band of 863 MHz-870 MHz, has the transmitting power as high as 20dBm and supports a Wi-SUN protocol.

In order to achieve the purpose, the utility model adopts the following technical scheme:

a wireless transceiver supporting a Wi-SUN protocol comprises a main control chip, wherein the main control chip is respectively connected with a power circuit, a clock circuit, a transmitting circuit, a receiving circuit and a high-frequency switch control circuit, and the receiving circuit and the transmitting circuit are respectively connected with the high-frequency switch control circuit. The scheme of the utility model is based on IEEE802.15.4 specification, and the utility model has high transceiving performance through device selection and circuit optimization and debugging with good quantity, the working frequency band is 863 MHz-870 MHz, the maximum output can be 20dBm, the current is about 120mA, and the receiving loop is amplified by LNA (low-noise amplifier), so that the scheme of the utility model can realize transmission at a longer distance, and support Wi-SUN (wireless fidelity-SunAN) protocol, and the utility model is very suitable for low-power consumption, long-distance and large-scale networking.

As a preferable scheme of the present invention, the power supply circuit includes a resistor R13, a capacitor C5, a capacitor C6, a capacitor C1, an inductor B1, and a power supply chip U1, one end of the capacitor C5 is connected to an input power supply 5V _ IN, the other end of the capacitor C5 is grounded, the capacitor C6 is connected IN parallel to the capacitor C5, one end of the resistor R13 is connected to the input power supply 5V _ IN, the other end of the resistor R13 is connected to an enable pin of the power supply chip, an input pin of the power supply chip is connected to the input power supply 5V _ IN, a ground pin of the power supply chip is grounded, one end of the capacitor C1 is connected to an output pin of the power supply chip, the other end of the capacitor C1 is grounded, one end of the inductor B1 is connected to an output pin of the power supply chip, and the other end of the inductor B1 is connected to an output terminal VDD _ MCU of the power supply circuit. The power supply is DC5V, the LDO is adopted in the power circuit to convert the voltage and output 3.3V for the main control chip, the transmitting circuit, the receiving circuit and the like to work, and the LDO with the input voltage range of DC 2-5.5V is selected in consideration of the input voltage range.

As a preferable scheme of the present invention, the clock circuit includes an MCU clock circuit and an RF clock circuit, the MCU clock circuit includes a capacitor C35, a capacitor C36, and a crystal oscillator X1, one end of the crystal oscillator X1 is grounded via a capacitor C35, the other end of the crystal oscillator X1 is grounded via a capacitor C36, the RF clock circuit includes a crystal oscillator X2, a capacitor C54C, a capacitor 55, and a resistor R31, an input pin of the crystal oscillator X2 is connected to one end of the capacitor C55, the other end of the capacitor C55 is connected to a first ground pin of the crystal oscillator X2, a first end of the resistor R31 is connected to an output pin of the crystal oscillator X2 via a capacitor C54, a first ground pin of the crystal oscillator X2 is connected to a first end of a resistor R31, a second ground pin of the crystal oscillator X2 is connected to a first end of the resistor R31, and a second end of the resistor R31 is grounded. The scheme of the utility model comprises two crystal oscillator circuits which are respectively provided for the main control chip and the RF. The capacitor C35, the capacitor C36, the capacitor C54 and the capacitor C55 are reserved crystal oscillator load capacitors, and because the crystal oscillator X1 provides a clock source for the MCU (namely an internal clock of a main control chip), the time synchronization in the networking process can be influenced, the EPSON is selected, and the precision of the crystal oscillator is 10 ppm; the crystal oscillator X2 provides an external clock for RF, and because the circuit has frequency offset calibration in practical test, the crystal oscillator has no high precision requirement, and TST is selected here, and the precision is 15 ppm.

As a preferred embodiment of the present invention, the transmitting circuit includes a resistor R9, a resistor R10, a capacitor C7, a capacitor C11, a capacitor C13, a capacitor C16, a capacitor C19, a capacitor C32, a capacitor C32, an inductor L2, an inductor L3, and an inductor L5, one end of the capacitor C52 is connected to the power circuit output terminal VDD _ MCU, the other end of the capacitor C52 is grounded, one end of the resistor R9 is connected to the power circuit output terminal VDD _ MCU via an inductor L1, the other end of the resistor R9 is connected to the first control power pin of the main control chip, one end of the resistor R10 is connected to the power circuit output terminal VDD _ MCU via an inductor L1, the other end of the resistor R10 is connected to the second control power pin of the main control chip, one end of the capacitor C7 is connected to the power circuit output terminal VDD _ MCU via an inductor L1, the other end of the capacitor C1 is connected to the ground, one end of the capacitor C13 is grounded through a capacitor C11, the other end of the capacitor C13 is grounded through an inductor L3, one end of the inductor L5 is grounded through an inductor L3, the other end of the inductor L5 is grounded through a capacitor C19, the capacitor C16 is connected with an inductor L5 in parallel, one end of the capacitor C32 is grounded through a capacitor C19, and the other end of the capacitor C32 is connected with a high-frequency switch control circuit. The working frequency band of the scheme of the utility model is 863 MHz-870 MHz, the output power can reach 20dBm, the main control chip can provide MPA output with the maximum 13dBm or HPA output with the maximum 20dBm, so the HPA port of the main control chip is selected for output. The output impedance of the main control chip is matched to 50 omega through impedance matching, so that the highest power and the best efficiency are realized, and finally, the transmitted harmonic waves are suppressed through a filter circuit.

As a preferable aspect of the present invention, the receiving circuit includes a balun circuit and an LNA control circuit.

As a preferable scheme of the present invention, the balun circuit includes a capacitor C9, a capacitor C10, a capacitor C2, a capacitor C15, an inductor L4, and an inductor L6, one end of the capacitor C9 is connected to a first signal receiving pin of the main control chip, the other end of the capacitor C9 is grounded via an inductor L4, one end of the capacitor C10 is connected to a second signal receiving pin of the main control chip, the other end of the capacitor C10 is grounded via a capacitor C15, one end of the capacitor C2 is grounded via an inductor L4, the other end of the capacitor C2 is connected to a radio frequency output pin of an LNA chip U6 in the LNA control circuit via a capacitor C58, one end of the inductor L6 is grounded via a capacitor C15, and the other end of the inductor L6 is connected to a radio frequency output pin of an LNA chip U6 in the LNA control circuit via a capacitor C58. The RX receiving end of the scheme of the utility model is in a differential mode, so single-end conversion is required to be carried out through a balun circuit, the balun circuit is designed by adopting a separating device, and capacitors C9 and C10 are blocking capacitors and play a role in isolating direct current.

As a preferred embodiment of the present invention, the LNA control circuit includes an inductor B3, an inductor L11, an inductor L13, a capacitor C25, a capacitor C53, a capacitor C61, a capacitor C62, a capacitor C33, a capacitor C60, a resistor R5, an LNA chip U5, and a filter SAW 5, a first ground terminal and a second ground terminal of the LNA chip U5 are grounded, a power supply pin of the LNA chip U5 is connected to a power supply circuit output terminal VDD _ MCU via the inductor B5, a power supply pin of the LNA chip U5 is grounded via the capacitor C5, a power supply pin of the LNA chip U5 is connected to a power supply terminal VCC _ LNA of the LNA control circuit VCC _ LNA, the capacitor C5 is connected in parallel to the capacitor C5 in the balun circuit, an enable pin of the LNA chip U5 is connected to the power supply terminal VCC _ LNA control circuit VCC _ LNA chip, an LNA chip enable pin of the LNA chip U5 is connected to the LNA chip 5 via the inductor L5, and an LNA chip L5 is connected to the LNA chip 5, the other end of inductor L13 ground connection, the one end of electric capacity C61 is through the one end of inductor L11 and LNA chip U6's radio frequency input pin link to each other, the other end of electric capacity C61 and the one end of electric capacity C62 link to each other, the other end of electric capacity C62 links to each other with the switch control circuit frequently, the one end of electric capacity C60 is through inductor L13 ground connection, the other end of electric capacity C60 and the fourth terminal of wave filter SAW1 link to each other, the second terminal, the third terminal and the fifth terminal of wave filter SAW1 all ground connection, the first terminal of wave filter SAW1 is through electric capacity C33 and frequency switch control circuit link to each other. In order to improve the receiving sensitivity performance of a receiving circuit, the LNA is selected for signal amplification, and the gain and noise coefficients of the LNA in the range of 863MHz to 870MHz are respectively 15dB and 1 dB. FIG. 8 is a circuit diagram of peripheral design of LNA, LNA enable pin of LNA chip U6, the operational mode of LNA can be switched through IOD10 of main control chip, namely the enable pin of LNA, so that the toughness of the module can be enhanced, and the LNA can be switched into Bypass mode to prevent the chip from being damaged when a high-power signal is input. Meanwhile, in order to reduce the interference of environmental noise to received signals as much as possible, a filter is connected in series with the input end of the LNA, the frequency band of the pass band is 863 MHz-870 MHz, and the insertion loss in the pass band is 2.5 dB.

As a preferable mode of the present invention, the high frequency switch control circuit includes a capacitor C32, a capacitor C33, a capacitor C40, a capacitor C41, a capacitor C42, an inductor L17, an inductor L18, a transient suppression diode D1, and a high frequency switch chip U9, a third rf signal pin of the high frequency switch chip U9 is connected to a capacitor C33 in the LNA control circuit through a capacitor C33, both a first ground pin and a second ground pin of the high frequency switch chip U9 are grounded, a second rf signal pin of the high frequency switch chip U9 is connected to an inductor L5 in the transmitter circuit through a capacitor C32, a first dc voltage control pin of the high frequency switch chip U9 is grounded through a capacitor C40, a second dc voltage control pin of the high frequency switch chip U9 is grounded through a capacitor C41, a first rf signal pin of the high frequency switch chip U9 is grounded through an inductor L17, a first end of the capacitor C42 is connected to a first rf signal pin of the high frequency switch chip U9, the second end of the capacitor C42 is grounded through an inductor L18, the transient suppression diode D1 is connected in parallel with the inductor L18, and the second end of the capacitor C42 is connected with an ANT pin of a main control chip. The TX and RX loops are switched by a high-frequency switch, wherein a control pin of the high-frequency switch is controlled by a main control chip.

As a preferable aspect of the present invention, the wireless transceiver further includes an external interface. The external interface of the circuit comprises a data serial port, a debugging serial port, a reset pin and an SPI (serial peripheral interface), wherein the data serial port is used for user data transmission, the debugging serial port is used for user network debugging or hardware performance, the reset pin is effective in low level, the module is provided with an internal power-on reset circuit, and the SPI can drive FLASH or SRAM.

Therefore, the utility model has the following beneficial effects: based on the IEEE802.15.4 specification, the wireless transceiver has the advantages that large-scale networking can be realized, the working frequency band is 863 MHz-870 MHz, the transmitting power is up to 20dBm, the Wi-SUN protocol is supported, the wireless transceiver has high transceiving performance, and the wireless transceiver is suitable for low-power consumption, long-distance and large-scale networking.

Drawings

FIG. 1 is a block diagram of the overall architecture of the present invention;

FIG. 2 is a schematic diagram of the power supply circuit of the present invention;

FIG. 3 is a schematic diagram of the MCU clock circuit of the present invention;

FIG. 4 is a schematic diagram of the RF clock circuit of the present invention;

FIG. 5 is a schematic diagram of the transmit circuit of the present invention;

FIG. 6 is a schematic diagram of the balun circuit of the present invention;

FIG. 7 is a schematic diagram of the LNA control circuit of the present invention;

fig. 8 is a schematic diagram of a high frequency switch control circuit of the present invention.

Detailed Description

The utility model is further described with reference to the following detailed description and accompanying drawings.

A wireless transceiver supporting Wi-SUN protocol is shown in figure 1 and comprises a main control chip, wherein the main control chip is respectively connected with a power circuit, a clock circuit, a transmitting circuit, a receiving circuit and a high-frequency switch control circuit, and the receiving circuit and the transmitting circuit are respectively connected with the high-frequency switch control circuit. The scheme of the utility model is based on IEEE802.15.4 specification, and the utility model has high transceiving performance through device selection and circuit optimization and debugging with good quantity, the working frequency band is 863 MHz-870 MHz, the maximum output can be 20dBm, the current is about 120mA, and the receiving loop is amplified by LNA (low-noise amplifier), so that the scheme of the utility model can realize transmission at a longer distance, and support Wi-SUN (wireless fidelity-SunAN) protocol, and the utility model is very suitable for low-power consumption, long-distance and large-scale networking.

As shown IN fig. 2, the power circuit includes a resistor R13, a capacitor C5, a capacitor C6, a capacitor C1, an inductor B1, and a power chip U1, one end of the capacitor C5 is connected to the input power 5V _ IN, the other end of the capacitor C5 is grounded, the capacitor C6 is connected IN parallel to the capacitor C5, one end of the resistor R13 is connected to the input power 5V _ IN, the other end of the resistor R13 is connected to an enable pin of the power chip, an input pin of the power chip is connected to the input power 5V _ IN, a ground pin of the power chip is grounded, one end of the capacitor C1 is connected to an output pin of the power chip, the other end of the capacitor C1 is grounded, one end of the inductor B1 is connected to an output pin of the power chip, and the other end of the inductor B1 is connected to the output terminal VDD _ MCU of the power circuit. The power supply is DC5V, the LDO is adopted in the power circuit to convert the voltage and output 3.3V for the main control chip, the transmitting circuit, the receiving circuit and the like to work, and the LDO with the input voltage range of DC 2-5.5V is selected in consideration of the input voltage range. As shown in fig. 2, in order to ensure that the noise on the chip input power supply is as small as possible, a 1 μ F shunt capacitor to ground needs to be connected in parallel to the input pin of the power supply chip; the enabling pin of the power chip is a chip closing control pin, a low-level closing chip and a high-level enabling chip, and because the output 3.3V needs to be provided for the main chip, the LDO cannot be in a closing state, so that the LDO is pulled up to an input voltage through a 10K resistor; the output pin of the power supply chip is a chip voltage output end, and in order to better suppress noise and improve the stability of output voltage, the output end is connected with a filter capacitor of 1uF or more in parallel.

The clock circuit comprises an MCU clock circuit and an RF clock circuit, as shown in FIG. 3, the MCU clock circuit comprises a capacitor C35, a capacitor C36 and a crystal oscillator X1, one end of the crystal oscillator X1 is grounded through the capacitor C35, and the other end of the crystal oscillator X1 is grounded through the capacitor C36, as shown in FIG. 4, the RF clock circuit comprises a crystal oscillator X2, a capacitor C54C, a capacitor 55 and a resistor R31, a first pin of the crystal oscillator X2 is connected with one end of the capacitor C55, the other end of the capacitor C55 is connected with a second pin of the crystal oscillator X2, a first end of the resistor R31 is connected with a third pin of the crystal oscillator X2 through the capacitor C54, a second pin of the crystal oscillator X2 is connected with a first end of the resistor R31, a fourth pin of the crystal oscillator X2 is connected with a first end of the resistor R31, and a second end of the resistor R31 is grounded. The scheme of the utility model comprises two crystal oscillator circuits which are respectively provided for the main control chip and the RF. The capacitor C35, the capacitor C36, the capacitor C54 and the capacitor C55 are reserved crystal oscillator load capacitors, and because the crystal oscillator X1 provides a clock source for the MCU (namely an internal clock of a main control chip), the time synchronization in the networking process can be influenced, the EPSON is selected, and the precision of the crystal oscillator is 10 ppm; the crystal oscillator X2 provides an external clock for RF, and because the circuit has frequency offset calibration in practical test, the crystal oscillator has no high precision requirement, and TST is selected here, and the precision is 15 ppm.

As shown in fig. 5, the transmitting circuit includes a resistor R9, a resistor R10, a capacitor C7, a capacitor C11, a capacitor C13, a capacitor C16, a capacitor C19, a capacitor C32, a capacitor C32, an inductor L2, and an inductor L2, one end of the capacitor C2 is connected to the power circuit output terminal VDD _ MCU, the other end of the capacitor C2 is grounded, one end of the resistor R2 is connected to the power circuit output terminal VDD _ MCU via the inductor L2, the other end of the resistor R2 is connected to the first control power pin of the main control chip, one end of the capacitor C2 is connected to the power circuit output terminal VDD _ MCU via the inductor L2, one end of the capacitor C2 is connected to one end of the inductor L2, the other end of the inductor L2 is grounded via the capacitor C2, one end of the capacitor C2 is connected to the ground via the inductor L2, and the other end of the capacitor C2 is grounded via the capacitor C2, one end of an inductor L5 is grounded through an inductor L3, the other end of an inductor L5 is grounded through a capacitor C19, a capacitor C168 is connected with the inductor L5 in parallel, one end of a capacitor C32 is grounded through a capacitor C19, and the other end of a capacitor C32 is connected with a high-frequency switch control circuit. The working frequency band of the scheme of the utility model is 863 MHz-870 MHz, the output power can reach 20dBm, the main control chip can provide MPA output with the maximum 13dBm or HPA output with the maximum 20dBm, so the HPA port of the main control chip is selected for output. The output impedance of the main control chip is matched to 50 omega through impedance matching, so that the highest power and the best efficiency are realized, and finally, the transmitted harmonic waves are suppressed through a filter circuit. As shown in FIG. 5, the transmitting circuit selects the HPA circuit of the chip to transmit through the selection resistor, and the 3.3V power supply is connected with the output of the chip through the bias inductor L1 to prevent the radio frequency signal from flowing backwards to influence the power supply. And an impedance matching network consisting of an inductor L2 and a capacitor C11 is used for matching the output impedance of the chip to a 50 omega resistor. The capacitor C16 and the inductor L5 form a second harmonic filter circuit which mainly determines the output power of the second harmonic, and the rest form another filter which mainly completes the filtering of higher harmonics. And finally, the direct current is sent to a high-frequency switch control circuit through a C32 blocking capacitor.

As shown in fig. 6, the balun circuit includes a capacitor C9, a capacitor C10, a capacitor C2, a capacitor C15, an inductor L4, and an inductor L6, one end of the capacitor C9 is connected to the first signal receiving pin of the main control chip, the other end of the capacitor C9 is grounded via the inductor L4, one end of the capacitor C10 is connected to the second signal receiving pin of the main control chip, the other end of the capacitor C10 is grounded via the capacitor C15, one end of the capacitor C2 is grounded via the inductor L4, the other end of the capacitor C2 is connected to the rf output pin of the LNA chip U6 in the LNA control circuit via the capacitor C58, one end of the inductor L6 is grounded via the capacitor C15, and the other end of the inductor L6 is connected to the rf output pin of the LNA chip U6 in the LNA control circuit via the capacitor C58. The RX receiving end of the scheme of the present invention is in a differential mode, so single-end conversion needs to be performed through a balun circuit, and the balun circuit is designed by using a separation device, as shown in fig. 6, wherein capacitors C9 and C10 are dc blocking capacitors, and play a role in isolating dc current.

As shown in fig. 7, the LNA control circuit includes an inductor B3, an inductor L11, an inductor L13, a capacitor C25, a capacitor C53, a capacitor C61, a capacitor C62, a capacitor C33, a capacitor C60, a resistor R5, an LNA chip U5, a filter SAW 5, a first ground terminal and a second ground terminal of the LNA chip U5 are grounded, a power supply pin of the LNA chip U5 is connected to a power supply terminal VDD _ MCU of the power supply circuit via the inductor B5, a power supply pin of the LNA chip U5 is grounded via the capacitor C5, a power supply pin of the LNA chip U5 is connected to a power supply terminal VCC _ LNA control circuit, the capacitor C5 is connected in parallel to the capacitor C5, a radio frequency output pin of the LNA chip U5 is connected to the capacitor C5 in the balun circuit, an LNA enable pin of the LNA chip U5 is connected to the LNA control circuit terminal VCC _ LNA control circuit via the inductor L5, an LNA enable pin of the LNA chip 5 is connected to the LNA chip 5, the other end of the inductor L13 is grounded, one end of a capacitor C61 is connected with a radio frequency input pin of the LNA chip U6 through one end of an inductor L11, the other end of the capacitor C61 is connected with one end of a capacitor C62, the other end of the capacitor C62 is connected with the frequency switch control circuit, one end of a capacitor C60 is grounded through the inductor L13, the other end of a capacitor C60 is connected with a fourth terminal of the filter SAW1, a second terminal, a third terminal and a fifth terminal of the filter SAW1 are all grounded, and a first terminal of the filter SAW1 is connected with the frequency switch control circuit through the capacitor C33. In order to improve the receiving sensitivity performance of a receiving circuit, the LNA is selected for signal amplification, and the gain and noise coefficients of the LNA in the range of 863MHz to 870MHz are respectively 15dB and 1 dB. FIG. 8 is a circuit diagram of peripheral design of LNA, LNA enable pin of LNA chip U6, the operational mode of LNA can be switched through IOD10 of main control chip, namely the enable pin of LNA, so that the toughness of the module can be enhanced, and the LNA can be switched into Bypass mode to prevent the chip from being damaged when a high-power signal is input. Meanwhile, in order to reduce the interference of environmental noise to received signals as much as possible, a filter is connected in series with the input end of the LNA, the frequency band of the pass band is 863 MHz-870 MHz, and the insertion loss in the pass band is 2.5 dB.

As shown in fig. 8, the high-frequency switch control circuit includes a capacitor C32, a capacitor C33, a capacitor C40, a capacitor C41, a capacitor C42, an inductor L17, an inductor L18, a transient suppression diode D1, and a high-frequency switch chip U9, the third rf signal pin of the high-frequency switch chip U9 is connected to a capacitor C33 in the LNA control circuit through a capacitor C33, the first ground pin and the second ground pin of the high-frequency switch chip U9 are both grounded, the second rf signal pin of the high-frequency switch chip U9 is connected to an inductor L5 in the transmitter circuit through a capacitor C32, the first dc control pin of the high-frequency switch chip U9 is grounded through a capacitor C40, the second dc control pin of the high-frequency switch chip U9 is grounded through a capacitor C41, the first rf signal pin of the high-frequency switch chip U9 is grounded through an inductor L17, the first end of the capacitor C42 is connected to the first dc signal pin of the high-frequency switch chip U9, and the second end of the inductor L42 is grounded through a capacitor C18, the transient suppression diode D1 is connected in parallel with the inductor L18, and the second terminal of the capacitor C42 is connected to the ANT pin of the main control chip. The TX and RX loops are switched by high frequency switches and are designed as shown in fig. 8. Wherein the control pin of the high-frequency switch is controlled by the main control chip,

the utility model also comprises an external interface. The external interface of the circuit comprises a data serial port, a debugging serial port, a reset pin and an SPI (serial peripheral interface), wherein the data serial port is used for user data transmission, the debugging serial port is used for user network debugging or hardware performance, the reset pin is effective in low level, the module is provided with an internal power-on reset circuit, and the SPI can drive FLASH or SRAM.

Based on the IEEE802.15.4 specification, the main control chip adopts a VC7300 chip, the working frequency band is 863 MHz-870 MHz, the transmitting power is as high as 20dBm, the receiving sensitivity is as high as-110 dBm under the conditions of 50Kbps, 250-byte packet length and 10% packet loss rate through device selection and circuit optimization and debugging with good quantity, and the wireless transceiver is high in performance.

The scheme of the utility model is hardware supporting Wi-SUN protocol, can provide a wireless networking scheme supporting standard, normative and unbound and capable of realizing large-scale networking for a user, can solve the related problems of the Internet of things industry, can realize large-scale networking application, is low in power consumption, is convenient to transform various Internet of things devices in a long distance, and reduces the transformation cost.

The above description is only for the specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the inventive work should be covered within the protection scope of the present invention.

Claims

1. A wireless transceiver supporting a Wi-SUN protocol is characterized by comprising a main control chip, wherein the main control chip is respectively connected with a power circuit, a clock circuit, a transmitting circuit, a receiving circuit and a high-frequency switch control circuit, and the receiving circuit and the transmitting circuit are respectively connected with the high-frequency switch control circuit.

2. A wireless transceiver supporting the Wi-SUN protocol according to claim 1, it is characterized in that the power supply circuit comprises a resistor R13, a capacitor C5, a capacitor C6, a capacitor C1, an inductor B1 and a power supply chip U1, one end of the capacitor C5 is connected with an input power supply 5V _ IN, the other end of the capacitor C5 is grounded, the capacitor C6 is connected with the capacitor C5 IN parallel, one end of the resistor R13 is connected with the input power supply 5V _ IN, the other end of the resistor R13 is connected with an enable pin of the power supply chip, an input pin of the power supply chip is connected with an input power supply 5V _ IN, the grounding pin of the power chip is grounded, one end of the capacitor C1 is connected with the output pin of the power chip, the other end of the capacitor C1 is grounded, one end of the inductor B1 is connected with an output pin of the power supply chip, and the other end of the inductor B1 is connected with an output end VDD _ MCU of the power supply circuit.

3. A wireless transceiver supporting the Wi-SUN protocol according to claim 1, it is characterized in that the clock circuit comprises an MCU clock circuit and an RF clock circuit, the MCU clock circuit comprises a capacitor C35, a capacitor C36 and a crystal oscillator X1, one end of the crystal oscillator X1 is grounded through a capacitor C35, the other end of the crystal oscillator X1 is grounded through a capacitor C36, the RF clock circuit comprises a crystal oscillator X2, a capacitor C54C, a capacitor 55 and a resistor R31, the input pin of the crystal oscillator X2 is connected with one end of a capacitor C55, the other end of the capacitor C55 is connected with the first grounding pin of the crystal oscillator X2, the first end of the resistor R31 is connected with the output pin of the crystal oscillator X2 through the capacitor C54, the first grounding pin of the crystal oscillator X2 is connected with the first end of the resistor R31, the second grounding pin of the crystal oscillator X2 is connected with the first end of the resistor R31, and the second end of the resistor R31 is grounded.

4. The wireless transceiver of claim 1, wherein the transmitting circuit comprises a resistor R9, a resistor R10, a capacitor C7, a capacitor C11, a capacitor C13, a capacitor C16, a capacitor C19, a capacitor C32, an inductor L2, an inductor L3 and an inductor L5, one end of the capacitor C52 is connected to the power circuit output terminal VDD _ MCU, the other end of the capacitor C52 is grounded, one end of the resistor R9 is connected to the power circuit output terminal VDD _ MCU through the inductor L1, the other end of the resistor R9 is connected to the first control power pin of the master chip, one end of the resistor R10 is connected to the power circuit output terminal VDD _ MCU through the inductor L1, the other end of the resistor R10 is connected to the second control power pin of the master chip, one end of the capacitor C7 is connected to the power circuit output terminal VDD _ MCU through the inductor L1, the other end of the capacitor C7 is connected to one end of the inductor L2, the other end of the inductor L2 is grounded through a capacitor C11, one end of the capacitor C13 is grounded through a capacitor C11, the other end of the capacitor C13 is grounded through an inductor L3, one end of the inductor L5 is grounded through an inductor L3, the other end of the inductor L5 is grounded through a capacitor C19, the capacitor C16 is connected with the inductor L5 in parallel, one end of the capacitor C32 is grounded through a capacitor C19, and the other end of the capacitor C32 is connected with a high-frequency switch control circuit.

5. A wireless transceiver supporting a Wi-SUN protocol according to claim 1, wherein the receive circuit comprises a balun circuit and an LNA control circuit.

6. The wireless transceiver of claim 5, wherein the balun circuit comprises a capacitor C9, a capacitor C10, a capacitor C2, a capacitor C15, an inductor L4, and an inductor L6, one end of the capacitor C9 is connected to the first signal receiving pin of the main control chip, the other end of the capacitor C9 is connected to ground via the inductor L4, one end of the capacitor C10 is connected to the second signal receiving pin of the main control chip, the other end of the capacitor C10 is connected to ground via the capacitor C15, one end of the capacitor C2 is connected to ground via the inductor L4, the other end of the capacitor C2 is connected to the rf output pin of the LNA chip U6 in the LNA control circuit via the capacitor C58, one end of the inductor L6 is connected to ground via the capacitor C15, and the other end of the inductor L6 is connected to the rf output pin of the LNA chip U6 in the LNA control circuit via the capacitor C58.

7. A wireless transceiver supporting Wi-SUN protocol according to claim 5, wherein the LNA control circuit comprises an inductor B3, an inductor L11, an inductor L13, a capacitor C25, a capacitor C53, a capacitor C61, a capacitor C62, a capacitor C33, a capacitor C60, a resistor R5, a resistor R22, an LNA chip U6, and a filter SAW1, wherein the first ground terminal and the second ground terminal of the LNA chip U6 are grounded, the power supply pin of the LNA chip U6 is connected to the power supply circuit output VDD _ MCU via the inductor B3, the power supply pin of the LNA chip U6 is grounded via the capacitor C25, the power supply pin of the LNA chip U6 is connected to the LNA control circuit power supply terminal VCC _ LNA, the capacitor C53 is connected to the capacitor C25 in parallel, the RF output pin of the LNA chip U6 is connected to the capacitor C58 in the balun circuit, and the LNA enable pin of the LNA chip U6 is connected to the LNA control circuit power supply terminal VCC 34 via the resistor R5, an LNA enable pin of the LNA chip U6 is grounded through a resistor R22, a radio frequency input pin of the LNA chip U6 is connected with one end of an inductor L13 through an inductor L11, the other end of the inductor L13 is grounded, one end of a capacitor C61 is connected with the radio frequency input pin of the LNA chip U6 through one end of an inductor L11, the other end of a capacitor C61 is connected with one end of a capacitor C62, the other end of the capacitor C62 is connected with a frequency switch control circuit, one end of the capacitor C60 is grounded through an inductor L13, the other end of the capacitor C60 is connected with a fourth terminal of a filter SAW1, a second terminal, a third terminal and a fifth terminal of the filter SAW1 are grounded, and a first terminal of the filter SAW1 is connected with the frequency switch control circuit through a capacitor C33.

8. The wireless transceiver of claim 1, wherein the high frequency switch control circuit comprises a capacitor C32, a capacitor C33, a capacitor C40, a capacitor C41, a capacitor C42, an inductor L17, an inductor L18, a transient suppression diode D1, and a high frequency switch chip U9, wherein the third RF signal pin of the high frequency switch chip U9 is connected to a capacitor C33 of the LNA control circuit via a capacitor C33, the first ground pin and the second ground pin of the high frequency switch chip U9 are grounded, the second RF signal pin of the high frequency switch chip U9 is connected to an inductor L5 of the transmitter circuit via a capacitor C32, the first DC voltage control pin of the high frequency switch chip U9 is grounded via a capacitor C40, the second DC voltage control pin of the high frequency switch chip U9 is grounded via a capacitor C41, and the first RF signal pin 17 of the high frequency switch chip U9 is grounded via an inductor L4934, the first end of the capacitor C42 is connected with a first radio frequency signal pin of a high-frequency switch chip U9, the second end of the capacitor C42 is grounded through an inductor L18, the transient suppression diode D1 is connected with an inductor L18 in parallel, and the second end of the capacitor C42 is connected with an ANT pin of a main control chip.

9. A wireless transceiver supporting a Wi-SUN protocol according to claim 1, further comprising an external interface.