CN215416634U - Offline downloader for FPGA upgrading - Google Patents

Abstract

The application relates to the field of integrated circuits and discloses an offline downloader for FPGA upgrading. The off-line downloader comprises a CPU unit, N groups of buffer units, N groups of parallel JTAG interface units and a multi-path selector, wherein the CPU unit is provided with a TAP controller, TCK, TMS and TDI ports, the first input end, the second input end and the third input end of each group of buffer units are respectively connected with the TCK, TMS and TDI ports of the CPU unit, the TCK, TMS and TDI interfaces of each group of JTAG interface units are respectively connected with the first output end, the second output end and the third output end of each group of buffer units, the fourth input end of each group of buffer units is connected with the TDO of each group of JTAG interface units, the first input end, the second input end and the third input end of the multi-path selector are respectively connected with the fourth output end of each group of buffer units, and the output end of the multi-path selector is connected with the TDO port of the CPU unit. According to the implementation mode of the application, parallel offline upgrade of a plurality of FPGA devices can be realized.

Description

Offline downloader for FPGA upgrading

Technical Field

The application relates to the field of integrated circuits, in particular to an offline downloader technology for FPGA upgrading.

Background

In a programmable logic device, a configuration module is the most basic unit for the whole FPGA/CPLD to work, and after a user designs a functional logic circuit, a bit binary file is usually generated by a manufacturer EDA tool, and then the binary file is solidified into a Flash memory by an online downloader.

For offline download, the current common scheme is: directly programming a binary file to be updated into a Flash device through a burning machine, and then mounting the device on a board level through PCB processing.

Disclosure of Invention

The application aims to provide an offline downloader for FPGA upgrading, which can realize parallel offline upgrading of a plurality of FPGA devices.

The application discloses an off-line downloader for FPGA upgrading includes:

a CPU unit configured with a TAP controller and TCK, TMS, TDI ports;

the first, second and third input ends of each group of buffer units are respectively connected with TCK, TMS and TDI ports of the CPU unit;

n groups of parallel JTAG interface units, wherein TCK, TMS and TDI interfaces of each group of JTAG interface units are respectively connected with the first, second and third output ends of each group of buffer units, and the fourth input end of each group of buffer units is connected with TDO of each group of JTAG interface units;

and a multiplexer, wherein the first, second and third input terminals of the multiplexer are respectively connected with the fourth output terminal of each group of buffer units, and the output terminal of the multiplexer is connected to the TDO port of the CPU unit.

In a preferred embodiment, each set of buffer units comprises four sets of parallel buffers.

In a preferred embodiment, the multiplexer is controlled by a dial switch so that the return signal TDO can be effectively received.

In a preferred example, the CPU unit is a single chip microcomputer, an ARM, or an MCU.

In a preferred embodiment, the N groups of parallel JTAG interface units are further used for connecting N groups of FPGA devices to be upgraded.

In a preferred embodiment, the offline downloader further includes a power switch and a storage medium interface unit respectively connected to the CPU unit, where the storage medium interface unit is used to access a storage medium, and the storage medium stores an upgrade version file;

after the power switch is switched on, the off-line downloader directly downloads the upgrade version file from the storage medium to the memory and performs off-line upgrade of the N groups of FPGAs through the TAP controller.

Compared with the prior art, the embodiment of the application at least comprises the following advantages:

the multi-path parallel offline downloader is designed by the CPU unit, the N groups of buffer units, the N groups of parallel JTAG interface units and the multi-path selector, so that parallel offline upgrade of a plurality of FPGA devices is realized, and the FPGA upgrade efficiency is improved.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

Fig. 1 is a schematic structural diagram of an offline downloader for FPGA upgrade according to a first embodiment of the present application.

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

Description of partial concepts:

FPGA: field Programmable Gate Array.

GPIO: general-purpose input/output, General IO.

JTAG: joint Test Action Group, Joint Test workgroup.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The first embodiment of the present application relates to an offline downloader for FPGA upgrade, which has a structure as shown in fig. 1, and includes a CPU unit, N groups of buffer units, N groups of parallel JTAG interface units, and a multiplexer.

The CPU unit is provided with a TAP controller and TCK, TMS and TDI ports; the first, second and third input ends of each group of buffer units are respectively connected with TCK, TMS and TDI ports of the CPU unit; TCK, TMS, TDI interfaces of each group of JTAG interface units are respectively connected with the first, second and third output ends of each group of buffer units, and the fourth input end of each group of buffer units is connected with TDO of each group of JTAG interface units; the first, second and third input terminals of the multiplexer are respectively connected with the fourth output terminal of each group of buffer units, and the output terminal of the multiplexer is connected to the TDO port of the CPU unit.

The specific implementation manner of configuring the TAP controller in the CPU unit belongs to the prior art, and is not described herein.

Optionally, each group of buffer units comprises four groups of parallel buffers.

Alternatively, the multiplexer is switching controlled by a dial switch. TDO is an input signal of an external device to be downloaded, readback information such as an ID of the device is transmitted through the TDO, due to the fact that the number of downloader paths is large, an off-line downloader can circularly send an instruction for reading the ID of the device for ensuring the connectivity of a configuration link before configuration, and after the instruction is returned, the instruction is switched through an external dial switch, and a return value of each path is obtained.

Optionally, the CPU unit is a single chip microcomputer, an ARM, or an MCU.

Optionally, the N groups of parallel JTAG interface units are further configured to connect N groups of FPGA devices to be upgraded, the offline downloader further includes a power switch and a storage medium interface unit respectively connected to the CPU unit, and the storage medium (such as a usb disk/SD card/ethernet) stores an upgrade version file; after the power switch is switched on, the off-line downloader directly downloads the upgrade version file from the storage medium to the memory and performs off-line upgrade of the N groups of FPGAs through the TAP controller.

Optionally, the N groups of parallel JTAG interface units are further configured to connect N groups of FPGA devices to be upgraded, the offline downloader further includes a power switch, a display screen, and a storage medium interface unit respectively connected to the CPU unit, and the storage medium (such as a usb disk/SD card/ethernet) stores a JTAG link connection check file and an upgrade version file; after the power switch is switched on, the offline downloader downloads a JTAG link communication check file, an upgrade version file and a check file to the memory from the storage medium in sequence, and the TAP controller downloads the JTAG link communication check file and the upgrade version file to the N groups of FPGA in sequence, if the verification is passed, a target device is displayed on the display screen, otherwise, a non-target device is displayed on the display screen; and after the upgrade is finished, reading the download verification file, verifying whether the upgrade version file is updated and loaded, if the upgrade version file is successfully loaded, displaying that the download is successful on the display screen, otherwise, displaying that the download is failed on the display screen.

The specific implementation manner of the offline downloader directly downloading the file from the storage medium to the memory and the verification device upgrade status based on the verification file belongs to the prior art, and is not described herein again.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

All documents mentioned in this application are to be considered as being incorporated in their entirety into the disclosure of this application so as to be subject to modification as necessary. Further, it is understood that various changes or modifications may be made to the present application by those skilled in the art after reading the above disclosure of the present application, and such equivalents are also within the scope of the present application as claimed.

Claims (6)

1. An offline downloader for FPGA upgrades, comprising:

a CPU unit configured with a TAP controller and TCK, TMS, TDI ports;

the first, second and third input ends of each group of buffer units are respectively connected with TCK, TMS and TDI ports of the CPU unit;

n groups of parallel JTAG interface units, wherein TCK, TMS and TDI interfaces of each group of JTAG interface units are respectively connected with the first, second and third output ends of each group of buffer units, and the fourth input end of each group of buffer units is connected with TDO of each group of JTAG interface units;

and a first input end, a second input end and a third input end of the multiplexer are respectively connected with the fourth output end of each group of buffer units, and the output end of the multiplexer is connected to the TDO port of the CPU unit.

2. The offline downloader for FPGA upgrades of claim 1, wherein each set of buffer units comprises four sets of parallel buffers.

3. The offline downloader for FPGA upgrade as recited in claim 1, wherein said multiplexer is switching-controlled by a dial switch so that the return signal TDO can be efficiently received.

4. The offline downloader for FPGA upgrades of claim 1, wherein the CPU unit is a single chip, an ARM, or an MCU.

5. The offline downloader for FPGA upgrades of claim 1, wherein the N sets of parallel JTAG interface units are further used to connect N sets of FPGA devices to be upgraded.

6. The offline downloader for FPGA upgrade of claim 5, further comprising a power switch and a storage medium interface unit respectively connected to the CPU unit, wherein the storage medium interface unit is configured to access a storage medium, and the storage medium stores an upgrade version file;

after the power switch is switched on, the off-line downloader directly downloads the upgrade version file from the storage medium to the memory and performs off-line upgrade of the N groups of FPGAs through the TAP controller.

Images