CN215375528U - Semiconductor device test fixture - Google Patents
Semiconductor device test fixture Download PDFInfo
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- CN215375528U CN215375528U CN202121795074.0U CN202121795074U CN215375528U CN 215375528 U CN215375528 U CN 215375528U CN 202121795074 U CN202121795074 U CN 202121795074U CN 215375528 U CN215375528 U CN 215375528U
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- accommodating groove
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Abstract
The utility model provides a semiconductor device test fixture, comprising: a base and a sliding latch; the edge of the upper surface of the base is provided with a first accommodating groove, two electrodes are symmetrically arranged on one surface of the first accommodating groove, which is opposite to the semiconductor pins, the pins and the electrodes are arranged correspondingly, an insulating strip is arranged between the two electrodes, a test circuit is embedded in the base, the two electrodes are respectively connected with the test circuit through leads, and one end of the test circuit is grounded; one end of the sliding clamping device is arranged in the first accommodating groove and is arranged below the insulating strip, the sliding clamping device is connected with the first accommodating groove in a sliding mode, the other end of the sliding clamping device extends out of the outer end of the first accommodating groove and extends towards the direction of the semiconductor chip to be tested, and when the pin of the semiconductor chip is completely attached to the electrode of the base, the extending end of the sliding clamping device is attached to the side wall of the semiconductor chip. The utility model applies pressing force on the side wall of the semiconductor chip through the sliding clamping device, thereby ensuring the safety and reliability of the semiconductor chip.
Description
Technical Field
The utility model belongs to the technical field of semiconductor packaging test, and particularly relates to a semiconductor device test fixture.
Background
A semiconductor chip is a semiconductor device which is etched, wired, or formed on a semiconductor wafer and can realize a certain function. The production flow of semiconductor devices is roughly: the method comprises the steps of wafer manufacturing, wafer testing, chip packaging and testing after packaging. The semiconductor packaging test refers to a process of processing a wafer passing the test according to a product model and a function requirement to obtain an independent chip; and a specific fixture is required to be used for testing the junction-to-case thermal resistance of the semiconductor chip device in the semiconductor packaging test stage. The semiconductor clamp used at present is as follows: CN 211653054U, patent name: the utility model relates to a clamp for testing the thermal resistance between an SMD packaged semiconductor device and a shell, which has a complex structure, and a clamping device with the structure directly acts on the upper surface of a semiconductor chip, so that an electrode of the semiconductor chip is vertically pressed and contacted with a testing electrode, and the testing electrode or the semiconductor electrode is easy to wear and damage an electrical element; meanwhile, the semiconductor is required to be ensured to have no electrostatic action in the packaging test stage, and the test fixture related to the patent does not have an anti-electrostatic structure, so that the semiconductor chip generates static electricity in the test stage, and the electrostatic action possibly breaks through the semiconductor device to cause the failure and damage of the semiconductor device.
SUMMERY OF THE UTILITY MODEL
The utility model provides a semiconductor device test fixture, aiming at solving the technical problems that in the prior art, a semiconductor device test fixture pressing device vertically acts on a semiconductor chip, so that a semiconductor chip electrode and a test electrode are mutually abraded due to vertical force, and the semiconductor device is accelerated to lose efficacy and damage,
the technical scheme of the utility model is as follows: a semiconductor device test fixture, comprising:
the semiconductor chip to be tested is placed in the first accommodating groove; first electrode, second electrode are provided with for the one side symmetry of the semiconductor pin that awaits measuring on the first holding tank, and the pin includes: the testing device comprises a base, a first electrode, a second electrode, a testing circuit and a tester, wherein the first electrode corresponds to the first pin, the second electrode corresponds to the second pin, an insulating strip is arranged between the first electrode and the second electrode and used for preventing short circuit, the testing circuit is pre-embedded in the base, the first electrode and the second electrode are respectively connected with the testing circuit through leads, one end of the testing circuit is grounded, and the other end of the testing circuit is electrically connected with the tester;
one end of the sliding clamping device is arranged in the first accommodating groove and is arranged below the insulating strip, the sliding clamping device is connected with the first accommodating groove in a sliding mode, the other end of the sliding clamping device extends out of the outer end of the first accommodating groove and extends towards the direction of the semiconductor chip to be tested, and when the pin of the semiconductor chip to be tested is completely attached to the base electrode, the extending end of the sliding clamping device is attached to the side wall of the semiconductor chip to be tested.
Optionally, the second accommodating groove is formed in the first accommodating groove and below the insulating strip, and the sliding clamping device is arranged in the second accommodating groove.
Optionally, the sliding latch comprises:
one end of the elastic piece is fixedly connected to the inner wall of the second accommodating groove, the inner wall of the second accommodating groove is also provided with a sliding groove oppositely, and the sliding groove is arranged in parallel with the elastic piece;
the two ends of the sliding block are symmetrically provided with bulges which are arranged in the sliding chute and used for sliding the sliding block, and the other end of the elastic piece is fixedly connected with the sliding block;
the push rod is fixedly connected to the sliding block and is coaxially arranged with the elastic piece;
the stop plate is fixedly connected with the tail end of the push rod, and the stop plate is attached to the outer surface of the base when the elastic piece is located at the original position.
Optionally, the resilient member is a spring.
Optionally, the test device further comprises a dust cover, wherein one end of the dust cover is hinged to the edge of the first accommodating groove, and when the dust cover is closed, the dust cover wraps the first accommodating groove, the sliding clamping device and the semiconductor chip to be tested.
Optionally, the dust cover is L-shaped, and when the dust cover is closed, the upper surface of the dust cover is parallel to the upper surface of the base, and the inner side wall of the dust cover is attached to the outer surface of the blocking plate.
Optionally, the first accommodating groove is fixedly connected to the first end of the first accommodating groove.
The utility model has the beneficial effects that: the utility model provides a semiconductor device test fixture, which changes the existing pressure type clamping mode into a lateral clamping mode by arranging a transverse slidable sliding clamping device, releases the pressure between a semiconductor electrode and an electrode of the test fixture, and ensures that the electrode of a semiconductor chip is not damaged due to clamping force; meanwhile, the existing semiconductor packaging test device is not provided with an anti-static device, and the semiconductor chip possibly generates static electricity in the packaging test stage, and the static electricity can damage the semiconductor when directly acting on the semiconductor chip device. The utility model is also provided with a dust cover, and because dustless operation needs to be ensured in the production process of the semiconductor chip, the dust cover avoids dust particles in a workshop from influencing the test process and prevents test failure.
Drawings
FIG. 1 is a schematic diagram of an overall structure of a semiconductor device test fixture according to the present invention;
FIG. 2 is an enlarged view of a portion of A-A of FIG. 1;
FIG. 3 is a schematic view of the slide clamp of FIG. 1;
FIG. 4 is a schematic diagram of the circuit connection structure of FIG. 1;
FIG. 5 is a top view of a semiconductor chip;
fig. 6 is a schematic structural diagram of the slider in fig. 2.
The testing device comprises a base 1, a first accommodating groove 1-1, a pin 2, a first pin 2-1, a second pin 2-2, a first electrode 3, a second electrode 4, an insulating strip 5, a testing circuit 6, a sliding clamping device 7, an elastic piece 7-1, a sliding block 7-2, a protrusion 7-3, a push rod 7-4, a blocking plate 7-5, a second accommodating groove 8-1, a sliding groove 8-1, a dust cover 9, a base wiring board 10 and a semiconductor chip 11.
Detailed Description
An embodiment of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the embodiment.
In the description of the present invention, it should be understood that the terms "lateral", "longitudinal", "vertical", "edge", "inner wall", "upper", "outer", "facing", "lower", "surface", "vertical", "horizontal", "top", "axial", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing technical solutions of the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1, 2, 4, and 5, an embodiment of the present invention provides a semiconductor device test fixture, including: the testing device comprises a base 1 and a sliding clamping device 7, wherein a first accommodating groove 1-1 is formed in the edge of the upper surface of the base 1, and a semiconductor chip 11 to be tested is placed in the first accommodating groove 1-1; first electrode 3, second electrode 4 are provided with symmetrically for the one side of awaiting measuring semiconductor pin 2 on first holding tank 1-1, and first electrode 3 and second electrode 4 electrode electrical property are just opposite, and pin 2 includes: the testing device comprises a first pin 2-1 and a second pin 2-2, wherein a first electrode 3 corresponds to the first pin 2-1, a second electrode 4 corresponds to the second pin 2-2, an insulating strip 5 is arranged between the first electrode 3 and the second electrode 4, the insulating strip 5 is arranged in the middle, the first electrode 3 and the second electrode 4 are prevented from being mutually broken down to cause short circuit in the testing process, a testing circuit 6 is pre-embedded in a base 1, the first electrode 3 and the second electrode 4 are respectively connected with the testing circuit 6 through leads, one end of the testing circuit 6 is grounded, the other end of the testing circuit is electrically connected with a tester, and the tester is used for testing the junction-to-shell thermal resistance of a semiconductor chip device; one end of the sliding clamping device 7 is arranged in the first accommodating groove 1-1 and is arranged below the insulating strip 5, the insulating strip 5 can be made of transparent or semitransparent insulating rubber, the sliding clamping device 7 is connected with the first accommodating groove 1-1 in a sliding mode, the other end of the sliding clamping device 7 extends out of the outer end of the first accommodating groove 1-1 and extends towards the direction of the semiconductor chip to be tested, and when the pin of the semiconductor chip to be tested is completely attached to the electrode of the base 1, the extending end of the sliding clamping device 7 is attached to the side wall of the semiconductor chip to be tested.
Further, referring to fig. 2-3, a second receiving groove 8 is formed below the insulating strip 5 on the first receiving groove 1-1, and the sliding clamping device 7 is arranged in the second receiving groove 8. Wherein, the slide latch 7 includes: one end of the elastic part 7-1 is fixedly connected to the inner wall of the second accommodating groove 8, the inner wall of the second accommodating groove 8 is also provided with a sliding groove 8-1 relatively, and the sliding groove 8-1 is parallel to the elastic part 7-1; the two ends of the sliding block 7-2 are symmetrically provided with bulges 7-3, the bulges 7-3 are arranged in the sliding groove 8-1 and are used for sliding the sliding block 7-2, and the other end of the elastic piece 7-1 is fixedly connected with the sliding block 7-2; the push rod 7-4 is fixedly connected to the slide block 7-2 and is coaxially arranged with the elastic piece 7-1; the stop plate 7-5 is fixedly connected with the tail end of the push rod 7-4, and when the elastic piece 7-1 is positioned at the original position, the stop plate 7-5 is attached to the outer surface of the base 1. Wherein, the elastic member 7-1 may be a spring.
Further, referring to fig. 1 to 3, a dust cover 9 is further included, one end of the dust cover is hinged to the edge of the first accommodating groove 1-1, and when the dust cover 9 is closed, the first accommodating groove 1-1, the sliding clamping device 7 and the semiconductor chip to be tested are wrapped. Wherein, dust cover 9 is the L type, and when closing, dust cover 9 upper surface is parallel with base 1 upper surface and inside wall and the surface laminating of barrier plate 7-5.
Further, referring to fig. 4, the package testing device further includes a base wiring board 10, which is fixedly connected to an inner wall of the first accommodating groove 1-1 and grounded through a wire, and the base is provided with an antistatic layer through the base wiring board 10, so as to ensure that the semiconductor chip does not generate static electricity during the package testing process.
The utility model provides a semiconductor device test fixture, which changes the existing pressure type clamping mode into a lateral clamping mode by arranging a transverse slidable sliding clamping device, releases the pressure between a semiconductor electrode and an electrode of the test fixture, and ensures that the electrode of a semiconductor chip is not damaged due to clamping force; meanwhile, the existing semiconductor packaging test device is not provided with an anti-static device, and the semiconductor chip possibly generates static electricity in the packaging test stage, and the static electricity can damage the semiconductor when directly acting on the semiconductor chip device. The utility model is also provided with a dust cover, and because dustless operation needs to be ensured in the production process of the semiconductor chip, the dust cover avoids dust particles in a workshop from influencing the test process and prevents test failure.
The above disclosure is only for a few specific embodiments of the present invention, however, the present invention is not limited to the above embodiments, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (7)
1. A semiconductor device test fixture, comprising:
the testing device comprises a base (1), wherein a first accommodating groove (1-1) is formed in the edge of the upper surface of the base (1), and a semiconductor chip to be tested is placed in the first accommodating groove (1-1); the first accommodating groove (1-1) is symmetrically provided with a first electrode (3) and a second electrode (4) relative to one surface of a semiconductor pin (2) to be tested, and the pin (2) comprises: the testing device comprises a first pin (2-1) and a second pin (2-2), wherein a first electrode (3) corresponds to the first pin (2-1), a second electrode (4) corresponds to the second pin (2-2), an insulating strip (5) is arranged between the first electrode (3) and the second electrode (4) and used for preventing short circuit, a testing circuit (6) is pre-embedded in a base (1), the first electrode (3) and the second electrode (4) are respectively connected with the testing circuit (6) through leads, one end of the testing circuit (6) is grounded, and the other end of the testing circuit (6) is electrically connected with a tester;
one end of the sliding clamping device (7) is arranged in the first accommodating groove (1-1) and is arranged below the insulating strip (5), the sliding clamping device (7) is connected with the first accommodating groove (1-1) in a sliding mode, the other end of the sliding clamping device (7) extends out of the outer end of the first accommodating groove (1-1) and extends towards the direction of the semiconductor chip to be tested, and when the pin of the semiconductor chip to be tested is completely attached to the electrode of the base (1), the extending end of the sliding clamping device (7) is tightly attached to the side wall of the semiconductor chip to be tested.
2. The semiconductor device test fixture according to claim 1, wherein a second receiving groove (8) is formed below the insulating strip (5) on the first receiving groove (1-1), and the sliding clamping device (7) is disposed in the second receiving groove (8).
3. A semiconductor device test fixture according to claim 2, wherein the slide clamping means (7) comprises:
one end of the elastic piece (7-1) is fixedly connected to the inner wall of the second accommodating groove (8), the inner wall of the second accommodating groove (8) is also provided with a sliding groove (8-1) oppositely, and the sliding groove (8-1) is arranged in parallel with the elastic piece (7-1);
the two ends of the sliding block (7-2) are symmetrically provided with bulges (7-3), the bulges (7-3) are arranged in the sliding groove (8-1) and used for sliding the sliding block (7-2), and the other end of the elastic piece (7-1) is fixedly connected with the sliding block (7-2);
the push rod (7-4) is fixedly connected to the sliding block (7-2) and is coaxially arranged with the elastic piece (7-1);
the stop plate (7-5) is fixedly connected with the tail end of the push rod (7-4), and when the elastic piece (7-1) is located at the original position, the stop plate (7-5) is attached to the outer surface of the base (1).
4. A semiconductor device test fixture according to claim 3, wherein the elastic member (7-1) is a spring.
5. The semiconductor device testing jig as claimed in claim 4, further comprising a dust cover (9), one end of which is hinged to the edge of the first receiving groove (1-1), wherein when the dust cover (9) is closed, the dust cover wraps the first receiving groove (1-1), the sliding clamping device (7) and the semiconductor chip to be tested.
6. The semiconductor device test fixture of claim 5, wherein the dust cover (9) is L-shaped, and when closed, the upper surface of the dust cover (9) is parallel to the upper surface of the base (1) and the inner side wall of the dust cover is attached to the outer surface of the blocking plate (7-5).
7. A semiconductor device test jig according to claim 1, further comprising a base terminal plate (10) which is fixedly attached to an inner wall of the first housing groove (1-1) and is grounded through a wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121795074.0U CN215375528U (en) | 2021-08-03 | 2021-08-03 | Semiconductor device test fixture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121795074.0U CN215375528U (en) | 2021-08-03 | 2021-08-03 | Semiconductor device test fixture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215375528U true CN215375528U (en) | 2021-12-31 |
Family
ID=79614741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121795074.0U Active CN215375528U (en) | 2021-08-03 | 2021-08-03 | Semiconductor device test fixture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215375528U (en) |
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2021
- 2021-08-03 CN CN202121795074.0U patent/CN215375528U/en active Active
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