CN215263870U - Automatic testing arrangement of chip pin state - Google Patents
Automatic testing arrangement of chip pin state Download PDFInfo
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- CN215263870U CN215263870U CN202121572388.4U CN202121572388U CN215263870U CN 215263870 U CN215263870 U CN 215263870U CN 202121572388 U CN202121572388 U CN 202121572388U CN 215263870 U CN215263870 U CN 215263870U
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Abstract
The utility model discloses an automatic testing arrangement of chip pin state, including little the control unit, test instrument and little the variable voltage module of the control unit connection, the chip that awaits measuring is connected between variable voltage module and test instrument, and the device still includes by little the pin selection module and the signal selection module of the control unit control, pin selection module one end with the chip that awaits measuring connects, the other end with the signal selection module is connected, the signal selection module is connected with test instrument. The utility model discloses the state and the wave form of the pin of the chip that awaits measuring of high, with low costs, the test that can be high-efficient nimble shorten chip development cycle.
Description
Technical Field
The utility model relates to a chip test field, in particular to automatic testing arrangement of chip pin state.
Background
With the development of automation of the electronic industry, the demand of various industries on chips is increasing, the types of the chips are also increasing, and the functions are also more and more complex. The performance of the chip is increasing, the number of pins is increasing, and the test requirement for the chip is also increasing. In the past, chip pin state or waveform testing is mainly performed by a traditional manual operation instrument, and few advanced testing equipment is used.
The traditional manual test is time-consuming and labor-consuming and has poor reliability, once some test conditions (such as voltage and chip pull-up and pull-down states) are changed, manual repeated operation is needed, the reliability is poor, and the development period of the chip is prolonged.
SUMMERY OF THE UTILITY MODEL
Not enough to prior art, the utility model provides an automatic testing arrangement of chip pin state, the device degree of automation is high and the reliability is high.
The utility model discloses a following technical scheme realizes:
the device also comprises a pin selection module and a signal selection module which are controlled by the micro control unit, wherein one end of the pin selection module is connected with the chip to be tested, the other end of the pin selection module is connected with the signal selection module, and the signal selection module is connected with the test instrument.
Furthermore, the pin selection module comprises a plurality of pin selection switches, one end of each pin selection switch is connected with a pin of the chip to be tested, and the other end of each pin selection switch is connected with the signal selection module.
Furthermore, the signal selection module comprises a plurality of signal selection switches, the input common end of each signal selection switch is connected with the pin selection switch, and the output common end of each signal selection switch is connected with the test instrument.
Furthermore, the signal selection module further comprises a direct current power supply, a pull-up resistor and a pull-down resistor, wherein one end of the pull-up resistor is connected with the direct current power supply, the other end of the pull-up resistor is connected with one side of the signal selection switch, one end of the pull-down resistor is connected with the other side of the signal selection switch, and the other end of the pull-down resistor is grounded.
Furthermore, the device also comprises an upper computer connected with the micro control unit, and the upper computer is also connected with a test instrument.
Furthermore, the test instrument is connected with a power supply pin of the chip to be tested.
Furthermore, the variable voltage module is connected with a power supply pin of the chip to be tested.
Compared with the prior art, the utility model has the advantages of:
1. the pin selection module and the signal selection module are matched, so that the chip pins to be tested can be selected at will, the states of the pins can be measured by pulling up or pulling down according to the test requirements, the device is simple, and the cost is saved.
2. The test instrument is used to test the state or waveform of any pin, and multiple pins can be measured simultaneously and their waveforms integrated together for comparison.
Drawings
Fig. 1 is a block diagram of an apparatus for automatically testing a pin status of a chip according to an embodiment of the present invention;
fig. 2 is a schematic view of a test board according to an embodiment of the present invention.
1-an upper computer; 2-a micro control unit; 3-a variable voltage module; 4-a chip to be tested; 5-pin selection module, 50-pin selection switch; 6-a signal selection module, 60-a signal selection switch, 61-a direct current power supply, 62-a pull-up resistor and 63-a pull-down resistor; 7-test apparatus.
Detailed Description
The following non-limiting detailed description of the present invention is provided in connection with the preferred embodiments and accompanying drawings. In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.
As shown in fig. 1, the automatic testing apparatus for chip pin status according to an embodiment of the present invention includes an upper computer 1, a micro control unit 2, a variable voltage module 3, a pin selection module 5, a signal selection module 6, and a testing instrument 7; the chip 4 to be tested is connected between the variable voltage module 3 and the pin selection module 5, the micro control unit 2 is respectively connected with the upper computer 1, the variable voltage module 3, the pin selection module 5 and the signal selection module 6, the variable voltage module 3 is connected with the power supply pin of the chip 4 to be tested, the power supply pin of the chip 4 to be tested is also connected with the testing instrument 7, the pin selection module 5 is connected with the signal selection module 6, the signal selection module 6 is connected with the testing instrument 7, and the upper computer 1 is connected with the testing instrument 7. The firmware is downloaded into the micro control unit 2, the upper computer 1 controls the micro control unit 2 and the testing instrument 7 through a script program, the micro control unit 2 supplies power to a system through controlling the variable voltage module 3, meanwhile, the voltage of the variable voltage module 3 can be adjusted, pins of a chip 4 to be tested can be selected through the pin selection module 5, and signals of the pins can be selected to be subjected to pull-up detection or pull-down detection through the signal selection module 6.
As shown in fig. 2, the pin selection module 5 includes a plurality of pin selection switches 50, one end of each pin selection switch 50 is connected to a pin of the chip 4 to be tested, and the other end is connected to the signal selection module 6. The mcu 2 determines the signal of the desired measurement pin by controlling the closing of the pin selector switch 50 through a script program.
As shown in fig. 2, the signal selection module 6 includes a plurality of signal selection switches 60, a dc power supply 61, a pull-up resistor 62 and a pull-down resistor 63, the input common terminal of the signal selection switch 60 is connected to the pin selection switch 50, and the output common terminal is connected to the test instrument 7. One end of the pull-up resistor 62 is connected with the direct current power supply 61, the other end of the pull-up resistor 62 is connected with one side of the signal selection switch 60, one end of the pull-down resistor 63 is connected with the other side of the signal selection switch 60, and the other end of the pull-down resistor is grounded. When a signal of a certain pin of the chip 4 to be tested is transmitted to the signal selection switch 60, when both sides of the signal selection switch 60 are opened, the signal is pulled up to VCC through the pull-up resistor 62, and the test instrument 7 is connected to the test point, and then the test can be performed, otherwise, when both sides of the signal selection switch 60 are closed, the signal is pulled down to the ground through the pull-down resistor 63, and the test instrument 7 is connected to the test point, and then the test can be performed.
The device can be used for testing two conditions: see the following explanation of example one and example two for details.
The first embodiment is as follows:
as shown in fig. 1 and fig. 2, in this embodiment, the test instrument 7 selects an oscilloscope, the pull-up resistor 62 and the pull-down resistor 63 are both 4.7k ohms, the firmware is downloaded into the micro control unit 2, the test points 1, 2, 3 and 4 are connected to the oscilloscope, the pin selection switch 50 is controlled by a script program of the micro control unit 2, the chip pin to be tested is selected, the selection signal is pulled up to VCC by switching the signal selection switch 60, the oscilloscope is controlled by a script of the upper computer 1, and the rising edge of the VCC signal of the test point 1 is used as a trigger condition; the variable voltage module 3 is controlled to be powered on, the oscilloscope captures waveforms, the waveform chart and data are obtained through the script of the upper computer 1, the steps are repeated, signals of the test points 2, 3 and 4 can be respectively collected into the oscilloscope, whether the pin state is normal or not is analyzed, meanwhile, the upper computer 1 can also place waveforms of the test points collected by the oscilloscope into the same chart, and the working state of each pin can be contrasted clearly.
Example two:
as shown in fig. 1 and fig. 2, in this embodiment, the test instrument 7 selects an oscilloscope, the pull-up resistor 62 and the pull-down resistor 63 are both 4.7k ohms, the firmware is downloaded into the micro control unit 2, the test points 1, 2, 3 and 4 are connected to the oscilloscope, the micro control unit 2 controls the variable voltage module 3 to output a normal voltage VCC, the pin selection switch 50 is controlled by a script program of the micro control unit 2, the chip pin to be tested is selected, and the selection signal is pulled up to the VCC by the switching signal selection switch 60; the oscilloscope captures waveforms, obtains a waveform diagram and data through the script of the upper computer 1, stores the waveform diagram and the data into a table, can repeatedly acquire the waveforms and the data by the output voltage VCC + 10% and VCC-10% of the variable voltage module 3, and judges whether the timing diagram and the eye diagram of the pin are correct.
When the device is used, the micro control unit 2 is connected with the upper computer 1 through a serial port, a test point is connected onto a test instrument 7, the micro control unit 2 controls the variable voltage module 3, the pin selection module 50 and the signal selection switch 60, wherein the voltage of the variable voltage module 3 can be adjusted under the control of the micro control unit 2, the micro control unit 2 selects a pin needing to be tested through the control pin selection switch 50, and the control signal selection switch 60 selects to pull up or pull down a signal; however, if the pin is an output pin, and the power-on state is 1, the pull-up and pull-down results of the pin are all 1, and if the output pin state is 0, the signal pull-up and pull-down of the pin are all 0. The test instrument 7 can measure the state and timing diagram of the pins and can upload data and images to the upper computer 1. According to the invention, through ingenious hardware design and combination of the upper computer 1, the micro control unit 2 and the test instrument 7 control script, the state and the waveform of the chip pin can be tested simply, flexibly, efficiently and low in cost, so that the labor is greatly saved, and the chip development period is shortened.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (7)
1. The automatic testing device for the state of the chip pins comprises a micro control unit (2), a testing instrument (7) and a variable voltage module (3) connected with the micro control unit (2), wherein a chip (4) to be tested is connected between the variable voltage module (3) and the testing instrument (7), and is characterized by further comprising a pin selection module (5) and a signal selection module (6) which are controlled by the micro control unit (2), wherein one end of the pin selection module (5) is connected with the chip (4) to be tested, the other end of the pin selection module is connected with the signal selection module (6), and the signal selection module (6) is connected with the testing instrument (7).
2. The automatic chip pin status testing device according to claim 1, wherein the pin selection module (5) comprises a plurality of pin selection switches (50), one end of each pin selection switch (50) is connected with a pin of the chip (4) to be tested, and the other end of each pin selection switch is connected with the signal selection module (6).
3. The automatic testing device for the pin status of the chip according to claim 2, wherein the signal selection module (6) comprises a plurality of signal selection switches (60), the input common terminal of the signal selection switches (60) is connected with the pin selection switch (50), and the output common terminal is connected with the testing instrument (7).
4. The automatic chip pin status testing device according to claim 3, wherein the signal selection module (6) further comprises a DC power supply (61), a pull-up resistor (62) and a pull-down resistor (63), one end of the pull-up resistor (62) is connected to the DC power supply (61), the other end of the pull-up resistor is connected to one side of the signal selection switch (60), one end of the pull-down resistor (63) is connected to the other side of the signal selection switch (60), and the other end of the pull-down resistor is grounded.
5. The automatic testing device for the pin state of the chip according to claim 1, further comprising an upper computer (1) connected with the micro control unit (2), wherein the upper computer (1) is further connected with a testing instrument (7).
6. The automated testing device for the pin status of chips according to claim 1, characterized in that the testing instrument (7) is connected with the power supply pin of the chip (4) to be tested.
7. The automatic testing device for the pin status of the chip according to claim 1, wherein the variable voltage module (3) is connected with a power supply pin of the chip (4) to be tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121572388.4U CN215263870U (en) | 2021-07-12 | 2021-07-12 | Automatic testing arrangement of chip pin state |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121572388.4U CN215263870U (en) | 2021-07-12 | 2021-07-12 | Automatic testing arrangement of chip pin state |
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| CN215263870U true CN215263870U (en) | 2021-12-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115032520A (en) * | 2022-05-12 | 2022-09-09 | 西安电子科技大学 | Automatic remote measurement and control system for testing power management chip |
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2021
- 2021-07-12 CN CN202121572388.4U patent/CN215263870U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115032520A (en) * | 2022-05-12 | 2022-09-09 | 西安电子科技大学 | Automatic remote measurement and control system for testing power management chip |
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Address after: Room 201, building 4, No.78, Keling Road, high tech Zone, Suzhou City, Jiangsu Province Patentee after: Yutai Microelectronics Co.,Ltd. Address before: 215163 Room 201, building 4, 78 Keling Road, high tech Zone, Suzhou City, Jiangsu Province Patentee before: Suzhou Yutai Microelectronics Co.,Ltd. |
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