CN215070109U

CN215070109U - Chip cascade collection system suitable for many electricity cores

Info

Publication number: CN215070109U
Application number: CN202120714407.6U
Authority: CN
Inventors: 何浩辉
Original assignee: Jiangsu Boqiang New Energy Technology Co ltd
Current assignee: Shanghai Aodian New Energy Technology Co ltd
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2021-12-07
Anticipated expiration: 2031-04-08

Abstract

The utility model relates to a chip cascade collection system suitable for many electric cores, including cascaded two at least collection chips, cascaded first collection chip is connected with MCU, and all the other collection chips are connected with MCU through keeping apart the chip, connect and have the consumption compensating circuit that is used for offsetting other collection chip consumptions in the ground wire department of first collection chip at least. Compared with the prior art, the utility model has the advantages of the consumption is balanced, extension group battery life.

Description

Chip cascade collection system suitable for many electricity cores

Technical Field

The utility model belongs to the technical field of the lithium cell technique and specifically relates to a chip cascade collection system suitable for many electricity cores is related to.

Background

With the development of science and technology, lithium batteries gradually replace lead acid to be applied to the energy storage of electric power. Lithium cell group generally comprises many lithium cell series connection or parallelly connected, needs dedicated protection module to manage electric core, BMS for short. Currently, in the commercially available BMS, dedicated chips (hereinafter referred to as acquisition chips (AFEs)) are used for acquiring cell voltage, current and temperature in a battery pack, such as: LTC6803 by Linear, ML5238 by LAPIS, BQ76940 by TI, SH367309 by Miao et al. Due to AFE manufacturing, such chips generally only support management of 10-16 cell strings at most. In practical applications, there is a need for more than 16 strings of batteries to be used in series, and then a plurality of acquisition chips are required to be used in cascade, as shown in fig. 1.

And when a plurality of acquisition chips are used in a cascade mode, various problems exist. Use two chip cascades as the example, the operating mode between two chips can not be identical in the use, AFE1 is the main chip, gather including electric core voltage, the electric current, parameters such as temperature, AFE2 chip mainly gathers electric core voltage parameter, the different consumption that causes of operating mode is different, can not realize offsetting each other, and undulant great, actual measurement can reach 300 ~ 600 uA's current difference, can cause the voltage of the electric core of two AFE chip corresponding management to be different after using for a long time. As shown in fig. 1, the CELL voltages of CELL1 to CELL16 and CELL voltages of CELL17 to CELL32 have a large difference, which seriously affects the total discharge capacity of the battery, causing the problem of shortened service life, and at the same time, affecting the service life of the battery pack and increasing the management cost.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome the defect that above-mentioned prior art exists and provide a chip cascade collection system suitable for many electric cores, it is poor through reducing the consumption between each acquisition chip, guarantee group battery life.

The purpose of the utility model can be realized through the following technical scheme:

the utility model provides a chip cascade collection system suitable for many electricity cores, including cascaded two at least collection chips, cascaded first collection chip is connected with MCU, and all the other collection chips are connected with MCU through keeping apart the chip, connect and have the consumption compensating circuit that is used for offsetting other collection chip consumptions in the ground wire department of first collection chip at least.

Furthermore, the power consumption compensation circuit is connected between the ground wire of the corresponding acquisition chip and the last power-saving core connected with the acquisition chip.

Further, the power consumption compensation circuit comprises a semiconductor device, and the semiconductor device is respectively connected with the last cell, the ground and the compensation switch through a resistor.

Further, the semiconductor device comprises a triode, a MOS tube or an optical coupler.

Furthermore, the isolation chip is connected with an isolation power supply, and the isolation power supply is connected with a main power supply.

Further, the isolation chip and the isolation power supply are integrally packaged.

Further, only the first acquisition chip is provided with a charging and discharging MOS driving end used for generating a driving instruction.

Further, the MCU is connected with an MOS driving chip for generating a driving instruction.

Furthermore, the power supply end of the first acquisition chip is connected with a main power supply through a voltage reduction module, and the other acquisition chips are powered by the battery cores connected with the acquisition chips.

Further, the voltage reduction module comprises an LDO or a voltage stabilization diode.

Compared with the prior art, the utility model discloses following beneficial effect has:

1. the utility model discloses the problem that exists when can effectively solving current many collection chip cascade and use because the consumption is inconsistent and influence group battery life effectively reduces administrative cost.

2. The utility model has the advantages that the power consumption compensation circuit is connected between the last section of the electric core connected with the acquisition chip and the acquisition chip, and the power consumption compensation circuit offsets the power consumption generated by other acquisition chips, thereby achieving the purpose of constant current compensation, and even if each acquisition chip runs under different working conditions, the power consumption fluctuation is small; meanwhile, through the design of the power consumption compensation circuit, the difference influence of the AFE chip can be reduced, and the balance of each chip can be achieved to a greater extent.

3. The utility model discloses an keep apart the chip and supply power by solitary isolation power, keep apart the power and be connected with the main power supply, can make the undulant transfer of consumption that causes by the communication to total power supply loop on like this, let all electric cores undertake the same consumption, avoid producing the consumption fluctuation by a wide margin owing to keep apart the communication that the chip influences between the chip.

4. The utility model discloses by single acquisition chip or by the unified drive signal who produces the MOS pipe of MCU, with the combination fluctuation conversion that a plurality of driven are opened or are closed and produce single undulant, effectively reduce the differentiation influence to electric core.

5. The utility model discloses a first power supply end of gathering the chip passes through the step-down module to be connected with the mains, shifts the consumption fluctuation to always press up, can effectively reduce the differentiation influence to electric core, changes the power supply mode of differentiation into the mode of always pressing the power supply, makes all electric cores undertake the same consumption, improves because the improper battery pressure difference problem that brings of management chip use, prolongs the life of group battery.

Drawings

FIG. 1 is a schematic diagram of a prior art scenario of two chip cascade connection;

fig. 2 is a schematic diagram of a scenario in which two chips are cascaded in an embodiment of the present invention;

fig. 3 is a schematic diagram of a power consumption compensation circuit employed in the embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Aiming at the problems existing in the cascade use of a plurality of acquisition chips, the inventor of the application carries out a great deal of creative analysis and reasoning on possible influence factors. Referring to fig. 1, taking the use of two acquisition chips in cascade as an example, the following problems are mainly involved in influencing power consumption:

1. influence of communication in working condition. The communication isolation chip is related to factors such as power supply, communication speed and communication time difference between chips of the communication isolation chip. Due to the cascade reason, the ground wire of the AFE2 corresponds to the power supply of the AFE1, the zero potential is unequal, a communication isolation chip is needed during communication, and the AFE2 isolation power supply is provided by reducing the voltage between the CELLs 17 and CELL32 in the manners of LDO and the like. In addition, the influence of the communication speed, the communication time difference between chips and the like has larger power consumption fluctuation.

2. Influence of MOS drive. And the output state of the MOS tube of the AFE2 chip and the output state of the MOS tube of the AFE1 chip are subjected to logic AND processing and then drive the MOS tube, so that the MOS tube is switched on and off. Compared with AFE1, AFE2 consumes a relatively large amount of power due to its relatively high voltage. The AFE2 supply voltage also produces power consumption changes as the cell voltage decreases.

3. And powering the AFE chip. The power supply of the AFE1 chip is provided by CELL 1-CELL 16, and the power supply of the AFE2 chip is provided by CELL 17-CELL 32. Under different working conditions (such as communication time difference), power consumption fluctuation can be caused.

4. Differences in the AFE chip itself. The power consumption is poor due to the consistency of the chip.

The utility model provides a can solve above-mentioned technical problem's chip cascade collection system who is applicable to many electricity cores, including cascaded two at least collection chips, cascaded first collection chip is connected with MCU, and all the other collection chips are connected with MCU through keeping apart the chip. During the use, every gathers the electric core of chip correspondence connection settlement quantity, and quantity can be according to practical application adjustment. In the device, at least the ground wire of the first acquisition chip is connected with a power consumption compensation circuit for offsetting the power consumption of other acquisition chips. The power consumption compensation circuit is connected between the ground GND of the corresponding acquisition chip and the last power-saving core connected with the acquisition chip.

In other embodiments, a power consumption compensation circuit may be added to a plurality of acquisition chips according to the power consumption of each acquisition chip.

In one embodiment, the power consumption compensation circuit includes a semiconductor device, and the semiconductor device is connected to the last cell, the ground and the compensation switch through a resistor. The compensation switch uses an enable chip. The semiconductor device can be a triode, an MOS tube or an optical coupler and the like. The power consumption compensation circuit can be designed according to the parameters

In one embodiment, an isolated power supply is connected to the isolated chip. The isolated chip can be packaged with the isolated power supply integrally.

In one implementation mode, only the first acquisition chip is provided with a charging and discharging MOS driving end, the MCU acquires voltage signals of the other acquisition chips and then generates a first driving instruction in a fusion mode, the first driving instruction is transmitted to the first acquisition chip, and the first acquisition chip combines the first driving instruction with the voltage signals of the first acquisition chip to generate a second driving instruction which is sent out through the charging and discharging MOS driving end. In the implementation mode, the MOS tube is uniformly driven by the first acquisition chip, and single fluctuation is realized.

In another embodiment, the MCU is connected with an MOS driving chip, and the MCU collects voltage signals of all the collecting chips and then fuses the voltage signals to generate a driving instruction which is sent out by the MOS driving chip. In the embodiment, the MCU is used for driving the MOS tubes uniformly, so that single fluctuation is realized.

The power supply end of the first acquisition chip is connected with a main power supply through a voltage reduction module, and the other acquisition chips are powered by the battery cores connected with the acquisition chips. The voltage reduction module adopts LDO or a voltage stabilization diode and the like.

Example 1

The embodiment provides a chip cascade collection device suitable for many electricity cores, refer to fig. 2, the device includes two cascaded collection chips AFE1 and AFE2, AFE1 is connected with MCU, AFE2 is connected with MCU through isolation chip 10, isolation chip 10 is connected with isolation power supply 20, AFE1 has charge and discharge MOS drive end, after acquiring voltage signal of AFE2, MCU generates a first drive command, transmit to AFE1, AFE1 combines the first drive command with self voltage signal to generate a second drive command, send through charge and discharge MOS drive end. In this embodiment, the AFE1 and the AFE2 are respectively connected to 16 CELLs, which are CELL1 to CELL16 and CELL17 to CELL 32.

The power supply terminal of the AFE1 is connected to the total power VCC through the voltage dropping module 30, and the AFE2 is powered by the cell to which it is connected. The voltage reduction module adopts LDO or a voltage stabilization diode and the like.

When each acquisition chip is connected with multiple electric cores, a power consumption compensation circuit 40 for offsetting the power consumption of the acquisition chip is connected with the last electric core connected with the AFE1, namely the grounding wire of the CELL 16. In this embodiment, the power consumption compensation circuit is configured as shown in fig. 3, and includes a transistor Q1, and resistors R1, R2, and R3 respectively connected to the transistor Q1, where R1 is connected to a switch EN, R2 is grounded, and R3 is connected to a CELL16, where EN is a switch of the compensation circuit and can close compensation in a non-operating state; r2 is a key device, achieves the purpose of constant current compensation, and the value is debugged according to the actual circuit.

The communication method adopted in this embodiment is an I2C communication method. The communication interface according to the AFE is different, and may be a UART interface, an SPI interface, or the like.

Example 2

Referring to fig. 2, in the chip cascading collection device suitable for multiple electric cores provided in this embodiment, the MCU is connected to the MOS driver chip, and the MCU collects voltage signals of all the collection chips and then fuses to generate a driving command, which is sent out through the MOS driver chip. The rest is the same as example 1.

The foregoing has described in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be devised by those skilled in the art in light of the teachings of the present invention without undue experimentation. Therefore, the technical solutions that can be obtained by a person skilled in the art through logic analysis, reasoning or limited experiments based on the prior art according to the concepts of the present invention should be within the scope of protection defined by the claims.

Claims

1. The utility model provides a chip cascade collection system suitable for many electric cores, includes cascaded at least two collection chips, and cascaded first collection chip is connected with MCU, and all the other collection chips are connected with MCU through keeping apart the chip, its characterized in that, connect and be used for offsetting the consumption compensation circuit of other collection chip consumptions in the ground wire department of first collection chip at least.

2. The chip-level connection acquisition device applicable to multiple electric cores according to claim 1, wherein the power consumption compensation circuit is connected between a ground wire corresponding to the acquisition chip and a last electric core connected to the acquisition chip.

3. The chip-scale collection device suitable for multiple cells of claim 2, wherein the power consumption compensation circuit comprises a semiconductor device, and the semiconductor device is connected to the last cell, the ground and the compensation switch through a resistor respectively.

4. The chip-scale collection device suitable for multiple cells of claim 3, wherein the semiconductor device comprises a triode, a MOS transistor or an optocoupler.

5. The chip-level collection device suitable for multiple cells of claim 1, wherein the isolation chip is connected to an isolation power supply, and the isolation power supply is connected to a main power supply.

6. The chip-scale collection device suitable for multiple cells of claim 4, wherein the isolation chip and the isolation power supply are integrally packaged.

7. The chip-cascaded collection device suitable for multiple cells of claim 1 or 5, wherein only the first collection chip has a charge-discharge MOS driving end for generating a driving instruction.

8. The chip-cascaded collection device suitable for multiple electric cores of claim 1 or 5, wherein the MCU is connected with a MOS driving chip for generating driving instructions.

9. The chip-level collection device suitable for multiple cells according to claim 1 or 5, wherein a power supply terminal of the first collection chip is connected to a main power supply through a voltage reduction module, and the other collection chips are powered by the cells connected to the other collection chips.

10. The multi-cell chip-scale collection device of claim 9, wherein the voltage dropping module comprises an LDO or a zener diode.