CN113140814A

CN113140814A - Chip cascade collection system suitable for many electricity cores

Info

Publication number: CN113140814A
Application number: CN202110378469.9A
Authority: CN
Inventors: 何浩辉
Original assignee: Jiangsu Boqiang New Energy Technology Co ltd
Current assignee: Jiangsu Boqiang New Energy Technology Co ltd
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2021-07-20

Abstract

The invention relates to a chip cascade acquisition device suitable for multiple electric cores, which comprises at least two cascaded acquisition chips, wherein the first cascaded acquisition chip is connected with an MCU (micro control unit), the other acquisition chips are connected with the MCU through isolation chips, and a power consumption compensation circuit for offsetting the power consumption of the other acquisition chips is connected at least at the ground wire of the first acquisition chip. Compared with the prior art, the invention has the advantages of balanced power consumption, prolonged service life of the battery pack and the like.

Description

Chip cascade collection system suitable for many electricity cores

Technical Field

The invention relates to the technical field of lithium batteries, in particular to a chip-level connection acquisition device suitable for multiple electric cores.

Background

With the development of science and technology, lithium batteries gradually replace lead acid to be applied to the energy storage of electric power. Lithium cell group generally comprises many lithium cell series connection or parallelly connected, needs dedicated protection module to manage electric core, BMS for short. Currently, in the commercially available BMS, dedicated chips (hereinafter referred to as acquisition chips (AFEs)) are used for acquiring cell voltage, current and temperature in a battery pack, such as: LTC6803 by Linear, ML5238 by LAPIS, BQ76940 by TI, SH367309 by Miao et al. Due to AFE manufacturing, such chips generally only support management of 10-16 cell strings at most. In practical applications, there is a need for more than 16 strings of batteries to be used in series, and then a plurality of acquisition chips are required to be used in cascade, as shown in fig. 1.

And when a plurality of acquisition chips are used in a cascade mode, various problems exist. Use two chip cascades as the example, the operating mode between two chips can not be identical in the use, AFE1 is the main chip, gather including electric core voltage, the electric current, parameters such as temperature, AFE2 chip mainly gathers electric core voltage parameter, the different consumption that causes of operating mode is different, can not realize offsetting each other, and undulant great, actual measurement can reach 300 ~ 600 uA's current difference, can cause the voltage of the electric core of two AFE chip corresponding management to be different after using for a long time. As shown in fig. 1, the CELL voltages of CELL1 to CELL16 and CELL voltages of CELL17 to CELL32 have a large difference, which seriously affects the total discharge capacity of the battery, causing the problem of shortened service life, and at the same time, affecting the service life of the battery pack and increasing the management cost.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a chip-level collection device suitable for multiple electric cores, and the service life of a battery pack is ensured by reducing the power consumption difference among the collection chips.

The purpose of the invention can be realized by the following technical scheme:

the invention provides a chip cascade acquisition device suitable for multiple electric cores, which comprises at least two cascaded acquisition chips, wherein the first cascaded acquisition chip is connected with an MCU (micro control unit), the other acquisition chips are connected with the MCU through isolation chips, and a power consumption compensation circuit for offsetting the power consumption of the other acquisition chips is connected at least at the ground wire of the first acquisition chip.

Furthermore, the power consumption compensation circuit is connected between the ground wire of the corresponding acquisition chip and the last power-saving core connected with the acquisition chip.

Further, the power consumption compensation circuit comprises a semiconductor device, and the semiconductor device is respectively connected with the last cell, the ground and the compensation switch through a resistor.

Further, the semiconductor device comprises a triode, a MOS tube or an optical coupler.

Furthermore, the isolation chip is connected with an isolation power supply, and the isolation power supply is connected with a main power supply.

Further, the isolation chip and the isolation power supply are integrally packaged.

Furthermore, the first acquisition chip is provided with a charging and discharging MOS driving end, the MCU acquires voltage signals of the other acquisition chips and then generates a first driving instruction in a fusion mode, the first driving instruction is transmitted to the first acquisition chip, and the first acquisition chip combines the first driving instruction with self voltage signals to generate a second driving instruction which is sent out through the charging and discharging MOS driving end.

Furthermore, the MCU is connected with an MOS driving chip, the MCU collects voltage signals of all the collecting chips and then fuses the voltage signals to generate a driving instruction, and the driving instruction is sent out through the MOS driving chip.

Furthermore, the power supply end of the first acquisition chip is connected with a main power supply through a voltage reduction module, and the other acquisition chips are powered by the battery cores connected with the acquisition chips.

Further, the voltage reduction module comprises an LDO or a voltage stabilization diode.

Compared with the prior art, the invention has the following beneficial effects:

1. the invention can effectively solve the problem that the service life of the battery pack is influenced due to inconsistent power consumption when the existing multi-acquisition chip is used in a cascade mode, and effectively reduces the management cost.

2. According to the invention, the power consumption compensation circuit is connected between the last section of the battery cell connected with the acquisition chip and the acquisition chip, and the power consumption compensation circuit is offset with the power consumption generated by other acquisition chips, so that the purpose of constant current compensation is achieved, and even if each acquisition chip operates under different working conditions, the power consumption fluctuation is small; meanwhile, through the design of the power consumption compensation circuit, the difference influence of the AFE chip can be reduced, and the balance of each chip can be achieved to a greater extent.

3. The isolation chip is powered by an independent isolation power supply, and the isolation power supply is connected with the main power supply, so that power consumption fluctuation caused by communication can be transferred to the main power supply loop, all the battery cores bear the same power consumption, and the phenomenon that the isolation chip influences communication among the chips to generate large-amplitude power consumption fluctuation is avoided.

4. According to the invention, the single acquisition chip or the MCU generates drive signals to the MOS tube in a unified manner, and the combined fluctuation generated by the on or off of a plurality of drives is converted into single fluctuation, so that the differential influence on the electric core is effectively reduced.

5. The power supply end of the first acquisition chip is connected with the main power supply through the voltage reduction module, power consumption fluctuation is transferred to the total voltage, differential influence on the battery cells can be effectively reduced, the differentiated power supply mode is changed into the total voltage power supply mode, all the battery cells bear the same power consumption, the problem of battery differential pressure caused by improper application of the management chip is solved, and the service life of the battery pack is prolonged.

Drawings

FIG. 1 is a schematic diagram of a prior art scenario of two chip cascade connection;

FIG. 2 is a schematic diagram of a scenario of cascade connection of two chips according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a power consumption compensation circuit employed in the embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Aiming at the problems existing in the cascade use of a plurality of acquisition chips, the inventor of the application carries out a great deal of creative analysis and reasoning on possible influence factors. Referring to fig. 1, taking the use of two acquisition chips in cascade as an example, the following problems are mainly involved in influencing power consumption:

1. influence of communication in working condition. The communication isolation chip is related to factors such as power supply, communication speed and communication time difference between chips of the communication isolation chip. Due to the cascade reason, the ground wire of the AFE2 corresponds to the power supply of the AFE1, the zero potential is unequal, a communication isolation chip is needed during communication, and the AFE2 isolation power supply is provided by reducing the voltage between the CELLs 17 and CELL32 in the manners of LDO and the like. In addition, the influence of the communication speed, the communication time difference between chips and the like has larger power consumption fluctuation.

2. Influence of MOS drive. And the output state of the MOS tube of the AFE2 chip and the output state of the MOS tube of the AFE1 chip are subjected to logic AND processing and then drive the MOS tube, so that the MOS tube is switched on and off. Compared with AFE1, AFE2 consumes a relatively large amount of power due to its relatively high voltage. The AFE2 supply voltage also produces power consumption changes as the cell voltage decreases.

3. And powering the AFE chip. The power supply of the AFE1 chip is provided by CELL 1-CELL 16, and the power supply of the AFE2 chip is provided by CELL 17-CELL 32. Under different working conditions (such as communication time difference), power consumption fluctuation can be caused.

4. Differences in the AFE chip itself. The power consumption is poor due to the consistency of the chip.

The invention provides a chip cascade collection device suitable for multiple cells, which can solve the technical problems and comprises at least two cascaded collection chips, wherein the first cascaded collection chip is connected with an MCU, and the other collection chips are connected with the MCU through isolation chips. During the use, every gathers the electric core of chip correspondence connection settlement quantity, and quantity can be according to practical application adjustment. In the device, at least the ground wire of the first acquisition chip is connected with a power consumption compensation circuit for offsetting the power consumption of other acquisition chips. The power consumption compensation circuit is connected between the ground GND of the corresponding acquisition chip and the last power-saving core connected with the acquisition chip.

In other embodiments, a power consumption compensation circuit may be added to a plurality of acquisition chips according to the power consumption of each acquisition chip.

In one embodiment, the power consumption compensation circuit includes a semiconductor device, and the semiconductor device is connected to the last cell, the ground and the compensation switch through a resistor. The compensation switch uses an enable chip. The semiconductor device can be a triode, an MOS tube or an optical coupler and the like. The power consumption compensation circuit can be designed according to the parameters

In one embodiment, an isolated power supply is connected to the isolated chip. The isolated chip can be packaged with the isolated power supply integrally.

In one implementation mode, the first acquisition chip is provided with a charging and discharging MOS driving end, the MCU acquires voltage signals of the other acquisition chips and then generates a first driving instruction in a fusion mode, the first driving instruction is transmitted to the first acquisition chip, and the first acquisition chip combines the first driving instruction with the voltage signals of the first acquisition chip to generate a second driving instruction which is sent out through the charging and discharging MOS driving end. In the implementation mode, the MOS tube is uniformly driven by the first acquisition chip, and single fluctuation is realized.

In another embodiment, the MCU is connected with an MOS driving chip, and the MCU collects voltage signals of all the collecting chips and then fuses the voltage signals to generate a driving instruction which is sent out by the MOS driving chip. In the embodiment, the MCU is used for driving the MOS tubes uniformly, so that single fluctuation is realized.

The power supply end of the first acquisition chip is connected with a main power supply through a voltage reduction module, and the other acquisition chips are powered by the battery cores connected with the acquisition chips. The voltage reduction module adopts LDO or a voltage stabilization diode and the like.

Example 1

The embodiment provides a chip cascade collection device suitable for many electricity cores, refer to fig. 2, the device includes two cascaded collection chips AFE1 and AFE2, AFE1 is connected with MCU, AFE2 is connected with MCU through isolation chip 10, isolation chip 10 is connected with isolation power supply 20, AFE1 has charge and discharge MOS drive end, after acquiring voltage signal of AFE2, MCU generates a first drive command, transmit to AFE1, AFE1 combines the first drive command with self voltage signal to generate a second drive command, send through charge and discharge MOS drive end. In this embodiment, the AFE1 and the AFE2 are respectively connected to 16 CELLs, which are CELL1 to CELL16 and CELL17 to CELL 32.

The power supply terminal of the AFE1 is connected to the total power VCC through the voltage dropping module 30, and the AFE2 is powered by the cell to which it is connected. The voltage reduction module adopts LDO or a voltage stabilization diode and the like.

When each acquisition chip is connected with multiple electric cores, a power consumption compensation circuit 40 for offsetting the power consumption of the acquisition chip is connected with the last electric core connected with the AFE1, namely the grounding wire of the CELL 16. In this embodiment, the power consumption compensation circuit is configured as shown in fig. 3, and includes a transistor Q1, and resistors R1, R2, and R3 respectively connected to the transistor Q1, where R1 is connected to a switch EN, R2 is grounded, and R3 is connected to a CELL16, where EN is a switch of the compensation circuit and can close compensation in a non-operating state; r2 is a key device, achieves the purpose of constant current compensation, and the value is debugged according to the actual circuit.

The communication method adopted in this embodiment is an I2C communication method. The communication interface according to the AFE is different, and may be a UART interface, an SPI interface, or the like.

Example 2

Referring to fig. 2, in the chip cascading collection device suitable for multiple electric cores provided in this embodiment, the MCU is connected to the MOS driver chip, and the MCU collects voltage signals of all the collection chips and then fuses to generate a driving command, which is sent out through the MOS driver chip. The rest is the same as example 1.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. The utility model provides a chip cascade collection system suitable for many electric cores, includes cascaded at least two collection chips, and cascaded first collection chip is connected with MCU, and all the other collection chips are connected with MCU through keeping apart the chip, its characterized in that, connect and be used for offsetting the consumption compensation circuit of other collection chip consumptions in the ground wire department of first collection chip at least.

2. The chip-level connection acquisition device applicable to multiple electric cores according to claim 1, wherein the power consumption compensation circuit is connected between a ground wire corresponding to the acquisition chip and a last electric core connected to the acquisition chip.

3. The chip-scale collection device suitable for multiple cells of claim 2, wherein the power consumption compensation circuit comprises a semiconductor device, and the semiconductor device is connected to the last cell, the ground and the compensation switch through a resistor respectively.

4. The chip-scale collection device suitable for multiple cells of claim 3, wherein the semiconductor device comprises a triode, a MOS transistor or an optocoupler.

5. The chip-level collection device suitable for multiple cells of claim 1, wherein the isolation chip is connected to an isolation power supply, and the isolation power supply is connected to a main power supply.

6. The chip-scale collection device suitable for multiple cells of claim 4, wherein the isolation chip and the isolation power supply are integrally packaged.

7. The chip-level collection device suitable for multiple electric cores of claim 1 or 5, wherein the first collection chip has a charge-discharge MOS drive end, the MCU collects voltage signals of the other collection chips and then fuses the voltage signals to generate a first driving instruction to be transmitted to the first collection chip, and the first collection chip combines the first driving instruction with a self voltage signal to generate a second driving instruction to be sent out through the charge-discharge MOS drive end.

8. The chip cascading collection device suitable for the multiple electric cores of claim 1 or 5, wherein the MCU is connected with an MOS driving chip, and the MCU collects voltage signals of all the collection chips and then fuses the voltage signals to generate a driving instruction which is sent out through the MOS driving chip.

9. The chip-level collection device suitable for multiple cells according to claim 1 or 5, wherein a power supply terminal of the first collection chip is connected to a main power supply through a voltage reduction module, and the other collection chips are powered by the cells connected to the other collection chips.

10. The multi-cell chip-scale collection device of claim 9, wherein the voltage reduction module comprises an LDO or a zener diode.