CN215067081U

CN215067081U - Testing device

Info

Publication number: CN215067081U
Application number: CN202023166861.7U
Authority: CN
Inventors: 赖俊; 江凤丹; 唐梅花
Original assignee: China Display Optoelectronics Technology Huizhou Co Ltd
Current assignee: China Display Optoelectronics Technology Huizhou Co Ltd
Priority date: 2020-12-24
Filing date: 2020-12-24
Publication date: 2021-12-07
Anticipated expiration: 2030-12-24

Abstract

A testing device comprises a testing board, a first frequency testing device and a second frequency testing device. The first interface of the test board is connected with the first end of the circuit board, and the second interface of the test board is connected with the second end of the circuit board. The first interface and the second interface each include a plurality of connection terminals. A first conductive path is arranged between the connecting ends of the first interface, and a second conductive path is arranged between the connecting ends of the second interface. The first conductive path and the second conductive path enable the circuit board connected to the test board to form a first conductive loop and a second conductive loop, and two adjacent interfaces in the circuit board are located on different conductive loops. The first frequency testing device is connected to one end of the first conductive loop, and the other end of the first conductive loop is connected with the first testing signal. The second frequency testing device is connected to one end of the second conductive loop, and the other end of the second conductive loop is connected with the second testing signal.

Description

Testing device

Technical Field

The utility model relates to an electronic circuit technical field especially relates to a testing arrangement.

Background

With the intense competition of the market, the current electronic consumer products are always developed towards the trend of high screen occupation ratio, lightness and thinness without reducing endurance so as to ensure the advantages of the products. This development has led to the related designs having to be compact to avoid more space, so the main FPC (Flexible Printed Circuit) connected to the display screen now plays a role of transmitting not only display signals but also other non-display signals on the main board. When the FPC connector has little tin, continuous tin or the FPC circuit is opened and short-circuited, the circuit is abnormal, so that the functional failure phenomenon of the product is caused. The traditional method for testing the FPC is to serially connect LED lamps in each circuit of the FPC to detect the open circuit or short circuit condition, and when the number of circuits of the FPC is large, the number of consumed LED lamps is increased. And the LED lamp used is easy to damage and explode, which causes material waste.

SUMMERY OF THE UTILITY MODEL

To the problem that exists among the prior art, the embodiment of the utility model provides a testing arrangement to solve LED lamp and consume more in traditional FPC test method, lead to the higher problem of cost.

A testing device comprises a testing board, a first frequency testing device and a second frequency testing device. The test board includes a first interface and a second interface. The first interface is used for connecting a first end of the circuit board, and the second interface is used for connecting a second end of the circuit board. The first interface comprises a plurality of connection ends A1, A2, … … and An, wherein n is a positive integer. The second interface comprises a plurality of connection terminals B1, B2, … …, Bn. A first conductive path is arranged between the connection ends A1, A2, … … and An of the first interface. And a second conductive path is arranged between the connection ends B1, B2, … … and Bn of the second interface. The first conductive path and the second conductive path are used for enabling a circuit board connected to the test board to form a first conductive loop and a second conductive loop, and two adjacent interfaces in the circuit board are located on different conductive loops. The first frequency testing device is connected to one end of the first conductive loop, and the other end of the first conductive loop is connected with a first testing signal. The second frequency testing device is connected to one end of the second conductive loop, and the other end of the second conductive loop is connected with a second testing signal.

Optionally, when n/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-3) is electrically connected with A (n-1); the second conductive path is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-2) is electrically connected with Bn; when n/2 is an odd number, the first conductive path is connected in the following way: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-3) is electrically connected with B (n-1); when (n-1)/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-4) is electrically connected with A (n-2); the second conductive path is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-2) is electrically connected with Bn; when (n-1)/2 is an odd number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b2 and B4 are electrically connected, B3 and B5 are electrically connected, … …, and B (n-4) and B (n-2) are electrically connected.

Optionally, when n/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-4) is electrically connected with B (n-2); when n/2 is an odd number, the first conductive path is connected in the following way: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-4) is electrically connected with A (n-2); the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-2) is electrically connected with Bn; when (n-1)/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-3) is electrically connected with A (n-1); the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-2) is electrically connected with Bn; when (n-1)/2 is an odd number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b3 and B5 are electrically connected, B4 and B6 are electrically connected, … …, and B (n-3) and B (n-1) are electrically connected.

Optionally, the first test signal is a PWM signal.

Optionally, the frequency of the PWM signal is 1000 HZ.

Optionally, the second test signal is a TE signal.

Optionally, the frequency of the TE signal is 60 HZ.

Optionally, the first frequency testing device and/or the second frequency testing device is a digital frequency meter.

Optionally, the first frequency testing device includes a first display device and a first frequency setting device, the first frequency setting device is configured to set a first frequency, and the first display device is configured to lock the output screen when the frequency of the first test signal detected by the first frequency testing device is inconsistent with the first frequency.

Optionally, the second frequency testing device includes a second display device and a second frequency setting device, the second frequency setting device is configured to set a second frequency, and the second display device is configured to lock the output screen when the frequency of the second test signal detected by the second frequency testing device is inconsistent with the second frequency.

The utility model provides an among the testing arrangement, make the circuit board form first conductive loop and second conductive loop through surveying test panel, and two adjacent interfaces are located different conductive loops in the circuit board. At this time, the information of the open circuit or the short circuit in the circuit board can be obtained by detecting the first conductive loop and the second conductive loop. The testing device has the following beneficial effects:

1. the test board is simple in structure, can adapt to open and short circuit tests of circuit boards containing more circuits according to actual requirements, and has the characteristics of simplicity, convenience and extremely high compatibility.

2. The first frequency testing device and the second frequency testing device are used for testing a first conductive loop and a second conductive loop formed on the circuit board, the circuit adopts a zero-device scheme, and an LED or a resistor device is not used, so that the testing cost is greatly optimized, and the reliability risk of device mounting is directly avoided.

3. In one embodiment, the first test signal is set to a PWM signal; setting the second test signal as a TE signal. Because the PWM signal and the TE signal are tested in the production process, the testing device for the PWM signal and the TE signal can be used for simultaneously carrying out open-short circuit testing on the circuit board, extra testing stations and extra testing items are not required to be added, the testing time of a production line is greatly shortened, and the output efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a system block diagram of a testing apparatus according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of the wiring board in fig. 1.

Fig. 3 is a schematic structural view of the test board in fig. 1.

Fig. 4 is a circuit diagram of the test board and the circuit board in fig. 3 after being connected.

FIG. 5 is a schematic structural diagram of another embodiment of the test board in FIG. 1.

Fig. 6 is a circuit diagram of the test board and the circuit board in fig. 5 after being connected.

Fig. 7 is a schematic diagram of signals received by the first frequency testing device and the second frequency testing device when the circuit board in fig. 1 is normal.

Fig. 8 is a schematic diagram of signals received by the first frequency testing device and the second frequency testing device when the circuit board in fig. 1 is short-circuited.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

Referring to fig. 1, an embodiment of the present invention provides a testing apparatus 100 for performing an open/short circuit test on a circuit board 200. In this embodiment, the circuit board 200 is an FPC circuit board. The testing device 100 includes a testing board 110, a first frequency testing device 120 and a second frequency testing device 130. The test board 110 includes a first interface and a second interface. The first interface is used for connecting a first end of the circuit board 200, and the second interface is used for connecting a second end of the circuit board 200. The test board 110 and the circuit board 200 connected to the test board 110 form a first conductive loop 140 and a second conductive loop 150, and two adjacent interfaces in the circuit board 200 are located on different conductive loops. The first frequency testing device 120 is connected to one end of the first conductive loop 140, and the other end of the first conductive loop 140 is connected to a first test signal 160. The second frequency testing device 130 is connected to one end of the second conductive loop 150, and the other end of the second conductive loop 150 is connected to a second test signal 170.

Referring to fig. 2, the circuit board 200 includes a first end and a second end. The first end of the wiring board 200 includes a plurality of connection terminals C1, C2, … …, Cn, where n is a positive integer. The second end of the circuit board 200 includes a plurality of connection terminals D1, D2, … …, Dn, wherein C1 and D1 form an electrical connection line, C2 and D2 form an electrical connection line, and so on, Cn and Dn form an electrical connection line. In the application process, the electrical connection lines between the first end and the second end of the circuit board 200 must be connected one by one and cannot be short-circuited to each other, so as to function as a transmission line. The circuit board 200 is used in an LCM module and used for transmitting fingerprint identification signals such as SPI _ MI, SPI _ MO and the like. In this embodiment, both the first and the second end of the wiring board 200 comprise 9 connection terminals, i.e. it comprises 9 electrical connection lines. The testing device 100 needs to perform an open-short test on the circuit board 200. The circuit board 200 may also perform the function of transmitting display signals or perform the transmission of other non-display signals on the motherboard as required. Specifically, the connection terminals C1, C2, … …, Cn and the connection terminals D1, D2, … …, Dn are pins or fingers disposed on the circuit board 200. The connection terminals C1, C2, … …, Cn may all be disposed on the same face of the wiring board 200 to form a single-layer structure. It is to be understood that the connection terminals C1, C2, … …, Cn may also be arranged in two rows in the thickness direction of the wiring board 200 to form a double-layered structure. It will be appreciated that the connection ends D1, D2, … …, Dn may be similarly arranged.

Referring to fig. 3 to 4, the first interface 111 of the test board 110 includes a plurality of connection terminals a1, a2, … …, An, where n is a positive integer. The second interface 112 of the test board 110 includes a plurality of connection terminals B1, B2, … …, Bn. The first interface 111 has a first conductive path 113 between the connection terminals a1, a2, … …, An. A second conductive path 114 is provided between the connection terminals B1, B2, … …, Bn of the second interface 112. The first conductive path 113 and the second conductive path 114 are used to form a first conductive loop 140 and a second conductive loop 150 with a circuit board 200 connected to the test board 110, and two adjacent interfaces in the circuit board 200 are located on different conductive loops. In this embodiment, the number of the connecting terminals of the test board 110 is the same as that of the connecting terminals of the circuit board 200, and is 9. The first end and the second end of the circuit board 200 are male sockets, and the first interface 111 and the second interface 112 of the test board 110 are female sockets, so that the circuit board 200 can be clamped on the test board 110. In this embodiment, the first end of the circuit board 200 is plugged into the first interface 111 of the test board 110, such that C1 is electrically connected to a1, C2 is electrically connected to a2, … …, Cn is electrically connected to An; the second end of the circuit board 200 is plugged into the second interface 112 of the test board 110, such that D1 is electrically connected to B1, D2 is electrically connected to B2, and … …, Dn and Bn are electrically connected.

In order to make the first conductive path 113 and the second conductive path 114 and the circuit board 200 connected to the test board 110 form the first conductive loop 140 and the second conductive loop 150, and two adjacent interfaces in the circuit board 200 are located on different conductive loops, the connection manner of the first conductive path 113 and the second conductive path 114 may be:

when n is 4, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3; the second conductive path 114 is connected in the following manner: b2 is electrically connected to B4. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3; the second conductive loop 150 formed is: A2-B2-B4-A4.

When n is 5, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3; the second conductive path 114 is connected in the following manner: b2 is electrically connected to B4, and B3 is electrically connected to B5. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5; the second conductive loop 150 formed is: A2-B2-B4-A4.

When n is 6, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6; the second conductive path 114 is connected in the following manner: b2 is electrically connected to B4, and B3 is electrically connected to B5. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5; the second conductive loop 150 formed is: A2-B2-B4-A4-A6-B6.

When n is 7, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, and A5 is electrically connected with A7; the second conductive path 114 is connected in the following manner: b2 is electrically connected to B4, and B3 is electrically connected to B5. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5-A7-B7; the second conductive loop 150 formed is: A2-B2-B4-A4-A6-B6.

When n is 8, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, and A5 is electrically connected with A7; the second conductive path 114 is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, and B6 is electrically connected with B8. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5-A7-B7; the second conductive loop 150 formed is: A2-B2-B4-A4-A6-B6-B8-A8.

When n is 9, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, and A5 is electrically connected with A7; the second conductive path 114 is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, B6 is electrically connected with B8, and B7 is electrically connected with B9. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5-A7-B7-B9-A9; the second conductive loop 150 formed is: A2-B2-B4-A4-A6-B6-B8-A8.

And so on … ….

In this embodiment, taking n-9, a schematic structural diagram of the first conductive path 113 and the second conductive path 114 is shown in fig. 3. The schematic circuit diagram formed by the test board 110 and the circuit board 200 is shown in fig. 4. It can be seen from this that:

when n/2 is an even number, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-3) is electrically connected with A (n-1); the second conductive path 114 is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-2) is electrically connected with Bn;

when n/2 is an odd number, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-2) is electrically connected with An; the second conductive path 114 is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-3) is electrically connected with B (n-1);

when (n-1)/2 is an even number, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-4) is electrically connected with A (n-2); the second conductive path 114 is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-2) is electrically connected with Bn;

when (n-1)/2 is an odd number, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-2) is electrically connected with An; the second conductive path 114 is connected in the following manner: b2 and B4 are electrically connected, B3 and B5 are electrically connected, … …, and B (n-4) and B (n-2) are electrically connected.

As shown in fig. 4, the first conductive path 113 and the second conductive path 114 are disposed in such a way that the circuit board 200 connected to the test board 110 forms a first conductive loop 140 and a second conductive loop 150, and two adjacent interfaces in the circuit board 200 are located on different conductive loops. The first conductive loop 140 and the second conductive loop 150 are formed to test the wiring board 200 for an open defect. When any conductive path in the circuit board 200 is broken, the conductive loop where it is located is broken, and the first frequency testing device 120 cannot receive the first test signal 160, or the second frequency testing device 130 cannot receive the second test signal 170. The purpose of having two adjacent interfaces in the wiring board 200 on different conductive loops is to test the wiring board 200 for short defects. Since the short-circuit defect of the circuit board 200 generally occurs between adjacent conductive paths in the circuit board 200, when the short-circuit defect occurs in the adjacent conductive paths of the circuit board 200, crosstalk occurs between the first test signal 160 and the second test signal 170, so that the signals received by the first frequency testing device 120 and the second frequency testing device 130 are different from normal signals. Therefore, whether the wiring board 200 is normal or abnormal, which is an open defect or a short defect, can be determined by the detection results of the first frequency testing device 120 and the second frequency testing device 130.

It is to be understood that the arrangement of the first conductive path 113 and the second conductive path 114 is not limited to the above-described embodiment. Referring to fig. 5 to 6, the connection manner of the first conductive path 113 and the second conductive path 114 may also be:

when n is 4, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A2 is electrically connected with A4; the second conductive path 114 is connected in the following manner: B1-B4 are left empty. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3; the second conductive loop 150 formed is: B2-A2-A4-B4.

When n is 5, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A2 is electrically connected with A4; the second conductive path 114 is connected in the following manner: b3 is electrically connected to B5. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5; the second conductive loop 150 formed is: B2-A2-A4-B4.

When n is 6, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A2 is electrically connected with A4; the second conductive path 114 is connected in the following manner: b3 is electrically connected to B5, and B4 is electrically connected to B6. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5; the second conductive loop 150 formed is: B2-A2-A4-B4-B6-A6.

When n is 7, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A2 is electrically connected with A4, and A5 is electrically connected with A7; the second conductive path 114 is connected in the following manner: b3 is electrically connected to B5, and B4 is electrically connected to B6. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5-A7-B7; the second conductive loop 150 formed is: B2-A2-A4-B4-B6-A6.

When n is 8, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, A5 is electrically connected with A7, and A6 is electrically connected with A8; the second conductive path 114 is connected in the following manner: b3 is electrically connected to B5, and B4 is electrically connected to B6. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5-A7-B7; the second conductive loop 150 formed is: B2-A2-A4-B4-B6-A6-A8-B8.

When n is 9, the first conductive path 113 is connected in the following manner: a1 is electrically connected with A3, A4 is electrically connected with A6, A5 is electrically connected with A7, and A6 is electrically connected with A8; the second conductive path 114 is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, and B7 is electrically connected with B9. At this time, when the circuit board 200 is plugged onto the test board 110, the first conductive loop 140 is formed as follows: B1-A1-A3-B3-B5-A5-A7-B7-B9-A9; the second conductive loop 150 formed is: A2-B2-B4-A4-A6-B6-B8-A8.

And so on … ….

In this embodiment, taking n-9, a schematic structural diagram of the first conductive path 113 and the second conductive path 114 is shown in fig. 5. The schematic circuit diagram formed by the test board 110 and the circuit board 200 is shown in fig. 6. It can be seen from this that:

when n/2 is even number, the connection mode of the first conductive path is as follows: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-4) is electrically connected with B (n-2);

when n/2 is an odd number, the first conductive path is connected in the following way: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-4) is electrically connected with A (n-2); the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-2) is electrically connected with Bn;

when (n-1)/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-3) is electrically connected with A (n-1); the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-2) is electrically connected with Bn;

when (n-1)/2 is an odd number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b3 and B5 are electrically connected, B4 and B6 are electrically connected, … …, and B (n-3) and B (n-1) are electrically connected.

The first conductive path 113 and the second conductive path 114 are also arranged in such a way that the circuit board 200 connected to the test board 110 forms a first conductive loop 140 and a second conductive loop 150, and two adjacent interfaces in the circuit board 200 are located on different conductive loops.

It is understood that the arrangement of the first conductive path 113 and the second conductive path 114 is not limited to the above embodiments, and it is sufficient that the circuit board 200 connected to the test board 110 forms the first conductive loop 140 and the second conductive loop 150, and two adjacent interfaces in the circuit board 200 are located on different conductive loops.

In this embodiment, the first frequency testing device 120 and/or the second frequency testing device 130 are/is a digital frequency meter. The first test signal is a PWM signal. The PWM signal is a pulse width modulation signal in the display module, and the signal, energy change and the like can be adjusted by adjusting the change of the duty ratio. The PWM signal is commonly used for the backlight to control the LED output of the backlight. The frequency of the PWM signal can be set directly by the IC register. In this embodiment, the frequency of the PWM signal is 1000 HZ. The second test signal is a TE signal. The TE signal is a synchronization signal output from the IC for avoiding frame division during data transmission. The frequency of the TE signal may be set by the rate in the IC, etc. In this embodiment, the frequency of the TE signal is 60 HZ.

The first frequency testing device 120 includes a first display device 121 and a first frequency setting device 122, as required. The first frequency setting device 122 is configured to set a first frequency, where the first frequency is a frequency of the first test signal 160 during normal operation. The first display device 121 is used for locking the output frame when the frequency of the first test signal 160 detected by the first frequency testing device 120 is inconsistent with the first frequency.

The second frequency testing device 130 includes a second display device 131 and a second frequency setting device 132, as required. The second frequency setting device 132 is configured to set a second frequency, where the second frequency is a frequency of the second test signal 170 during normal operation. The second display device 131 is used for locking the output frame when the frequency of the second test signal 170 detected by the second frequency testing device 130 is not consistent with the second frequency.

The output frequency of the TE signal is set to 60HZ by the code, and the output frequency of the PWM signal is set to 1KHZ by the code. When the open-short circuit line of the circuit board 200 is normal, the digital frequency meter can normally read the frequencies of the TE signal and the PWM signal, and the actually measured waveform is as shown in fig. 7.

When the first conductive loop 140 or the second conductive loop 150 is in an open state due to the solder skip phenomenon of the circuit board 200, the TE signal or the PWM signal received by the digital frequency meter is in an off state, and the reading frequency of the TE signal or the PWM signal is 0 HZ. Since the first conductive loop 140 or the second conductive loop 150 is disconnected, the TE signal or the PWM signal cannot be normally output to the first frequency testing device 120 or the second frequency testing device 130.

When the first conductive loop 140 or the second conductive loop 150 is short-circuited due to the existence of the solder connection on the circuit board 200, the TE signal and the PWM signal are superimposed. At this time, the digital frequency meter reads that the frequency of the TE signal or the PWM signal is the same and does not satisfy the previously set frequency, as shown in fig. 8.

It can be seen that, only by reading the frequencies of the TE signal and the PWM signal through the first frequency testing device 120 and the second frequency testing device 130, it can be confirmed whether there is an open short circuit in the circuit board 200,

taking code setting TE network frequency as 60HZ and PWM network frequency as 1000HZ as an example, the corresponding determination results are shown in the following table, namely:

1. when the open-short circuit line of the circuit board 200 is normal, the digital frequency meter can normally read the frequencies of the TE signal and the PWM signal. At this time, the frequency received by the first frequency testing device 120 is 1000 HZ; the frequency received by the second frequency testing device is 60 HZ.

2. When the first conductive loop 140 or the second conductive loop 150 is in an open state due to the solder skip phenomenon of the circuit board 200, the TE signal or the PWM signal received by the digital frequency meter is in an off state, and the reading frequency of the TE signal or the PWM signal is 0 HZ. That is, if the first conductive loop 140 is open, the second conductive loop 150 is normal, the frequency received by the first frequency testing device 120 is 0, and the frequency received by the second frequency testing device 130 is 60 HZ. If the first conductive loop 140 is normal, the second conductive loop 150 is open, the frequency received by the first frequency testing device 120 is 1000HZ, and the frequency received by the second frequency testing device 130 is 0. If the first conductive loop 140 and the second conductive loop 150 are both open, the frequencies received by the first frequency testing device 120 and the second frequency testing device 130 are both 0.

3. When the first conductive loop 140 or the second conductive loop 150 is short-circuited due to the existence of the solder connection on the circuit board 200, the TE signal and the PWM signal are superimposed. At this time, the digital frequency meter reads that the frequency of the TE signal or the PWM signal is the same and does not satisfy the previously set frequency. That is, the frequency received by the first frequency testing device 120 is greater than 0 but not equal to 1000 HZ; the frequency received by the second frequency testing device 130 is greater than 0 but not equal to 60 HZ.

	First frequency testing device	Second frequency testing device	First conductive loop	Second conductive loop
					Results 1	1000HZ	60HZ	Is normal	Is normal
Results 2	0	60HZ	Open circuit	Is normal
					Results 3	1000HZ	0	Is normal	Open circuit
Results 4	0	0	Open circuit	Open circuit
					Results 5	>0 and not equal to 1000HZ	>0 and not equal to 60HZ	Short circuit	Short circuit

The utility model provides an among the testing arrangement 100, make circuit board 200 form first conductive loop 140 and second conductive loop 150 through surveying test panel 110, and two adjacent interfaces are located different conductive loops in the circuit board 200. At this time, the open circuit or short circuit information in the wiring board 200 can be obtained by detecting the first conductive loop 140 and the second conductive loop 150. The test device 100 has the following beneficial effects:

1. the test board 110 has a simple structure, can adapt to the open-short circuit test of the circuit board 200 containing more circuits according to actual requirements, and has the characteristics of simplicity, convenience and extremely strong compatibility.

2. The first frequency testing device 120 and the second frequency testing device 130 are used for testing the first conductive loop 140 and the second conductive loop 150 formed on the circuit board 200, the circuit adopts a zero-device scheme, and an LED or a resistor device is not used, so that the testing cost is greatly optimized, and the reliability risk of device mounting is directly avoided.

3. In one embodiment, the first test signal 160 is set to a PWM signal; the second test signal 170 is set to a TE signal. Because the PWM signal and the TE signal are tested in the production process, the testing devices of the PWM signal and the TE signal, such as the first frequency testing device 120 and the second frequency testing device 130, can be used for simultaneously carrying out open-short circuit testing on the circuit board 200, additional testing stations and additional testing items are not required to be added, the production line testing time is greatly shortened, and the production efficiency is improved.

The above disclosure is only a preferred embodiment of the present invention, and certainly should not be taken as limiting the scope of the invention, which is defined by the claims and their equivalents.

Claims

1. A testing device is characterized by comprising a testing board, a first frequency testing device and a second frequency testing device, wherein the testing board comprises a first interface and a second interface, the first interface is used for connecting a first end of a circuit board, the second interface is used for connecting a second end of the circuit board, the first interface comprises a plurality of connecting ends A1, A2, … … and An, wherein n is a positive integer, the second interface comprises a plurality of connecting ends B1, B2, … … and Bn, a first conductive path is arranged between the connecting ends A1, A2, … … and An of the first interface, a second conductive path is arranged between the connecting ends B1, B2, … … and Bn of the second interface, the first conductive path and the second conductive path are used for enabling the circuit board connected on the testing board to form a first conductive loop and a second conductive loop, and two adjacent interfaces in the circuit board are positioned on different conductive loops, the first frequency testing device is connected to one end of the first conductive loop, the other end of the first conductive loop is connected with a first testing signal, the second frequency testing device is connected to one end of the second conductive loop, and the other end of the second conductive loop is connected with a second testing signal.

2. The test apparatus of claim 1, wherein when n/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-3) is electrically connected with A (n-1); the second conductive path is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-2) is electrically connected with Bn; when n/2 is an odd number, the first conductive path is connected in the following way: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-3) is electrically connected with B (n-1); when (n-1)/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-4) is electrically connected with A (n-2); the second conductive path is connected in the following manner: b2 is electrically connected with B4, B3 is electrically connected with B5, … …, and B (n-2) is electrically connected with Bn; when (n-1)/2 is an odd number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A4 is electrically connected with A6, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b2 and B4 are electrically connected, B3 and B5 are electrically connected, … …, and B (n-4) and B (n-2) are electrically connected.

3. The test apparatus of claim 1, wherein when n/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-4) is electrically connected with B (n-2); when n/2 is an odd number, the first conductive path is connected in the following way: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-4) is electrically connected with A (n-2); the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-2) is electrically connected with Bn; when (n-1)/2 is an even number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-3) is electrically connected with A (n-1); the second conductive path is connected in the following manner: b3 is electrically connected with B5, B4 is electrically connected with B6, … …, and B (n-2) is electrically connected with Bn; when (n-1)/2 is an odd number, the first conductive path is connected in a manner that: a1 is electrically connected with A3, A2 is electrically connected with A4, … …, A (n-2) is electrically connected with An; the second conductive path is connected in the following manner: b3 and B5 are electrically connected, B4 and B6 are electrically connected, … …, and B (n-3) and B (n-1) are electrically connected.

4. The test apparatus of claim 1, wherein the first test signal is a PWM signal.

5. The test apparatus of claim 4, wherein the PWM signal has a frequency of 1000 HZ.

6. The test apparatus of claim 1, wherein the second test signal is a TE signal.

7. The test apparatus of claim 6, wherein the TE signal has a frequency of 60 HZ.

8. A test device as claimed in claim 1, wherein the first frequency test device and/or the second frequency test device is a digital frequency meter.

9. The testing apparatus of claim 8, wherein the first frequency testing apparatus comprises a first display apparatus and a first frequency setting apparatus, the first frequency setting apparatus is configured to set a first frequency, and the first display apparatus is configured to lock the output screen when the frequency of the first test signal detected by the first frequency testing apparatus is not consistent with the first frequency.

10. The testing apparatus of claim 8, wherein the second frequency testing apparatus comprises a second display apparatus and a second frequency setting apparatus, the second frequency setting apparatus is configured to set a second frequency, and the second display apparatus is configured to lock the output screen when the frequency of the second test signal detected by the second frequency testing apparatus is not consistent with the second frequency.