CN214959274U - Single-end-to-double-end driving circuit - Google Patents
Single-end-to-double-end driving circuit Download PDFInfo
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- CN214959274U CN214959274U CN202120020467.8U CN202120020467U CN214959274U CN 214959274 U CN214959274 U CN 214959274U CN 202120020467 U CN202120020467 U CN 202120020467U CN 214959274 U CN214959274 U CN 214959274U
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Abstract
The utility model relates to a single-ended changes drive circuit of bi-polar, including the input simultaneously with the rising edge delay circuit that PWM signal foot electricity of PWM control IC is connected, decline along delay circuit, the input is connected with the first drive circuit UA that rises along delay circuit's output electricity, the input is connected with the second drive circuit UB or the third drive circuit UD that decline along delay circuit's output electricity, first drive circuit UA, second drive circuit UB or third drive circuit UD, PWM control IC's power foot connects VCC voltage end simultaneously, first drive circuit UA, second drive circuit UB or third drive circuit UD, PWM control IC, rise along delay circuit, decline along delay circuit's ground connection GND simultaneously. The scheme solves the problem that the dead time adjustment between adjacent high-level pulses output by the two-way asymmetric complementary drive of the PWM control IC in the power supply is not flexible enough, and the working is safer and more reliable.
Description
Technical Field
The utility model relates to a power supply circuit technical field especially relates to a single-ended changes drive circuit of bi-polar.
Background
The existing power supply with an active clamping function or an asymmetric half-bridge power supply and a DC-to-DC direct-current power supply with a synchronous rectification function (such as a flyback converter, a forward converter, a BOOST converter BOOST, a BUCK converter BUCK, a single-ended primary side inductance type converter SEPIC and a BOOST-BUCK converter CUK) have more than two field effect transistors or insulated gate bipolar transistors, and are generally driven by a special power supply control IC with a double-path asymmetric complementary driving output end, the special power supply control IC has two paths of output complementary PWM output ends, dead time is set between adjacent high-level pulses of the two paths of complementary PWM, and the two switching tubes are prevented from being broken due to common conduction.
However, the existing dedicated power control IC with dual-path asymmetric complementary driving output end has the following defects:
(1) the dead time between two paths of complementary PWM adjacent high-level pulses of the special IC is not flexible enough to be adjusted, either fixed dead time is set, or the dead time can be adjusted only at the same time;
(2) when different field effect transistors or insulated gate bipolar transistors are driven, the required dead time is different due to different input capacitances, and if the fixed dead time or the dead time is adjusted simultaneously, the proper driving matching cannot be achieved, so that the switching loss is increased or two field effect transistors or insulated gate bipolar transistors are conducted together to be damaged;
(3) the dedicated power supply has fewer ICs and is expensive, resulting in high power supply cost.
In view of the above disadvantages, we invented a single-end to dual-end driving circuit.
SUMMERY OF THE UTILITY MODEL
The utility model discloses an invention aim at solve current special power control IC from taking the asymmetric complementary drive output of double-circuit, there is the dead time between the adjacent high level pulse of two way complementary PWM of special IC to adjust not nimble enough, or set up fixed dead time, or dead time can only adjust simultaneously, when driving different field effect transistor or insulated gate bipolar transistor, because of the input capacitance is different, dead time is different, if fixed dead time or dead time adjust simultaneously, it matches not to reach very suitable drive, make switching loss increase or lead to two field effect transistor or insulated gate bipolar transistor to switch on jointly and damage, special power control IC problem with high costs. The concrete solution is as follows:
a single-end-to-double-end driving circuit comprises a rising edge delay circuit and a falling edge delay circuit, wherein the input end of the rising edge delay circuit and the falling edge delay circuit are electrically connected with a PWM signal pin of a PWM control IC at the same time, the input end of the first driving circuit UA is electrically connected with the output end of the rising edge delay circuit, the input end of the second driving circuit UB or the third driving circuit UD is electrically connected with the output end of the falling edge delay circuit, the power supply pins of the first driving circuit UA, the second driving circuit UB or the third driving circuit UD, the PWM control IC, the rising edge delay circuit and the falling edge delay circuit are connected with a VCC voltage end at the same time, and the grounding pins of the first driving circuit UA, the second driving circuit UB or the third driving circuit UD, the PWM control IC, the rising edge delay circuit and the falling edge delay circuit are grounded GND at the same time.
Furthermore, the rising edge delay circuit comprises one end of a resistor R1 and a cathode of a diode D1 which are simultaneously electrically connected with the input end IN, the other end of a resistor R1, an anode of a diode D1 and one end of a capacitor C1 are simultaneously electrically connected with the A end, and the other end of the capacitor C1 is grounded GND.
Furthermore, the falling edge delay circuit comprises one end of a resistor R2 and an anode of a diode D2 which are simultaneously electrically connected with the input end IN, the other end of a resistor R2, a cathode of a diode D2 and one end of a capacitor C2 are simultaneously electrically connected with the end B, and the other end of a capacitor C2 is grounded GND.
Further, the PWM control IC is any one of an IC of a flyback converter, an IC of a BOOST converter, and an IC of a forward converter; the IC model of the flyback converter is OB2361 or NCP1342 or UC3843, the IC model of the BOOST converter is L6561 or OB6563 or NCP1608, and the IC model of the forward converter is UC 3845.
Furthermore, the output end of the first driving circuit UA is in phase with the input end thereof, and the output end of the second driving circuit UB or the third driving circuit UD is in phase or in phase opposition with the input end thereof.
Alternative 1:
the input end of the first driving circuit UA is electrically connected with the end A, the output end DR1 of the first driving circuit UA is electrically connected with the grid electrode of the first field-effect tube Q1, the input end of the second driving circuit UB is electrically connected with the end B, the output end of the second driving circuit UB is electrically connected with the input end of the level shifting circuit, and the output end DR2 of the level shifting circuit is electrically connected with the grid electrode of the second field-effect tube Q2; the input end of the level shift circuit is one end of a capacitor C3, the other end of the capacitor C3 is electrically connected with the anode of a diode D3 and is the output end DR2 of the level shift circuit, and the cathode of the diode D3 is grounded GND.
The first driving circuit UA and the second driving circuit UB are combined into a double-channel low-side gate driving IC with in-phase output, or the first driving circuit UA and the second driving circuit UB are respectively a single-channel low-side gate driving IC with in-phase output; the model of the two-channel low-side gate drive IC of the in-phase output is any one of MIC4424, UCC27324 or UCC27524, and the model of the single-channel low-side gate drive IC of the in-phase output is any one of TC1410N or MCP 1402.
Alternative 2:
the input end of the first driving circuit UA is electrically connected to the a terminal, the output end DR1 of the first driving circuit UA is electrically connected to the gate of the first field-effect transistor Q1, the input end of the third driving circuit UD is electrically connected to the B terminal, and the output end DR3 of the third driving circuit UD is electrically connected to the gate of the third field-effect transistor Q3.
The first driving circuit UA and the third driving circuit UD are combined into a double-channel low-side grid driving IC with one path of in-phase output and one path of reverse phase output, or the first driving circuit UA is a single-channel low-side grid driving IC with one-phase output, and the third driving circuit UD is a single-channel low-side grid driving IC with one-phase reverse phase output; the model of the dual-channel low-side gate drive IC with one in-phase output and one reverse-phase output is any one of MIC4425, UCC27325 or UCC27525, the model of the single-channel low-side gate drive IC with the in-phase output is any one of TC1410N or MCP1402, and the model of the single-channel low-side gate drive IC with the reverse-phase output is any one of TC1410 or MCP 1401.
To sum up, adopt the utility model discloses a technical scheme has following beneficial effect:
the utility model provides a current special power control IC from taking the asymmetric complementary drive output of double-circuit, there is special IC's two way complementary PWM's dead time between the adjacent high level pulse to adjust not nimble enough, or set up fixed dead time, or dead time can only adjust simultaneously, when driving different field effect transistor or insulated gate bipolar transistor, because of the input capacitance is different, dead time is different, if fixed dead time or dead time adjust simultaneously, it matches not to reach very suitable drive, make the switching loss increase or lead to two field effect transistor or insulated gate bipolar transistor to switch on jointly and damage, special power control IC problem with high costs. The scheme has the following advantages:
1. the problem of in the power supply the dead time between the adjacent high level pulse of two-way asymmetric complementary drive output of PWM control IC adjust not enough in a flexible way is solved, the dead time can be independently adjusted wantonly, can better match the field effect transistor or the insulated gate bipolar transistor of different input capacitance, switching loss is minimum, field effect transistor or insulated gate bipolar transistor during operation is more safe and reliable.
2. The power supply control IC with the structures of flyback conversion, BOOST, BUCK, SEPIC and the like of a single driving output end in the power supply can not drive the power supply with the active clamping function or the power supply of an asymmetric half bridge, and the field effect transistor or the insulated gate bipolar transistor in the DC-to-DC direct-current power supply with the synchronous rectification function, such as BOOST, BUCK, SEPIC and the like, so that the cost of the power supply is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed to be used in the description of the embodiments of the present invention will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive faculty.
Fig. 1 is a block diagram of a single-end to double-end driving circuit according to the present invention;
fig. 2 is a circuit diagram of an embodiment 1 of a single-end to double-end driving circuit according to the present invention;
fig. 3 is a waveform diagram of an embodiment 1 of a single-end to double-end driving circuit according to the present invention;
fig. 4 is a circuit diagram of an embodiment 2 of a single-end to double-end driving circuit according to the present invention;
fig. 5 is a waveform diagram of an embodiment 2 of a single-end to dual-end driving circuit according to the present invention.
Description of reference numerals:
10-PWM control IC, 20-rising edge delay circuit, 30-falling edge delay circuit, 40-first drive circuit, 50-second drive circuit.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example 1:
as shown IN fig. 1 to 3, a single-end-to-dual-end driving circuit includes a rising edge delay circuit 20 and a falling edge delay circuit 30, the input ends of which are electrically connected to a PWM signal pin IN of a PWM control IC 10, a first driving circuit 40 (UA) whose input end is electrically connected to an output end of the rising edge delay circuit 20, a second driving circuit 50 (UB) whose input end is electrically connected to an output end of the falling edge delay circuit 30, the power supply pins of the first driving circuit 40, the second driving circuit 50 and the PWM control IC 10 are connected to a VCC voltage terminal, and the ground pins of the first driving circuit 40, the second driving circuit 50, the PWM control IC 10, the rising edge delay circuit 20 and the falling edge delay circuit 30 are connected to GND.
Further, the rising edge delay circuit 20 includes one end of a resistor R1, a cathode of a diode D1, which are electrically connected to the input terminal IN, the other end of the resistor R1, an anode of the diode D1, and one end of a capacitor C1, which are electrically connected to the a terminal, and the other end of the capacitor C1 is grounded to GND.
Further, the falling edge delay circuit 30 includes one end of a resistor R2 and an anode of a diode D2 which are electrically connected to the input terminal IN at the same time, the other end of a resistor R2, a cathode of a diode D2, and one end of a capacitor C2 are electrically connected to the B terminal at the same time, and the other end of the capacitor C2 is grounded to GND.
Further, the PWM control IC 10 is any one of an IC of a flyback converter, an IC of a BOOST converter, or an IC of a forward converter; the IC model of the flyback converter is OB2361, NCP1342 or UC3843, the IC model of the BOOST converter is L6561, OB6563 or NCP1608, and the IC model of the forward converter is UC 3845.
Further, the output of the first driving circuit 40 is in phase with its input, and the output of the second driving circuit 50 is in phase with its input.
Optionally, an input end of the first driving circuit UA is electrically connected to the terminal a, an output end DR1 of the first driving circuit UA is electrically connected to a gate of a first field-effect transistor (N-channel transistor) Q1, an input end of the second driving circuit UB is electrically connected to the terminal B, an output end of the second driving circuit UB is electrically connected to an input end of the level shifting circuit, and an output end DR2 of the level shifting circuit is electrically connected to a gate of a second field-effect transistor (P-channel transistor) Q2. The input end of the level shift circuit is one end of a capacitor C3, the other end of the capacitor C3 is electrically connected with the anode of a diode D3 and is the output end DR2 of the level shift circuit, and the cathode of the diode D3 is grounded GND.
The first driving circuit UA and the second driving circuit UB are combined into a double-channel low-side gate driving IC with in-phase output, or the first driving circuit UA and the second driving circuit UB are respectively a single-channel low-side gate driving IC with in-phase output. The model of the two-channel low-side gate drive IC of the in-phase output is any one of MIC4424, UCC27324 or UCC27524, and the model of the single-channel low-side gate drive IC of the in-phase output is any one of TC1410N or MCP 1402.
Example 2:
as shown in fig. 4 and 5, unlike embodiment 1, the output terminal of the third drive circuit (i.e., UD) is inverted with respect to the input terminal thereof. An input terminal of the third driver circuit UD is electrically connected to the terminal B, and an output terminal DR3 of the third driver circuit UD is electrically connected to a gate of a third field effect transistor (N-channel transistor) Q3.
The first driving circuit UA and the third driving circuit UD are combined into a dual-channel low-side gate driving IC with one path of in-phase output and one path of reverse phase output, or the first driving circuit UA is a single-channel low-side gate driving IC with one-phase output, and the third driving circuit UD is a single-channel low-side gate driving IC with one-phase reverse phase output. The model of the dual-channel low-side gate drive IC with one in-phase output and one inverted output is any one of MIC4425, UCC27325 and UCC27525, and the model of the single-channel low-side gate drive IC with the inverted output is any one of TC1410 and MCP 1401. The rest of the process is the same as that of embodiment 1, and will not be described herein.
As shown in fig. 2, 3, 4, and 5, the present solution is a single-to-double end driving circuit, which performs delay and dead-zone adjustment according to the following steps:
step 1, when a rising edge of a PWM signal waveform (see IN fig. 3 for an input waveform) is input, on one hand, a resistor R1 of a rising edge delay circuit 20 jointly acts on a capacitor C1 charging circuit (corresponding to a charging waveform at the a end IN fig. 3) and a turn-on threshold voltage of a first driving circuit UA, and a first driving (i.e., UA) outputs (see DR1 IN fig. 3 for an output waveform) a delayed first driving rising edge; on the other hand, the capacitor C2 is rapidly charged by the diode D2 of the falling-edge delay circuit 30 to rapidly reach the second driving (i.e., UB) turn-on threshold voltage, and the second driving output (see DR2 in fig. 3 for the output waveform) has a second driving rising edge or a second driving falling edge (see fig. 5) synchronized with the rising edge of the PWM signal waveform;
step 3, when the falling edge of the input PWM signal waveform, on one hand, the capacitor C1 of the rising edge delay circuit 20 discharges to the input terminal rapidly through the diode D1, and the first drive outputs a first drive falling edge synchronized with the falling edge of the PWM signal waveform; on the other hand, the capacitor C2 of the falling edge delay circuit 30 discharges the input terminal through the resistor R2 (corresponding to the discharge waveform of the B terminal in fig. 3B) and the turn-on threshold voltage of the second driving circuit UB cooperates, the second driving outputs a delayed second driving falling edge, the second driving high level stage extends to the second driving falling edge or the second driving outputs a delayed second driving rising edge, and the second driving low level stage extends to the second driving falling edge (as shown in fig. 5);
step 4, when the PWM signal waveform low-level platform is input, on one hand, the first drive outputs a first drive low-level platform, and the first drive low-level platform is prolonged to be before the next first drive is conducted; on the other hand, the second drive outputs a second drive low level plateau from the falling edge or outputs a second drive high level plateau from the rising edge;
step 5, a first driving high-level platform time length from the first driving rising edge to the first driving falling edge corresponds to a turn-on time length Td1 of the first field effect transistor Q1, and a first driving low-level platform time length from the first driving falling edge to the next first driving rising edge corresponds to a turn-off time length Tj1 of the first field effect transistor Q1; a second driving high-level stage duration from the second driving rising edge to the second driving falling edge, which corresponds to an off duration Tj2 of the second field effect transistor Q2, and a second driving low-level stage duration from the second driving falling edge to the next second driving rising edge, which corresponds to an on duration Td2 of the second field effect transistor Q2; or the second driving low-level stage duration from the second driving falling edge to the second driving rising edge corresponds to the off duration Tj3 of the third field effect transistor Q3, and the second driving high-level stage duration from the second driving rising edge to the next second driving falling edge corresponds to the on duration Td3 of the third field effect transistor Q3;
step 6, by the rising edge delay circuit 20 and the falling edge delay circuit 30, the on-time Td1 of the first fet Q1 falls within the off-time Tj2 of the second fet Q2 or falls within the off-time Tj3 of the third fet Q3, the on-time Td2 of the second fet Q2 or the on-time Td3 of the third fet Q3 falls within the off-time Tj1 of the first fet Q1, and the first fet Q1 and the second fet Q2 or the third fet Q3 are alternately turned on;
and step 7, through the rising edge delay circuit 20 and the falling edge delay circuit 30, a common cut-off dead zone (shown as a shaded zone in fig. 3) exists between the front end and the rear end of the conduction interval of the first field effect transistor Q1 and the front end and the rear end of the conduction interval of the second field effect transistor Q2 or the third field effect transistor Q3, and the length of the dead zone is adjusted by parameters of the resistor R1, the capacitor C1 or the resistor R2 and the capacitor C2.
To sum up, adopt the utility model discloses a technical scheme has following beneficial effect:
the utility model provides a current special power control IC from taking the asymmetric complementary drive output of double-circuit, there is special IC's two way complementary PWM's dead time between the adjacent high level pulse to adjust not nimble enough, or set up fixed dead time, or dead time can only adjust simultaneously, when driving different field effect transistor or insulated gate bipolar transistor, because of the input capacitance is different, dead time is different, if fixed dead time or dead time adjust simultaneously, it matches not to reach very suitable drive, make the switching loss increase or lead to two field effect transistor or insulated gate bipolar transistor to switch on jointly and damage, special power control IC problem with high costs. The scheme has the following advantages:
1. the problem that dead time adjustment between adjacent high-level pulses (namely between adjacent high-level platforms) output by double-path asymmetric complementary drive of a PWM control IC in a power supply is not flexible enough is solved, the dead time can be independently and randomly adjusted, field effect transistors or insulated gate bipolar transistors with different input capacitances can be better matched, the switching loss is minimum, and the field effect transistors or the insulated gate bipolar transistors are safer and more reliable in working.
2. The power supply control IC with the structures of flyback conversion, BOOST, BUCK, SEPIC and the like of a single driving output end in the power supply can not drive the power supply with the active clamping function or the power supply of an asymmetric half bridge, and the field effect transistor or the insulated gate bipolar transistor in the DC-to-DC direct-current power supply with the synchronous rectification function, such as BOOST, BUCK, SEPIC and the like, so that the cost of the power supply is reduced.
The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.
Claims (10)
1. A single-end-to-double-end driving circuit is characterized in that: the power supply pins of the first driving circuit UA, the second driving circuit UB or the third driving circuit UD and the PWM control IC are simultaneously connected with a VCC voltage end, and the grounding pins of the first driving circuit UA, the second driving circuit UB or the third driving circuit UD, the PWM control IC, the rising edge delay circuit and the falling edge delay circuit are simultaneously grounded GND.
2. The single-to-double end driver circuit of claim 1, wherein: the rising edge delay circuit comprises one end of a resistor R1 and a cathode of a diode D1 which are simultaneously and electrically connected with an input end IN, the other end of a resistor R1, an anode of a diode D1 and one end of a capacitor C1 are simultaneously and electrically connected with an end A, and the other end of a capacitor C1 is grounded GND.
3. The single-to-double end driver circuit of claim 2, wherein: the falling edge delay circuit comprises one end of a resistor R2 and an anode of a diode D2 which are simultaneously and electrically connected with an input end IN, the other end of a resistor R2, a cathode of a diode D2 and one end of a capacitor C2 are simultaneously and electrically connected with a terminal B, and the other end of a capacitor C2 is grounded GND.
4. The single-to-double end driver circuit of claim 3, wherein: the PWM control IC is any one of an IC of a flyback converter, an IC of a BOOST converter or an IC of a forward converter; the IC model of the flyback converter is OB2361 or NCP1342 or UC3843, the IC model of the BOOST converter is L6561 or OB6563 or NCP1608, and the IC model of the forward converter is UC 3845.
5. The single-to-double end driver circuit of claim 4, wherein: the output end of the first driving circuit UA is in phase with the input end thereof, and the output end of the second driving circuit UB or the third driving circuit UD is in phase with or opposite to the input end thereof.
6. The single-to-double end driver circuit of claim 5, wherein: the input end of the first driving circuit UA is electrically connected with the end A, the output end DR1 of the first driving circuit UA is electrically connected with the grid electrode of the first field-effect tube Q1, the input end of the second driving circuit UB is electrically connected with the end B, the output end of the second driving circuit UB is electrically connected with the input end of the level shifting circuit, and the output end DR2 of the level shifting circuit is electrically connected with the grid electrode of the second field-effect tube Q2; the input end of the level shift circuit is one end of a capacitor C3, the other end of the capacitor C3 is electrically connected with the anode of a diode D3 and is the output end DR2 of the level shift circuit, and the cathode of the diode D3 is grounded GND.
7. The single-to-double end driver circuit of claim 6, wherein: the first driving circuit UA and the second driving circuit UB are combined into a double-channel low-side gate driving IC with in-phase output, or the first driving circuit UA and the second driving circuit UB are respectively a single-channel low-side gate driving IC with in-phase output; the model of the two-channel low-side gate drive IC of the in-phase output is any one of MIC4424, UCC27324 or UCC27524, and the model of the single-channel low-side gate drive IC of the in-phase output is any one of TC1410N or MCP 1402.
8. The single-to-double end driver circuit of claim 5, wherein: the input end of the first driving circuit UA is electrically connected to the a terminal, the output end DR1 of the first driving circuit UA is electrically connected to the gate of the first field-effect transistor Q1, the input end of the third driving circuit UD is electrically connected to the B terminal, and the output end DR3 of the third driving circuit UD is electrically connected to the gate of the third field-effect transistor Q3.
9. The single-to-double ended driver circuit of claim 8, wherein: the first driving circuit UA and the third driving circuit UD are combined into a dual-channel low-side gate driving IC with one path of in-phase output and one path of reverse phase output, or the first driving circuit UA is a single-channel low-side gate driving IC with one-phase output, and the third driving circuit UD is a single-channel low-side gate driving IC with one-phase reverse phase output.
10. The single-to-double ended driver circuit of claim 9, wherein: the model of the dual-channel low-side gate drive IC with the same-phase output and the same-phase reverse output is any one of MIC4425, UCC27325 or UCC27525, the model of the single-channel low-side gate drive IC with the same-phase output is any one of TC1410N or MCP1402, and the model of the single-channel low-side gate drive IC with the reverse-phase output is any one of TC1410 or MCP 1401.
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| CN202120020467.8U CN214959274U (en) | 2021-01-04 | 2021-01-04 | Single-end-to-double-end driving circuit |
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| CN202120020467.8U CN214959274U (en) | 2021-01-04 | 2021-01-04 | Single-end-to-double-end driving circuit |
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