CN214958665U - Hiccup protection circuit, power chip - Google Patents
Hiccup protection circuit, power chip Download PDFInfo
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- CN214958665U CN214958665U CN202121058069.1U CN202121058069U CN214958665U CN 214958665 U CN214958665 U CN 214958665U CN 202121058069 U CN202121058069 U CN 202121058069U CN 214958665 U CN214958665 U CN 214958665U
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Abstract
The utility model provides a hiccup protection circuit, power chip, hiccup protection circuit constructs delay circuit including the main logic circuit of protection that is used for control power to open and close through a plurality of D triggers in protection main logic circuit, and the judgement in the face of faults such as excessive pressure, under-voltage, short circuit that appear in the power is more accurate, effectively prevents the misjudgment and leads to the problem that power stability reduces, has improved the interference killing feature of power, can protect the load better, makes to be located within the safe power supply environment.
Description
Technical Field
The utility model belongs to the technical field of electrician's electron technique and specifically relates to a hiccup protection circuit, power chip are related to.
Background
Usually, the power supply product has a fixed maximum output current protection, but when the working current of the load is abnormal and cannot reach the protection threshold current of the power supply, the load can be further damaged by continuing to be electrified; or when some loads need instantaneous burst output, the protection current set by the finished power supply module is often too sensitive to cause abnormal stop of the loads. Therefore, there is a need for a hiccup protection circuit that can improve the stability of the power supply and protect the load from safety.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention provides a hiccup protection circuit and a power chip, which improve the stability of the power supply to make the load in the safe power supply environment.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides a hiccup protection circuit, including a protection main logic circuit for controlling power on and off, the protection main logic circuit includes: a first delay circuit and a second delay circuit; wherein the first delay circuit and the second delay circuit each comprise N D flip-flops, where N ∈ {1,2,3 …, i }; i belongs to a positive integer; for the D triggers belonging to the same delay circuit, the Nth D trigger is connected with the (N + 1) th D trigger;
when N is equal to 1, the CP trigger of the first D trigger is used for inputting pulse signals, and the D end of the first D trigger are connected with the D end of the first D trigger
The Q end of the first D trigger is connected with the CP trigger delay of the second D trigger;
when N is larger than 1 and smaller than i, the CP trigger delay of the Nth D trigger is connected with the Q end of the (N-1) th D trigger; d end of the Nth D trigger and the D end of the Nth D trigger
End connection; the Q end of the Nth D trigger is connected with the CP trigger delay of the (N + 1) th D trigger;
when N is equal to i, the CP trigger delay of the ith D trigger is connected with the Q end of the (N-1) th D trigger; the D end of the ith D trigger and the D end of the ith D trigger
End connection; and the Q end of the ith D flip-flop is used for outputting a pulse signal.
Optionally, the protection main logic circuit further includes: the load overcurrent protection circuit comprises an IOVP input end for receiving an input voltage indication signal, an OOVP input end for receiving an output voltage indication signal, an OCP input end for receiving a load overcurrent indication signal, a pulse signal input end, a starting signal input end, an enabling signal output end, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a first inverter, a second inverter, a third inverter and an RS trigger;
the IOVP input end, the OOVP input end and the OCP input end are respectively connected with the three input ends of the first NAND gate; the output end of the first NAND gate is connected with the first input end of the third NAND gate; the output end of the third NAND gate is connected with the reset end of the first delay circuit; the second input end of the third NAND gate is connected with the output end of the second NAND gate; the output end of the first delay circuit is connected with the input end of the first phase inverter; the input end of the starting signal and the output end of the second delay circuit are respectively connected with two input ends of a second NAND gate; the reset end of the second delay circuit is connected with the output end of the RS trigger; the RS trigger is formed by cross connection of a fourth NAND gate and a fifth NAND gate; the input end of the RS trigger is respectively connected with the output ends of the first inverter and the second inverter; the output end of the RS trigger is connected with the input end of the third inverter; the output end of the third inverter is connected with the enable signal output end; the output end of the second NAND gate is respectively connected with the second input end of the third NAND gate and the input end of the second inverter.
Optionally, the hiccup protection circuit further comprises a clock generation circuit for generating a clock signal, the clock generation circuit comprising: the device comprises a first resistor, a voltage stabilizing diode, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier, a first reference voltage, a second reference voltage and a D trigger; a first delayer; a power supply output terminal; a pulse signal output terminal;
the first resistor and the voltage stabilizing diode are connected in series to divide voltage to form a reference source and are connected in parallel with the first capacitor; the source electrode of the first MOS tube is connected with the power supply output end; the grid electrode of the first MOS tube is respectively connected with the drain electrode of the first MOS tube and the grid electrode of the second MOS tube; the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with one end of the first resistor; the source electrode of the third MOS tube is connected with the common ground; the source electrode of the second MOS tube is connected with the power supply output end; the drain electrode of the second MOS tube is respectively connected with the drain electrode of the fourth MOS tube, one end of the second capacitor, the inverting port of the first operational amplifier and the non-inverting port of the second operational amplifier; the drain electrode of the fourth MOS tube and the other end of the second capacitor are respectively connected with the common ground; the grid electrode of the fourth MOS tube is connected with the output end of the delayer; the non-inverting port of the first operational amplifier is connected with a first reference voltage; the output end of the first operational amplifier is connected with the CP triggering edge of the D trigger; the inverting input end of the second operational amplifier is connected with a second reference voltage; the output end of the second operational amplifier is connected with the reset end of the D trigger; the input end of the D trigger is connected with a power supply; and the Q end of the D trigger is respectively connected with the input end of the time delay unit and the pulse signal output end.
Optionally, the hiccup protection circuit further comprises a voltage comparison circuit; the voltage comparison circuit includes a first module for representing an indication of an overvoltage of an input voltage; the first module includes: the voltage regulator comprises a VI _ SMP input end, a second resistor, a third resistor, a first comparator, a fifth MOS (metal oxide semiconductor) transistor, a sixth MOS transistor, a third reference voltage, a fourth reference voltage, a second delayer and a fourth inverter; an IOVP output terminal;
the VI _ SMP input end is connected with a non-inverting input port of the first comparator, and is connected in series through a second resistor and a third resistor to divide voltage; the source electrode of the fifth MOS tube is connected with the third reference voltage, the drain electrode of the fifth MOS tube is connected with the inverted input port of the first comparator, and the grid electrode of the fifth MOS tube is connected with the IOVP output end; the source electrode of the sixth MOS tube is connected with a fourth reference voltage, the drain electrode of the sixth MOS tube is connected with the inverted input port of the first comparator, the grid electrode of the sixth MOS tube is connected with the output end of the fourth phase inverter, and the IOVP output end is connected with the input end of the fourth phase inverter; the input end of the second delayer is connected with the output end of the first comparator; the output end of the second delayer is connected with the IOVP output end.
Optionally, the voltage comparison circuit further comprises a second module for indicating an output voltage over-voltage indication; the second module includes: the voltage regulator comprises a VO _ SMP input end, a fourth resistor, a fifth resistor, a second comparator, a third delayer, a seventh MOS (metal oxide semiconductor) tube, an eighth MOS tube, a fifth reference voltage, a sixth reference voltage and a fifth inverter;
the VO _ SMP input end is connected with a non-inverting input port of the second comparator, and voltage division is performed through the series connection of a fourth resistor and a fifth resistor; the source electrode of the seventh MOS tube is connected with the fifth reference voltage; the drain electrode of the seventh MOS tube is connected with the inverted input port of the second comparator; the grid electrode of the seventh MOS tube is connected with the OOVP output end; the source electrode of the eighth MOS tube is connected with a sixth reference voltage; the drain electrode of the eighth MOS tube M4 is connected with the inverting input port of the second comparator; the gate of the eighth MOS transistor M4 is connected to the output end of the fifth inverter; the OOVP output end is connected with the input end of the fifth inverter; the input end of the third delayer is connected with the output end of the second comparator; and the output end of the third delayer is connected with the OOVP output end.
Optionally, the voltage comparison circuit further comprises a third module for representing an indication of the load overcurrent voltage; the third module includes: the third operational amplifier is connected with the fourth comparator, the ninth MOS tube, the tenth MOS tube, the seventh reference voltage, the eighth reference voltage, the sixth inverter and the fourth delayer;
the C _ SMP input end is connected with the non-inverting input end of the third operational amplifier; the output end of the third operational amplifier is connected with the inverting input end of the third operational amplifier and the homodromous input port of the third comparator respectively after being connected with a sixth resistor and a seventh resistor in series for voltage division; the source electrode of the ninth MOS tube is connected with a seventh reference voltage; the drain electrode of the ninth MOS tube is connected with the reverse input port of the third comparator; the grid electrode of the ninth MOS tube is connected with the OCP output end; the source electrode of the tenth MOS tube is connected with the eighth reference voltage; the drain electrode of the tenth MOS tube is connected with the reverse input port of the third comparator; the grid electrode of the tenth MOS tube is connected with the output end of the fifth inverter; the output end of the OCP is connected with the input end of the sixth inverter; the input end of the fourth delayer is connected with the output end of the third comparator; and the output end of the third delayer is connected with the OCP output end.
Optionally, the clock generation circuit controls charging and discharging of the second capacitor through a Q terminal of the D flip-flop.
Optionally, the delay period of the first delay circuit and the second delay circuit is milliseconds or seconds.
In a second aspect, an embodiment of the present invention provides a power chip, including a load switch, a power input terminal, a power output terminal, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a hiccup protection circuit as described in the first aspect of the present invention; the power supply chip is applied to a switching power supply or a linear power supply; the eleventh resistor is a load; the first input end of the hiccup protection circuit is connected to a tap position of the power input end after voltage division through the eighth resistor and the ninth resistor; the second input end of the hiccup protection circuit is connected to a tap of the power supply output end passing through a tenth resistor and an eleventh resistor; the third input end of the hiccup protection circuit is connected with the power supply output end; the enable signal output end of the hiccup protection circuit is connected to an enable pin of a power supply.
Optionally, if the enable pin of the power supply is not available, the enable signal output terminal of the hiccup protection circuit is connected to the G pole of the load switch.
The utility model provides a hiccup protection circuit, power chip, hiccup protection circuit constructs delay circuit including the main logic circuit of protection that is used for control power to open and close through a plurality of D triggers in protection main logic circuit, and the judgement in the face of faults such as excessive pressure, undervoltage, short circuit that appear in the power is more accurate, effectively prevents the misjudgement and leads to the problem that power stability reduces, has improved the interference killing feature of power, can protect the load better and make the part be within safe power supply environment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a first delay circuit and a second delay circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a protection main logic circuit provided in an embodiment of the present invention;
fig. 3 is a schematic diagram of a clock generation circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a voltage comparison circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a power chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Usually, the power supply product has a fixed maximum output current protection, but when the working current of the load is abnormal and cannot reach the protection threshold current of the power supply, the load can be further damaged by continuing to be electrified; or when some loads need instantaneous burst output, the protection current set by the finished power supply module is often too sensitive to cause abnormal stop of the loads. Therefore, a hiccup protection circuit capable of accurately judging power supply faults is urgently needed, stability of a power supply is improved, and load safety is protected.
In view of the above, the present application provides a hiccup protection circuit including a protection main logic circuit for controlling power on and off, the protection main logic circuit including: a first delay circuit and a second delay circuit; as shown in fig. 1, the first delay circuit and the second delay circuit each include N D flip-flops, where N ∈ {1,2,3 …, i }, i is a positive integer; for the D triggers belonging to the same delay circuit, the Nth D trigger is connected with the (N + 1) th D trigger;
when N is equal to 1, the CP trigger of the first trigger is used for inputting the pulse signal CLK, and the D end of the first trigger are connected with the D end of the first trigger
The Q end of the first trigger is connected with the CP trigger delay of the second trigger;
when N is larger than 1 and smaller than i, the CP trigger delay of the Nth D trigger is connected with the Q end of the (N-1) th D trigger; d end of the Nth D trigger and the D end of the Nth D trigger
End connection; the above-mentionedThe Q end of the Nth trigger is connected with the CP trigger delay of the (N + 1) th trigger;
when N is equal to i, the CP trigger delay of the ith D trigger is connected with the Q end of the (N-1) th D trigger; the D end of the ith D trigger and the D end of the ith D trigger
And the Q end of the ith D flip-flop is used for outputting a pulse signal.
Specifically, as shown in fig. 1, CLK _ OUT1 is a pulse signal output terminal in the first delay circuit; CLK _ OUT2 is the pulse signal output terminal of the second delay circuit; RST1 is a first delay circuit reset signal interface; RST2 is the second delay circuit reset signal interface.
Specifically, as shown in fig. 2, the protection main logic circuit further includes: an IOVP input end for receiving an input voltage indication signal, an OOVP input end for receiving an output voltage indication signal, an OCP input end for receiving a load overcurrent indication signal, a pulse signal input end CLK, a start signal input end SD, an enable signal output end EN, a first nand gate I1, a second nand gate I2, a third nand gate I3, a first inverter I4, a second inverter I5, an RS flip-flop, and a third inverter I8;
the IOVP input end, the OOVP input end and the OCP input end are respectively connected with three input ends of a first NAND gate I1; the output end of the first NAND gate I1 is connected with the first input end of the third NOT gate I3; the output end of the third NAND gate I3 is connected with the reset end RST1 of the first delay circuit; a second input end of the third NAND gate I3 is connected with an output end of the second NAND gate I2; the output end of the first delay circuit is connected with the input end of a first inverter I4; the starting signal input end SD and the output end of the second delay circuit are respectively connected with two input ends of a second NAND gate I2; the reset end RST2 of the second delay circuit is connected with the output end of the RS trigger; the RS trigger is formed by cross connection of a fourth NAND gate I6 and a fifth NAND gate I7; the input end of the RS trigger is respectively connected with the output ends of the first inverter I4 and the second inverter I5; the output end of the RS trigger is connected with the input end of a third inverter I8; the output end of the third inverter I8 is connected with the enable signal output end EN; the output end of the second nand gate I2 is connected to the second input end of the third nand gate I3 and the input end of the second inverter I5, respectively.
Specifically, as shown in fig. 3, the hiccup protection further comprises a clock generation circuit for generating a clock signal, the clock generation circuit comprising: the circuit comprises a first resistor R1, a voltage-stabilizing diode D1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a first capacitor C1, a second capacitor C2, a first operational amplifier I9, a second operational amplifier I10, a first reference voltage Verf1, a second reference voltage Verf2 and a D flip-flop I11; a first delayer I12; a power supply output terminal VDD; a pulse signal output terminal CLK;
the first resistor R1 and the voltage-stabilizing diode D1 are connected in series to form a reference source and are connected in parallel with the first capacitor C1; the source electrode of the first MOS transistor M1 is connected with the power output end VDD; the grid electrode of the first MOS tube M1 is respectively connected with the drain electrode of the first MOS tube M1 and the grid electrode of the second MOS tube M2; the drain electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3; the gate of the third MOS transistor M3 is connected to one end of the first resistor R1; the source electrode of the third MOS tube M3 is connected with the common ground; the source electrode of the second MOS transistor M2 is connected with the power output end VDD; the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4, one end of the second capacitor C2, the inverting port of the first operational amplifier I9, and the non-inverting port of the second operational amplifier I10, respectively; the drain electrode of the fourth MOS transistor M4 and the other end of the second capacitor C2 are respectively connected with the common ground; the grid electrode of the fourth MOS tube M4 is connected with the output end of the first delayer I12; the non-inverting port of the first operational amplifier I9 is connected to a first reference voltage Vref 1; the output end of the first operational amplifier I9 is connected with the CP triggering edge of the D flip-flop I11; the inverting input terminal of the second operational amplifier I10 is connected to a second reference voltage Vref 12; the output end of the second operational amplifier I10 is connected with the reset end of the D flip-flop I11; the input end of the D trigger I11 is connected with the power supply output end VDD; the Q terminal of the D flip-flop I11 is connected to the input terminal of the first delay I12 and the pulse signal output terminal CLK, respectively.
In specific implementation, a reference source is formed by serially connecting the first resistor R1 and the voltage-stabilizing diode D1 to form a voltage division, and the reference source is simpler and more reliable by replacing the prior art that a complex storage battery GB is used for generating reference current.
Specifically, as shown in fig. 4, the hiccup protection circuit further includes a voltage comparison circuit; the voltage comparison circuit includes a first module for representing an indication of an overvoltage of an input voltage; the first module includes: the voltage regulator comprises a VI _ SMP input end, a second resistor R2, a third resistor R3, a first comparator I13, a fifth MOS transistor M5, a sixth MOS transistor M6, a third reference voltage Verf3, a fourth reference voltage Verf4, a second delayer I14 and a fourth inverter I15; an IOVP output terminal;
the VI _ SMP input end is connected with a non-inverting input port of a first comparator I13, and is connected in series through a second resistor R2 and a third resistor R3 to divide voltage; the source of the fifth MOS transistor M5 is connected to a third reference voltage Vref 3; the drain electrode of the fifth MOS transistor M5 is connected with the inverted input port of the first comparator I13; the grid electrode of the fifth MOS tube M5 is connected with the IOVP output end; the source of the sixth MOS transistor M6 is connected to a fourth reference voltage Vref 4; the drain electrode of the sixth MOS transistor M6 is connected with the inverted input port of the first comparator I13; the gate of the sixth MOS transistor M6 is connected to the output end of the fourth inverter I15; the IOVP output end is connected with the input end of a fourth inverter I15; the IOVP output end controls the on or off of the fifth MOS tube M5 and the sixth MOS tube M6 by controlling the grid voltage thereof, so that the voltage compared with the VI _ SMP input end is selected; the input end of the second delayer I14 is connected with the output end of the first comparator I13; the output of the second delay I14 is connected to the IOVP output.
Specifically, as shown in FIG. 4, the voltage comparison circuit includes a second module for representing an output voltage over-voltage indication; the second module includes: a VO _ SMP input terminal, a fourth resistor R4, a fifth resistor R5, a second comparator I16, a third delayer I17, a seventh MOS transistor M7, an eighth MOS transistor M8, a fifth reference voltage Verf5, a sixth reference voltage Verf6, and a fifth inverter I18; an OOVP output terminal;
the VO _ SMP input end is connected with a non-inverting input port of a second comparator I16 and is connected in series through a fourth resistor R4 and a fifth resistor R5 to divide voltage; the source of the seventh MOS transistor M7 is connected to the fifth reference voltage Vref 5; the drain electrode of the seventh MOS transistor M7 is connected with the inverting input port of the second comparator I16; the grid electrode of the seventh MOS tube M7 is connected with the OOVP output end; the source of the eighth MOS transistor M8 is connected to a sixth reference voltage Verf 6; the drain electrode of the eighth MOS transistor M8 is connected to the inverting input port of the second comparator I16; the gate of the eighth MOS transistor M8 is connected to the output end of the fifth inverter I18; the OOVP output end is connected with the input end of the fifth inverter I18; the OOVP output terminal controls the on or off of the seventh MOS transistor M7 and the eighth MOS transistor M8 by controlling the gate voltages thereof, so as to select the voltage to be compared with the VO _ SMP input terminal; the input end of the second delayer is connected with the output end of the second comparator; the output of the second delayer I17 is connected to the OOVP output.
Specifically, as shown in fig. 4, the voltage comparison circuit includes a third module for representing an indication of load over-current voltage; the third module includes: the circuit comprises a C _ SMP input end, a third operational amplifier I19, a sixth resistor R6, a seventh resistor R7, a third comparator I20, a fourth delay unit I21, a sixth inverter I22, a ninth MOS transistor M9, a tenth MOS transistor M10, a seventh reference voltage Verf7 and an eighth reference voltage Verf 8;
the C _ SMP input end is connected with the non-inverting input end of a third operational amplifier I19; the output end of the third operational amplifier I19 is connected with the inverting input end of the third operational amplifier I20 and the homodromous input end of the third comparator I20 respectively after being serially connected with a sixth resistor R6 and a seventh resistor R7 for voltage division; the source electrode of the ninth MOS transistor M9 is connected to a seventh reference voltage Verf 7; the drain electrode of the ninth MOS transistor M9 is connected with the inverted input port of the third comparator I20; the grid electrode of the ninth MOS tube M9 is connected with the OCP output end; the source of the tenth MOS transistor M10 is connected to an eighth reference voltage Verf 8; the drain electrode of the tenth MOS transistor M10 is connected to the inverting input terminal of the third comparator I20; the gate of the tenth MOS transistor M10 is connected to the output terminal of the sixth inverter I22; the output end of the OCP is connected with the input end of a sixth inverter I22; the OCP output end controls the conduction or the cut-off of the ninth MOS tube M9 and the tenth MOS tube M10 by controlling the grid voltage of the ninth MOS tube M9 and the tenth MOS tube M10, so that the voltage compared with the C _ SMP input end is selected; the input end of the fourth delay device I21 is connected with the output end of the third comparator I20; the output terminal of the fourth delay I21 is connected to the OCP output terminal.
Specifically, as shown in fig. 3, the clock generation circuit controls the charging and discharging of the second capacitor C2 through the Q terminal of the D flip-flop I11.
Specifically, the delay period of the first delay circuit and the second delay circuit is milliseconds or seconds.
Optionally, as shown in fig. 5, the present application provides a power chip, which includes a load switch, a power input terminal Vin, a power output terminal Vout, an enable signal output terminal, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a hiccup protection circuit according to the first aspect of the present invention; the power supply chip is applied to a switching power supply or a linear power supply; the eleventh resistor is a load; the first input end of the hiccup protection circuit is connected to a tap position of the power input end after voltage division through the eighth resistor and the ninth resistor; the second input end of the hiccup protection circuit is connected to a tap of the power supply output end passing through a tenth resistor and an eleventh resistor; the third input end of the hiccup protection circuit is connected with the power supply output end Vout; the enable signal output end of the hiccup protection circuit is connected to an enable pin EN of a power supply.
Specifically, if the enable pin of the power supply is not available, the enable signal output end of the hiccup protection circuit is connected to the G pole of the load switch.
The utility model provides a hiccup protection circuit, power chip, its circuit principle is simple reliable and stable, and the design of a plurality of D flip-flops time delay protection is more accurate to the judgement of circuit trouble, can improve the anti-interference characteristic of power simultaneously, improves the stability of system, and the joining of hiccup mode makes the power can restart automatically, need not artificial intervention and can have the function of recovering automatically with reducing the manpower maintenance cost, has the effect of preventing the spurious triggering.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it is to be understood that the terms "first", "second", "third", "fourth", and the like are used merely for distinguishing between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless explicitly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "coupled" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (10)
1. A hiccup protection circuit comprising a protection main logic circuit for controlling power on and off, the protection main logic circuit comprising: a first delay circuit and a second delay circuit; the first delay circuit and the second delay circuit respectively comprise N D flip-flops, wherein N is an element of {1,2,3 …, i }, and i is a positive integer; for the D triggers belonging to the same delay circuit, the Nth D trigger is connected with the (N + 1) th D trigger;
when N is equal to 1, the CP trigger of the first D trigger is used for inputting pulse signals, and the D end of the first D trigger are connected with the D end of the first D trigger
Terminal connectionThe Q end of the first D trigger is connected with the CP trigger delay of the second D trigger;
when N is larger than 1 and smaller than i, the CP trigger delay of the Nth D trigger is connected with the Q end of the (N-1) th D trigger; d end of the Nth D trigger and the D end of the Nth D trigger
End connection; the Q end of the Nth D trigger is connected with the CP trigger delay of the (N + 1) th D trigger;
when N is equal to i, the CP trigger delay of the ith D trigger is connected with the Q end of the (N-1) th D trigger; the D end of the ith D trigger and the D end of the ith D trigger
End connection; and the Q end of the ith D flip-flop is used for outputting a pulse signal.
2. The hiccup protection circuit of claim 1, wherein the protection master logic circuit further comprises: the load overcurrent protection circuit comprises an IOVP input end for receiving an input voltage indication signal, an OOVP input end for receiving an output voltage indication signal, an OCP input end for receiving a load overcurrent indication signal, a pulse signal input end, a starting signal input end, an enabling signal output end, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a first inverter, a second inverter, a third inverter and an RS trigger;
the IOVP input end, the OOVP input end and the OCP input end are respectively connected with the three input ends of the first NAND gate; the output end of the first NAND gate is connected with the first input end of the third NAND gate; the output end of the third NAND gate is connected with the reset end of the first delay circuit; the second input end of the third NAND gate is connected with the output end of the second NAND gate; the output end of the first delay circuit is connected with the input end of the first phase inverter; the input end of the starting signal and the output end of the second delay circuit are respectively connected with two input ends of a second NAND gate; the reset end of the second delay circuit is connected with the output end of the RS trigger; the RS trigger is formed by cross connection of a fourth NAND gate and a fifth NAND gate; the input end of the RS trigger is respectively connected with the output ends of the first inverter and the second inverter; the output end of the RS trigger is connected with the input end of the third inverter; the output end of the third inverter is connected with the enable signal output end; the output end of the second NAND gate is respectively connected with the second input end of the third NAND gate and the input end of the second inverter.
3. The hiccup protection circuit of claim 1, comprising a clock generation circuit to generate a clock signal, the clock generation circuit comprising: the device comprises a first resistor, a voltage stabilizing diode, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier, a first reference voltage, a second reference voltage and a D trigger; a first delayer; a power supply output terminal; a pulse signal output terminal;
the first resistor and the voltage stabilizing diode are connected in series to divide voltage to form a reference source and are connected in parallel with the first capacitor; the source electrode of the first MOS tube is connected with the power supply output end; the grid electrode of the first MOS tube is respectively connected with the drain electrode of the first MOS tube and the grid electrode of the second MOS tube; the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with one end of the first resistor; the source electrode of the third MOS tube is connected with the common ground; the source electrode of the second MOS tube is connected with the power supply output end; the drain electrode of the second MOS tube is respectively connected with the drain electrode of the fourth MOS tube, one end of the second capacitor, the inverting port of the first operational amplifier and the non-inverting port of the second operational amplifier; the drain electrode of the fourth MOS tube and the other end of the second capacitor are respectively connected with the common ground; the grid electrode of the fourth MOS tube is connected with the output end of the delayer; the non-inverting port of the first operational amplifier is connected with a first reference voltage; the output end of the first operational amplifier is connected with the CP triggering edge of the D trigger; the inverting input end of the second operational amplifier is connected with a second reference voltage; the output end of the second operational amplifier is connected with the reset end of the D trigger; the input end of the D trigger is connected with a power supply; and the Q end of the D trigger is respectively connected with the input end of the time delay unit and the pulse signal output end.
4. The hiccup protection circuit of claim 1, wherein the hiccup protection circuit further comprises a voltage comparison circuit; the voltage comparison circuit includes a first module for representing an indication of an overvoltage of an input voltage; the first module includes: the voltage regulator comprises a VI _ SMP input end, a second resistor, a third resistor, a first comparator, a fifth MOS (metal oxide semiconductor) transistor, a sixth MOS transistor, a third reference voltage, a fourth reference voltage, a second delayer and a fourth inverter; an IOVP output terminal;
the VI _ SMP input end is connected with a non-inverting input port of the first comparator, and is connected in series through a second resistor and a third resistor to divide voltage; the source electrode of the fifth MOS tube is connected with the third reference voltage, the drain electrode of the fifth MOS tube is connected with the inverted input port of the first comparator, and the grid electrode of the fifth MOS tube is connected with the IOVP output end; the source electrode of the sixth MOS tube is connected with a fourth reference voltage, the drain electrode of the sixth MOS tube is connected with the inverted input port of the first comparator, the grid electrode of the sixth MOS tube is connected with the output end of the fourth phase inverter, and the IOVP output end is connected with the input end of the fourth phase inverter; the input end of the second delayer is connected with the output end of the first comparator; the output end of the second delayer is connected with the IOVP output end.
5. The hiccup protection circuit of claim 4, wherein the voltage comparison circuit further comprises a second module for representing an output voltage over-voltage indication; the second module includes: the voltage regulator comprises a VO _ SMP input end, a fourth resistor, a fifth resistor, a second comparator, a third delayer, a seventh MOS (metal oxide semiconductor) tube, an eighth MOS tube, a fifth reference voltage, a sixth reference voltage and a fifth inverter;
the VO _ SMP input end is connected with the non-inverting input port of the second comparator, and voltage division is performed through the series connection of a fourth resistor and a fifth resistor; the source electrode of the seventh MOS tube is connected with the fifth reference voltage; the drain electrode of the seventh MOS tube is connected with the inverted input port of the second comparator; the grid electrode of the seventh MOS tube is connected with the OOVP output end; the source electrode of the eighth MOS tube is connected with a sixth reference voltage; the drain electrode of the eighth MOS tube M4 is connected with the inverting input port of the second comparator; the gate of the eighth MOS transistor M4 is connected to the output end of the fifth inverter; the OOVP output end is connected with the input end of the fifth inverter; the input end of the third delayer is connected with the output end of the second comparator; and the output end of the third delayer is connected with the OOVP output end.
6. The hiccup protection circuit of claim 4, wherein the voltage comparison circuit further comprises a third module for representing an indication of a load over-current voltage; the third module includes: the third operational amplifier is connected with the fourth comparator, the ninth MOS tube, the tenth MOS tube, the seventh reference voltage, the eighth reference voltage, the sixth inverter and the fourth delayer;
the C _ SMP input end is connected with the non-inverting input end of the third operational amplifier; the output end of the third operational amplifier is connected with the inverting input end of the third operational amplifier and the homodromous input port of the third comparator respectively after being connected with a sixth resistor and a seventh resistor in series for voltage division; the source electrode of the ninth MOS tube is connected with a seventh reference voltage; the drain electrode of the ninth MOS tube is connected with the reverse input port of the third comparator; the grid electrode of the ninth MOS tube is connected with the OCP output end; the source electrode of the tenth MOS tube is connected with the eighth reference voltage; the drain electrode of the tenth MOS tube is connected with the reverse input port of the third comparator; the grid electrode of the tenth MOS tube is connected with the output end of the fifth inverter; the output end of the OCP is connected with the input end of the sixth inverter; the input end of the fourth delayer is connected with the output end of the third comparator; and the output end of the third delayer is connected with the OCP output end.
7. The hiccup protection circuit of claim 3, wherein the clock generation circuit controls the second capacitor to charge and discharge through a Q terminal of a D flip-flop.
8. The hiccup protection circuit of claim 1, wherein the delay period of the first delay circuit and the second delay circuit is milliseconds or seconds.
9. A power supply chip comprising a load switch, a power input, a power output, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and the hiccup protection circuit of any one of claims 1 to 8; the power supply chip is applied to a switching power supply or a linear power supply; the eleventh resistor is a load; the first input end of the hiccup protection circuit is connected to a tap position of the power input end after voltage division through the eighth resistor and the ninth resistor; the second input end of the hiccup protection circuit is connected to a tap of the power supply output end passing through a tenth resistor and an eleventh resistor; the third input end of the hiccup protection circuit is connected with the power supply output end; the enable signal output end of the hiccup protection circuit is connected to an enable pin of a power supply.
10. The power supply chip of claim 9, wherein the enable signal output terminal of the hiccup protection circuit is connected to the G pole of the load switch without an enable pin of the power supply.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121058069.1U CN214958665U (en) | 2021-05-17 | 2021-05-17 | Hiccup protection circuit, power chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121058069.1U CN214958665U (en) | 2021-05-17 | 2021-05-17 | Hiccup protection circuit, power chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113991611A (en) * | 2021-12-03 | 2022-01-28 | 阳光电源股份有限公司 | Switching power supply and protection circuit thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113991611A (en) * | 2021-12-03 | 2022-01-28 | 阳光电源股份有限公司 | Switching power supply and protection circuit thereof |
| CN113991611B (en) * | 2021-12-03 | 2024-04-12 | 阳光电源股份有限公司 | Switch power supply and protection circuit thereof |
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