CN214851134U

CN214851134U - Single-pin crystal oscillator circuit with bidirectional amplitude limitation

Info

Publication number: CN214851134U
Application number: CN202120686602.2U
Authority: CN
Inventors: 徐华超
Original assignee: Guangzhou Ankai Microelectronics Co ltd
Current assignee: Guangzhou Ankai Microelectronics Co ltd
Priority date: 2021-04-02
Filing date: 2021-04-02
Publication date: 2021-11-23
Anticipated expiration: 2031-04-02

Abstract

The utility model relates to a single-pin crystal oscillator circuit with bidirectional amplitude limitation, which comprises an oscillation module, a first amplitude limiting module and a second amplitude limiting module, wherein the oscillation module is electrically connected with a power supply module; a first oscillation node of the oscillation module is electrically connected with the first amplitude limiting module, and a second oscillation node of the oscillation module is electrically connected with the second amplitude limiting module; the first amplitude limiting module is used for limiting the amplitude of the first oscillation node by a first amplitude, and the second amplitude limiting module is used for limiting the amplitude of the second oscillation node by a second amplitude. The utility model provides a thereby traditional single pin crystal oscillator amplitude's maximum value restrict in mains voltage bring big power noise injection and minimum be far below VSS thereby bring frequently trigger ESD protection circuit and easily lead to the problem that the chip burns out, and circuit structure is simple, and the area is less, can wide application in the nervous SoC design of pin, has satisfied the practical application demand.

Description

Single-pin crystal oscillator circuit with bidirectional amplitude limitation

Technical Field

The utility model relates to an integrated circuit designs technical field, especially relates to a single pin crystal oscillator circuit of two-way amplitude restriction.

Background

The crystal oscillator is one of the essential components of a digital integrated circuit, can be equivalent to a reactive element, and has an extremely high quality factor. When the quartz crystal is connected into a circuit, the quartz crystal can be matched with a capacitor or an inductor to form a capacitor three-point oscillator or an inductor three-point oscillator. At present, a crystal oscillator in an integrated circuit usually adopts a capacitance three-point structure, mainly because the area of an on-chip inductor is large, the area of a capacitor is small and the quality factor is high.

However, the maximum value of the low oscillation amplitude node oscillation signal of the basic type single-pin crystal oscillator is limited by the power supply voltage, so that the power supply noise may deteriorate the phase noise to a large extent; the minimum value of the oscillation signal of the high oscillation amplitude node is only limited indirectly by VSS, but the minimum value of the oscillation signal of the high oscillation amplitude node is far lower than VSS, so that an ESD circuit is frequently triggered, and latch-up is easy to occur.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problem, the present invention provides a two-way amplitude limitation circuit capable of realizing oscillation signals, so that the oscillator circuit obtains better power supply rejection characteristics, and the single-pin crystal oscillator circuit of the two-way amplitude limitation which does not lead to chip failure is provided.

A single-pin crystal oscillator circuit with bidirectional amplitude limitation comprises an oscillation module, a first amplitude limiting module and a second amplitude limiting module, wherein the oscillation module, the first amplitude limiting module and the second amplitude limiting module are electrically connected with a power supply module; a first oscillation node of the oscillation module is electrically connected with the first amplitude limiting module, and a second oscillation node of the oscillation module is electrically connected with the second amplitude limiting module; the first amplitude limiting module is used for limiting the amplitude of the first oscillation node by a first amplitude, and the second amplitude limiting module is used for limiting the amplitude of the second oscillation node by a second amplitude.

Additionally, according to the utility model provides a single pin crystal oscillator circuit of two-way amplitude restriction can also have following additional technical characterstic:

furthermore, the power supply module comprises a first current source, a second current source and a third current source which are respectively electrically connected with the power output end.

Furthermore, the oscillation module comprises a PMOS (P-channel metal oxide semiconductor) transistor, a crystal, a bias resistor, a first capacitor and a second capacitor;

the source end and the body end of the PMOS tube are electrically connected with the output end of the third current source, the second end of the first capacitor and the first end of the second capacitor, the first end of the first capacitor, the second end of the bias resistor and the gate end of the PMOS tube are electrically connected with the first end of the crystal, and the second end of the crystal, the drain end of the PMOS tube and the second end of the second capacitor are grounded.

Further, a second end of the bias resistor, a gate end of the PMOS transistor, and a first end of the crystal form a first oscillation node of the oscillation module, and a second end of the first capacitor, a first end of the second capacitor, and a source end of the PMOS transistor form a second oscillation node of the oscillation module.

Further, the first clipping module includes a first clipping unit and a second clipping unit.

Furthermore, the first amplitude limiting unit comprises a first NMOS transistor and a second NMOS transistor;

the drain end and the gate end of the first NMOS tube are electrically connected with the output end of the first current source, the gate end of the second NMOS tube is electrically connected with the gate end of the first NMOS tube, the source end and the body end of the first NMOS tube and the drain end and the body end of the second NMOS tube are grounded, and the source end of the second NMOS tube is electrically connected with the first oscillation node.

Further, the second amplitude limiting unit comprises a third NMOS transistor;

the drain terminal of the third NMOS tube and the first terminal of the bias resistor are respectively electrically connected with the output terminal of the second current source, and the source terminal and the body terminal of the third NMOS tube are grounded.

Further, the second amplitude limiting module comprises a fourth NMOS transistor and a fifth NMOS transistor;

the grid end of the fifth NMOS tube is electrically connected with the first oscillation node, the drain end of the fifth NMOS tube is electrically connected with the second oscillation node, the source end of the fifth NMOS tube is electrically connected with the grid end and the drain end of the fourth NMOS tube, and the body end of the fifth NMOS tube and the body end and the source end of the fourth NMOS tube are grounded.

Further, the power supply module comprises a reference current source and a power supply which are electrically connected with the PMOS current mirror.

Furthermore, the PMOS current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, where source terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are used as input terminals and electrically connected to the power supply, drain terminals are used as output terminals, and gates are connected to each other.

According to the utility model provides a single pin crystal oscillator circuit of two-way amplitude restriction, including the oscillation module, first amplitude limiting module and the second amplitude limiting module that are connected with the power module electricity; a first oscillation node of the oscillation module is electrically connected with the first amplitude limiting module, and a second oscillation node of the oscillation module is electrically connected with the second amplitude limiting module; the first amplitude limiting module is used for limiting the amplitude of the first oscillation node by a first amplitude, and the second amplitude limiting module is used for limiting the amplitude of the second oscillation node by a second amplitude. The utility model can realize the bidirectional amplitude limitation of the oscillation signal, so that the oscillator circuit can obtain better power supply inhibition characteristic and the chip can not fail; the problem that the maximum value of the low-oscillation amplitude node oscillation signal of the conventional crystal oscillator is limited by the power supply voltage is solved, so that the power supply noise can deteriorate the phase noise to a greater extent; the minimum value of the oscillation signal of the node with the high oscillation amplitude can only be limited indirectly by VSS, but the minimum value of the oscillation signal of the node with the high oscillation amplitude is far lower than VSS, so that the ESD circuit is frequently triggered, the latch-up effect is easily caused, and the practical application requirement is met.

Drawings

Fig. 1 is a block diagram of a bidirectional amplitude-limited single-pin crystal oscillator circuit according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a bi-directional amplitude-limited single-pin crystal oscillator circuit according to an embodiment of the present invention;

fig. 3 is a circuit diagram of a bi-directional amplitude-limited single-pin crystal oscillator circuit according to another embodiment of the present invention.

The following detailed description of the invention will be further described in conjunction with the above-identified drawings.

Detailed Description

In order to make the objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Several embodiments of the invention are given in the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are for illustrative purposes only and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The maximum value of the low oscillation amplitude node oscillation signal of the existing basic single-pin crystal oscillator is limited by the power supply voltage, so that the power supply noise can deteriorate the phase noise to a greater extent; the minimum value of the oscillation signal of the high oscillation amplitude node is only limited indirectly by VSS, but the minimum value of the oscillation signal of the high oscillation amplitude node is far lower than VSS, so that an ESD circuit is frequently triggered, and latch-up is easy to occur.

As shown in fig. 1 to 2, based on the above problem, an embodiment of the present invention discloses a single-pin crystal oscillator circuit with bidirectional amplitude limitation, including an oscillation module 20 electrically connected to a power supply module 10, a first amplitude limiting module 30 and a second amplitude limiting module 40, the power supply module 10 is used for supplying energy to the oscillation circuit.

Specifically, a first oscillation node a of the oscillation module 20 is electrically connected to the first amplitude limiting module 30, and a second oscillation node B of the oscillation module 20 is electrically connected to the second amplitude limiting module 40. The first amplitude limiting module 30 is configured to perform a first amplitude limitation on the amplitude of the first oscillation node a, and the second amplitude limiting module 40 is configured to perform a second amplitude limitation on the amplitude of the second oscillation node B. The first oscillation node A is a high oscillation amplitude node, and the node is connected to a chip pin; the second oscillation node B is a low oscillation amplitude node.

Further, the power supply module 10 includes a first current source IB1, a second current source IB2 and a third current source IB3 electrically connected to the power supply VDD output terminal, respectively, for providing a bias current to the oscillation circuit. The end of the current source connected to VDD is defined as an input end, i.e., an input end, and the other end is an output end, i.e., an output end.

Further, the oscillation module 20 includes a PMOS transistor MP, a crystal, a bias resistor R1, a first capacitor C1, and a second capacitor C2.

A source end and a body end of the PMOS transistor MP are electrically connected to an output end of the third current source IB3, a second end of the first capacitor C1, and a first end of the second capacitor C2, a first end of the first capacitor C1, a second end of the bias resistor R1, and a gate end of the PMOS transistor MP are electrically connected to a first end of the crystal, and a second end of the crystal, a drain end of the PMOS transistor MP, and a second end of the second capacitor C2 are grounded. The first end and the second end of the bias resistor R1, the first capacitor C1 and the second capacitor C2 are defined from left to right and from top to bottom, that is, the left end and the upper end are the upper plate of the capacitor, and the right end and the lower end are the lower plate of the capacitor.

Specifically, the second end of the bias resistor R1, the gate end of the PMOS transistor MP, and the first end of the crystal form a first oscillation node a of the oscillation module 20, and the second end of the first capacitor C1, the first end of the second capacitor C2, and the source end of the PMOS transistor MP form a second oscillation node B of the oscillation module 20. The access mode of the crystal is that one end of the crystal is accessed to a node A in the chip through a bonding pad, and the other end of the crystal is connected to the ground. In addition, the resistor and the capacitor in this embodiment are two-terminal devices, and may be three-terminal devices in practice.

Further, the first clipping module 30 includes a first clipping unit 31 and a second clipping unit 32.

Specifically, the first clipping unit 31 includes a first NMOS transistor MN1 and a second NMOS transistor MN 2. The drain end and the gate end of the first NMOS tube MN1 are both electrically connected with the output end of the first current source IB1, the gate end of the second NMOS tube MN2 is electrically connected with the gate end of the first NMOS tube MN1, the source end and the body end of the first NMOS tube MN1 and the drain end and the body end of the second NMOS tube MN2 are grounded VSS, and the source end of the second NMOS tube MN2 is electrically connected with the first oscillation node A.

Specifically, the second clipping unit includes a third NMOS transistor MN 3. The drain terminal of the third NMOS transistor MN3 and the first terminal of the bias resistor are electrically connected to the output terminal of the second current source IB2, respectively, and the source terminal and the body terminal of the third NMOS transistor MN3 are grounded.

Further, the second clipping module 40 includes a fourth NMOS transistor MN4 and a fifth NMOS transistor MN 5.

A gate terminal of the fifth NMOS transistor MN5 is electrically connected to the first oscillation node, a drain terminal of the fifth NMOS transistor MN5 is electrically connected to the second oscillation node B, a source terminal of the fifth NMOS transistor MN5 is electrically connected to a gate terminal and a drain terminal of the fourth NMOS transistor MN4, and a body terminal of the fifth NMOS transistor MN5 and a body terminal and a source terminal of the fourth NMOS transistor MN4 are grounded.

Specifically, when the first current source IB1, the second current source IB2 and the third current source IB3 are correctly activated, the first current source IB1 injects a current into the first NMOS transistor MN1, the second current source IB2 injects a current into the third NMOS transistor MN3 to generate the bias voltage VB, and the third current source IB3 injects a current into the PMOS transistor MP.

After power-on, the DC operating point of the circuit is established. Since the voltage of the first oscillation node a is necessarily greater than 0, the drain terminal of the second NMOS transistor MN2 is connected to VSS, and although the current of the first current source IB1 flows through the first NMOS transistor MN1, the second NMOS transistor MN2, the drain terminal of which is connected to VSS, has no dc current. And normally, the capacitor and the crystal have no leakage current, and the gate ends of the PMOS transistor MP and the fifth NMOS transistor MN5 have no leakage current. Therefore, the first oscillation node a does not flow any dc current into the first capacitor C1, the crystal (XTAL), the PMOS transistor MP, the fifth NMOS transistor MN5 or the second NMOS transistor MN2, i.e., there is no dc voltage drop across the bias resistor R1, and the dc voltage at the first oscillation node a is equal to VB. The gate voltage of the PMOS transistor MP is VB, the PMOS transistor MP flows the dc current generated by the third current source IB3, the drain terminal of the PMOS transistor MP is connected to VSS, so that the PMOS transistor MP operates in the saturation region, the dc voltage of the second oscillation node B is determined to be VB + VGSP, where VGSP is the gate-source voltage of the PMOS transistor MP. VB is the gate-source voltage VGSN3 of the third NMOS transistor MN3, which is connected to the gate terminal of the fifth NMOS transistor MN5, but a diode-connected fourth NMOS transistor MN4 is between the source terminal of the fifth NMOS transistor MN5 and the ground, so that there is no dc current in the fifth NMOS transistor MN5 and the fourth NMOS transistor MN 4.

Under the current initial bias condition, the current source is started, and the maximum value of the sine signal of the oscillator is slowly increased, namely, the gate terminal voltage of the fifth NMOS transistor MN5 is gradually increased, namely, the difference between the gate terminal voltage and VB is larger and larger. When the maximum value reaches or approaches to the sum of the gate-source voltage VGSN4 of the fourth NMOS transistor MN4 and the gate-source voltage VGSN5 of the fifth NMOS transistor MN5, the fifth NMOS transistor MN5 and the fourth NMOS transistor MN4 rapidly enter a saturation region from a cut-off region, a large current for VSS flows in the fifth NMOS transistor MN5 and the fourth NMOS transistor MN4, and the current flows from the second oscillation node B, that is, the voltage of the second oscillation node B is pulled down by the fifth NMOS transistor MN5 and the fourth NMOS transistor MN4, which can also be understood as to drain the current of the third current source IB3, so as to reduce the injection energy, and the oscillator does not have enough energy to maintain the amplitude to be further increased.

In summary, when the maximum value of the sinusoidal signal of the first oscillation node a reaches VGSN5+ VGSN4, the oscillator amplitude is limited to increase further, i.e. to reach a forward amplitude limit. In the opposite direction, as time increases, the minimum value of the sinusoidal signal of the first oscillation node a of the oscillator gradually decreases and approaches VSS, when the voltage of the first oscillation node a reaches VSS, that is, the source terminal voltage of the second NMOS transistor MN2 is VSS, at this time, although the gate-source voltage of the second NMOS transistor MN2 is equal to the gate-source voltage of the first NMOS transistor MN1, the drain terminal of the second NMOS transistor MN2 is connected to VSS, and the drain terminal voltage of the second NMOS transistor MN2 is VSS-VSS 0, so that the second NMOS transistor MN2 still operates in the deep linear region, and almost no current flows through the second NMOS transistor MN 2.

Further, when the voltage of the first oscillation node a further decreases and passes through VSS, at this time, the gate-source voltage of the second NMOS transistor MN2 is greater than the gate-source voltage of the first NMOS transistor MN1, the drain-source voltage of the second NMOS transistor MN2 starts to turn to a positive value, the second NMOS transistor MN2 starts to enter a conducting state, and a current is injected from VSS to the first oscillation node a. The first oscillation node a receives current injection in the direction of the node a, the voltage of the first oscillation node a is raised instantly, but the oscillator itself has a tendency of increasing in negative amplitude, and when the two voltage increments reach equilibrium, the voltage of the first oscillation node a reaches a minimum value, that is, reaches the negative amplitude limit. And normally the negative amplitude is slightly below VSS, but the absolute value of the difference from VSS is much less than one diode drop, and therefore does not trigger a reverse biased diode in the ESD circuit.

It can be understood that the maximum value of the sinusoidal signal of the first oscillation node a of the oscillator is limited by the fifth NMOS transistor MN5 and the fourth NMOS transistor MN4, rather than being limited by the third current source IB3 entering the linear region, and the third current source IB3 is always in the saturation region, so that the influence of the power supply noise is reduced as much as possible; the minimum value of the sinusoidal signal of the first oscillation node A of the oscillator is limited by the first NMOS tube MN1 and the second NMOS tube MN2, but the limitation is not carried out when the second oscillation node B is reduced to be close to VSS, the minimum value of the voltage of the first oscillation node A is inevitably caused to be far lower than VSS when the second oscillation node B is reduced to be close to VSS, so that an ESD circuit is triggered, and the negative amplitude limiting circuit formed by the first NMOS tube MN1 and the second NMOS tube MN2 avoids the risk that the ESD circuit is frequently triggered and protected, so that a latch-up effect is caused, and chips are burnt. The problem of the maximum value of traditional single pin crystal oscillator amplitude be restricted in the mains voltage thus bring big power noise injection and the minimum value is far below VSS thereby bring frequently to trigger ESD protection circuit and easily lead to the chip to burn out is solved, circuit structure is simple, and the area is less, easily realizes, can wide application in the nervous SoC design of pin.

Referring to fig. 3, in another embodiment, the power supply module includes a reference current source IREF electrically connected to the PMOS current mirror and a power supply VDD.

The PMOS current mirror comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3 and a fourth PMOS tube MP4, the source ends of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube and the MP3, the fourth PMOS tube MP4 are used as input ends and are electrically connected with the power supply VDD, the drain ends are used as output ends, and grid electrodes are mutually connected.

Specifically, IREF is a reference current, typically generated by a bandgap reference circuit; MP1, MP2, MP3 and MP4 form a PMOS current mirror. MP2 is equivalent to IB1 of FIG. 2, the outflow end of IB1 is the drain end of MP2, and the inflow end of IB1 is the source end of MP 2; MP3 is equivalent to IB2 of FIG. 2, the outflow end of IB2 is the drain end of MP3, and the inflow end of IB2 is the source end of MP 3; MP4 is equivalent to IB3 of fig. 2, the outflow end of IB3 is the drain end of MP4, and the inflow end of IB3 is the source end of MP 4. IREF flows through diode-connected MP1, so the current for MP1 is IREF. The gate terminals of MP1, MP2, MP3 and MP4 are interconnected, and the body terminal and the source terminal are both connected to the power supply VDD, so if different currents need to be set to flow through MP2, MP3 and MP4, only MP2, MP3 and MP4 with different aspect ratios need to be set. One end of the crystal XTAL is connected with the first oscillation node A, and the other end is connected with a reference ground VSS.

It should be noted that the circuit configuration of fig. 3 is only one implementation of the general configuration of fig. 2. In fact, there are many implementations that can be the subject of protection.

The utility model provides a single-pin crystal oscillator circuit with bidirectional amplitude limitation, which comprises an oscillation module, a first amplitude limiting module and a second amplitude limiting module, wherein the oscillation module is electrically connected with a power supply module; a first oscillation node of the oscillation module is electrically connected with the first amplitude limiting module, and a second oscillation node of the oscillation module is electrically connected with the second amplitude limiting module; the first amplitude limiting module is used for limiting the amplitude of the first oscillation node by a first amplitude, and the second amplitude limiting module is used for limiting the amplitude of the second oscillation node by a second amplitude. The utility model discloses can realize oscillating signal's two-way amplitude restriction, make the oscillator circuit obtain better power suppression characteristic, and can not lead to the chip inefficacy, solve the low oscillation amplitude node oscillating signal's of current crystal oscillator maximum value by mains voltage restriction, thereby power noise can worsen phase noise to a great extent; the minimum value of the oscillation signal of the node with the high oscillation amplitude can only be limited indirectly by VSS, but the minimum value of the oscillation signal of the node with the high oscillation amplitude is far lower than VSS, so that the ESD circuit is frequently triggered, the latch-up effect is easily caused, and the practical application requirement is met.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A single-pin crystal oscillator circuit with bidirectional amplitude limitation is characterized by comprising an oscillation module, a first amplitude limiting module and a second amplitude limiting module, wherein the oscillation module, the first amplitude limiting module and the second amplitude limiting module are electrically connected with a power supply module; a first oscillation node of the oscillation module is electrically connected with the first amplitude limiting module, and a second oscillation node of the oscillation module is electrically connected with the second amplitude limiting module; the first amplitude limiting module is used for limiting the amplitude of the first oscillation node by a first amplitude, and the second amplitude limiting module is used for limiting the amplitude of the second oscillation node by a second amplitude.

2. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 1, wherein the power supply module includes a first current source, a second current source, and a third current source electrically connected to the power output, respectively.

3. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 2, wherein the oscillation module comprises a PMOS transistor, a crystal, a bias resistor, a first capacitor, and a second capacitor;

4. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 3, wherein the second terminal of the bias resistor, the gate terminal of the PMOS transistor, and the first terminal of the crystal form a first oscillation node of the oscillation module, and the second terminal of the first capacitor, the first terminal of the second capacitor, and the source terminal of the PMOS transistor form a second oscillation node of the oscillation module.

5. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 4, wherein the first clipping module comprises a first clipping unit and a second clipping unit.

6. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 4, wherein the first clipping unit comprises a first NMOS transistor and a second NMOS transistor;

7. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 5, wherein the second clipping unit comprises a third NMOS transistor;

8. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 6, wherein the second clipping module comprises a fourth NMOS transistor and a fifth NMOS transistor;

9. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 1, wherein the power supply module comprises a reference current source and a power supply electrically connected to a PMOS current mirror.

10. The bi-directional amplitude-limited single-pin crystal oscillator circuit of claim 9, wherein the PMOS current mirror comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, wherein source terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are electrically connected to the power supply as input terminals, drain terminals are output terminals, and gates are connected to each other.