CN214799602U

CN214799602U - Video processor supporting 12G SDI input and output

Info

Publication number: CN214799602U
Application number: CN202120660467.4U
Authority: CN
Inventors: 胡宏清; 王海洋; 潘东阳
Original assignee: Xiamen Rgblink Science & Technology Co ltd
Current assignee: Xiamen Rgblink Science & Technology Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-11-19
Anticipated expiration: 2031-03-31

Abstract

A video processor supporting 12G SDI input and output comprises an FPGA module, a buffer module, a 12G SDI input module and a 12G SDI output module; the 12G SDI input module is used for inputting 12G SDI signals; the FPGA module is internally provided with a decoding module and an encoding module, and the decoding module is connected with the 12G SDI input module and is used for decoding the input 12G SDI signal; the FPGA module is connected with the cache module and is matched with the cache module to process the decoded 12G SDI signal; the coding module is used for coding the processed 12G SDI signal; and the 12G SDI output module is connected with the coding module and used for outputting the coded 12G SDI signal. The utility model discloses designed 12G SDI input module, 12G SDI output module and decoding module and coding module in video processor, can make video processor can support the input and the output of 12G SDI.

Description

Video processor supporting 12G SDI input and output

Technical Field

The utility model relates to an audio and video processing field, concretely relates to support video processor of 12G SDI input and output.

Background

The LED full-color display screen application is characterized in that a gigabit network-based control system with separated sending card and receiving card is created by Lingxing rain science and technology development limited company in Shenzhen, 2005, the form of the control system is popular among industry applications and manufacturers, and the control system becomes a standard product application form. The LED video processor gradually becomes a standard matched product of an LED full-color display screen from the first commercial product in 2006 to market along with the development of the industry to 2014.

A full-color LED multi-picture video image processor is high-performance image processing and control equipment aiming at full-color LEDs, which is introduced by high and new technology enterprises in China. The equipment integrates years of rich experience in aspects of video image processing, high-definition signal processing, display and the like, adopts the design of patent technology hardware, combines the special requirement design of full-color LED screen display, can receive and process various different video graphic signals simultaneously, and displays on a full-color LED.

The 12G SDI is a transmission light facing 2160p × 60p (commonly called true 4K) applications, and directly transmits 4K audio and video. The refreshing of 60 frames of pictures per second has low cost, simple system and better guaranteed image quality. However, current video processors are generally only capable of processing 3G SDI signals. It is therefore desirable to provide a video processor capable of supporting 12G SDI signals.

SUMMERY OF THE UTILITY MODEL

To the problem that prior art exists, the utility model aims to provide a support 12G SDI input and output's video processor.

In order to achieve the above object, the utility model adopts the following technical scheme:

a video processor supporting 12G SDI input and output comprises an FPGA module, a buffer module, a 12G SDI input module and a 12G SDI output module;

the 12G SDI input module is used for inputting 12G SDI signals;

the FPGA module is internally provided with a decoding module and an encoding module, and the decoding module is connected with the 12G SDI input module and is used for decoding the input 12G SDI signal; the FPGA module is connected with the cache module and is matched with the cache module to process the decoded 12G SDI signal; the coding module is used for coding the processed 12G SDI signal;

and the 12G SDI output module is connected with the coding module and used for outputting the coded 12G SDI signal.

The decoding module is composed of a decoding chip M21324 and peripheral circuits of the decoding chip M21324.

The coding module is composed of a decoding chip M23428 and peripheral circuits of the decoding chip M23428.

After the scheme is adopted, the utility model discloses 12G SDI input module and 12G SDI output module have been designed in video processor to set up corresponding decoding module and coding module in the FPGA module, make video processor can acquire 12G SDI signal, and handle it, can export the signal after handling simultaneously and use in other equipment. Due to the design of the 12G SDI input module, the 12G SDI output module, and the decoding and encoding modules, the video processor may be enabled to support input and output of the 12G SDI.

Drawings

Fig. 1 is a schematic block diagram of a video processor according to the present invention;

fig. 2 is a schematic circuit diagram of the decoding module of the present invention;

fig. 3 is a schematic circuit diagram of the encoding module of the present invention.

Description of reference numerals:

an FPGA module 10; a decoding module 11; an encoding module 12; a cache module 20; a 12G SDI input module 30; and a 12G SDI output module 40.

Detailed Description

As shown in fig. 1, the utility model relates to a support video processor of 12G SDI input/output, it includes FPGA module 10, buffer module 20, 12G SDI input module 30 and 12G SDI output module 40.

The 12G SDI input module 30 is used for inputting a 12G SDI signal. The 12G SDI output module 40 is connected to the encoding module 12, and configured to output the encoded 12G SDI signal, so that the 12G SDI signal processed by the video processor enters a back-end device for application.

The FPGA module 10 is mainly used for processing 12G SDI signals, but the processed signals must be decoded, and the processed signals need to be encoded again for transmission. Therefore, the decoding module 11 and the encoding module 12 are disposed in the FPGA module 10. The decoding module 11 is connected to the 12G SDI input module 30, and configured to perform decoding processing on the input 12G SDI signal. The 12G SDI signal input to the video processor is decoded to obtain a decoded 12G SDI signal. At this time, the FPGA module 10 cooperates with the buffer module 20 to process the decoded 12G SDI signal. The processing is performed according to the environment and requirements of the video processor, and the operations involved in the processing can adopt the existing related technology. After the FPGA module 10 performs data processing, the encoding module 12 encodes the processed 12G SDI signal so as to transmit the processed 12G SDI signal in the following.

As shown in fig. 2 and 3, the decoding module includes a decoding chip M21324 and peripheral circuits of the decoding chip M21324. The coding module is composed of a decoding chip M23428 and peripheral circuits of the decoding chip M23428.

To sum up, the utility model discloses 12G SDI input module 30 and 12G SDI output module 40 have been designed in video processor to set up corresponding decoding module and coding module in the FPGA module, make video processor can acquire 12G SDI signal, and handle it, can export the signal after handling simultaneously and use in other equipment. Due to the design of the 12G SDI input module, the 12G SDI output module, and the decoding and encoding modules, the video processor may be enabled to support input and output of the 12G SDI.

The above description is only an embodiment of the present invention, and is not intended to limit the technical scope of the present invention, so that any slight modifications, equivalent changes and modifications made by the technical spirit of the present invention to the above embodiments are all within the scope of the technical solution of the present invention.

Claims

1. A video processor supporting 12G SDI input and output, comprising: the device comprises an FPGA module, a cache module, a 12G SDI input module and a 12G SDI output module;

the 12G SDI input module is used for inputting 12G SDI signals;

2. The video processor of claim 1, wherein the video processor is configured to support 12G SDI input and output: the decoding module is composed of a decoding chip M21324 and peripheral circuits of the decoding chip M21324.

3. The video processor of claim 1, wherein the video processor is configured to support 12G SDI input and output: the coding module is composed of a decoding chip M23428 and peripheral circuits of the decoding chip M23428.