CN214795614U - X86 platform sequential control device - Google Patents

Abstract

The embodiment of the utility model discloses X86 platform sequential control device, include: the device comprises a standing power supply module, a basic power supply power-on indicating module, a starting signal acquiring module, a standing power supply module and a non-core power supply power-on indicating module; the input end of the stock power supply module is connected with a power supply, the basic power supply power-on indicating module is connected with the output end of the stock power supply module, and the basic power supply power-on indicating module is used for sending a first indicating signal to the SOC of the X86 framework when the stock power supply module is completely powered on; after receiving the first indication signal, the SOC of the X86 architecture enables the emergency power supply module to be powered on when the power-on signal acquisition module acquires the power-on signal; the non-core power supply power-on indicating module is respectively connected with the basic power supply power-on indicating module and the spare power supply module and is used for indicating whether the X86 platform non-core power supply is completely powered on. The utility model discloses need not to use the programming chip can realize X86 platform power-on sequence control, effectively reduced the development cycle of platform.

Description

X86 platform sequential control device

Technical Field

The utility model relates to a power time sequence control field indicates a X86 platform time sequence control device very much.

Background

The information technology and communication industry is continuously developing, and the requirements on the performance and the function of equipment by a server, an industrial control terminal and a financial terminal are higher and more flexible. The development cost control requirements of products and the development cycle requirements of products are becoming stricter.

Most of the developed and used devices are X86 platforms, and the existing X86 platform terminal needs to use a professional EC (Embedded Controller) chip or a timing control chip such as a CPLD (Complex Programming logic device), an FPGA (Field Programmable gate array) and the like developed for the platform to control the power-on timing of the platform when the platform is powered on. Therefore, the method brings the disadvantages of high hardware material cost, inflexible printed circuit board line layout and wiring, more research and development resource investment and longer development period.

Disclosure of Invention

The to-be-solved technical problem of the utility model lies in providing an X86 platform sequential control device, need not to use the programming chip to realize going up electrical sequence control, has reduced the development time and the cost of platform.

The utility model discloses a realize like this:

an X86 platform timing sequence control device comprises a standing power supply module, a basic power supply power-on indication module, a starting signal acquisition module, a standing power supply module and a non-core power supply power-on indication module;

the input end of the standby power module is connected with a power supply, the basic power supply power-on indicating module is connected with the output end of the standby power module and used for indicating whether the standby power module is completely powered on, and when the standby power module is completely powered on, the basic power supply power-on indicating module sends a first indicating signal to the SOC of the X86 architecture; after receiving the first indication signal, the SOC of the X86 architecture enables the emergency power supply module to be powered on when the power-on signal acquisition module acquires a power-on signal; the non-core power supply power-on indicating module is respectively connected with the basic power supply power-on indicating module and the non-standby power supply module and is used for indicating whether the standby power supply module and the non-standby power supply module are completely powered on, and when the standby power supply module and the non-standby power supply module are completely powered on, the non-core power supply power-on indicating module sends a second indicating signal to the SOC of the X86 architecture;

the standby power supply module comprises a memory power supply module, a small-voltage detection module and a conventional standby power supply module, wherein the memory power supply module and the conventional standby power supply module are respectively connected with the non-core power supply power-on indication module, and the small-voltage power supply module is connected with the non-core power supply power-on indication module through the small-voltage detection module.

Further, the stock power supply module comprises a conventional stock power supply module and a power supply module which still needs to work in a deep sleep state, the conventional stock power supply module, the power supply module which still needs to work in the deep sleep state and the conventional non-stock power supply module respectively comprise a plurality of discrete power supply modules which are sequentially connected, and a delay module is connected between the two discrete power supply modules;

the input end of the first discrete power supply module of the stock power supply module is connected with a power supply, the last discrete power supply module of the stock power supply module is connected with the SOC of the X86 architecture, and when the last discrete power supply module of the stock power supply module is powered on, a third indicating signal is sent to the SOC of the X86 architecture; the input end of the first discrete power supply module of the power supply module still needing to work in the deep sleep state is connected with the SOC of the X86 architecture, when the SOC of the X86 architecture receives a third indication signal, the power supply module still needing to work in the deep sleep state is powered on, and the last discrete power supply module of the power supply module still needing to work in the deep sleep state is connected with the basic power supply power-on indication module; the input end of the first path of discrete power supply module of the conventional emergency power supply module is connected with the SOC of an X86 architecture, and the last path of discrete power supply module of the conventional emergency power supply module is connected with the non-core power supply power-on indication module.

Further, the delay module comprises a resistor R1, a capacitor C1 and a diode D1, wherein one end of the resistor R1 is connected with the input end, the other end of the resistor R1 is connected with the output end and is grounded through the capacitor C1, the cathode of the diode D1 is connected with the input end, and the anode of the diode D1 is connected with the output end.

Further, the discrete power module is a power module with a PG signal.

Further, the basic power supply power-on indication module includes a first and gate, where the first and gate receives a power-on signal of the last discrete power supply module of the conventional stock power supply module, a power supply working signal in the control deep sleep state of the SOC of the X86 architecture, and a power-on signal of the last discrete power supply module of the power supply module still needing to work in the deep sleep state, respectively, and then performs power-on indication of the basic power supply according to the received signals.

Further, the non-core power supply power-on indication module includes a second and gate, where the second and gate receives the first indication signal of the basic power supply power-on indication module, the power-on signal of the memory power supply module, the detection signal of the small voltage detection module, and the power-on signal of the conventional non-core power supply module, and then performs the non-core power supply power-on indication according to the received signals.

Further, the small-voltage power supply module includes: an NMOS transistor Q1, an NMOS transistor Q2, an NMOS transistor Q3, a resistor R4, a resistor R5, a resistor R6, a capacitor C2, a capacitor C3 and a capacitor C4;

the G pole of the NMOS transistor Q3 is connected with a VCCST _ EN enabling pin, the S pole of the NMOS transistor Q3 is grounded, and the D pole of the NMOS transistor Q3 is connected with a + V3.3A power supply through the resistor R5;

the G pole of the NMOS transistor Q2 is connected with the D pole of the NMOS transistor Q3, the S pole of the NMOS transistor Q2 is grounded, and the D pole of the NMOS transistor Q2 is connected with a + V5A power supply through the resistor R4;

the G pole of the NMOS transistor Q1 is connected to the D pole of the NMOS transistor Q2 and grounded via the resistor R6, the D pole of the NMOS transistor Q1 is connected to + VCC1P05_ SOC _ OUT power supply and grounded via the capacitor C2, and the S pole of the NMOS transistor Q1 is connected to + VCCST power supply and grounded via the capacitor C3 and the capacitor C4, respectively.

Further, the small voltage detection module includes: an NMOS transistor Q4, an NPN triode Q5, a resistor R7, a resistor R8 and a resistor R9;

the B pole of the NPN triode Q5 is connected with a + VCCST power supply through the resistor R9, the E pole of the NPN triode Q5 is grounded, and the C pole of the NPN triode Q5 is connected with a + V3.3A power supply through the resistor R8;

the G pole of the NMOS tube Q4 is connected with the C pole of the NPN triode Q5, the S pole of the NMOS tube Q4 is grounded, the D pole of the NMOS tube Q4 is connected with a + V3.3A power supply through the resistor R7, and the D pole of the NMOS tube Q4 is also connected with a VCCST _ PG pin.

The utility model has the advantages that:

1. the development of a time sequence control chip is omitted, the power-on time sequence control can be realized without using a programming chip, the development period of a platform is effectively reduced, and the product research and development time is shortened;

2. by designing the delay circuit and the small-voltage detection circuit, the material cost is reduced by about 20% compared with the cost of a time sequence control chip, and the material development cost of the platform is effectively reduced;

3. the conventional stock power supply module, the power supply module which still needs to work in a deep sleep state and the conventional non-stock power supply module adopt a discrete power supply scheme, all power supplies are in chain combination to achieve time sequence control, a control signal and the power supply do not need to be accumulated in one area like a time sequence control chip, the layout and wiring of the PCB can be realized according to the nearby wiring of the power supply module, and the layout and wiring difficulty of the PCB is effectively reduced;

4. by providing the separated time sequence control, the permanent power supplies and the non-permanent power supplies can be flexibly configured, and other power supplies which are not in the platform time sequence can be designed and configured in a special use scene, so that the aim of flexible control is fulfilled.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of an apparatus according to an embodiment of the present application;

FIG. 2 is a schematic timing control flow chart in an embodiment of the present application;

FIG. 3 is a circuit diagram of a delay circuit module according to an embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a low voltage power supply module according to an embodiment of the present application;

fig. 5 is a schematic circuit diagram of a small voltage detection module in an embodiment of the present application.

Detailed Description

The invention idea of the utility model is as follows:

by adopting a plurality of independent power supply modules, small-voltage power supply modules and detection circuits thereof and then utilizing a CPU and a south bridge (PCH) in the SOC of the X86 architecture to participate in time sequence control, the development of a time sequence control chip is omitted, and the power-on time sequence control of the X86 platform can be realized without using a programming chip. The soc (system on chip), i.e. the system on chip, also called the system on chip, refers to an integrated circuit with a dedicated target, which includes the complete system and has all the contents of the embedded software. In the present embodiment, the SOC mainly refers to an integrated chip in which a CPU and a PCH are integrated. In addition, the plurality of independent power modules comprise a stock power module which needs to be powered on before the power is started and a spare power module which is not required to be powered on after the power is started and is except a core power supply (comprising a core of the CPU and a display card power supply). Further, the standby power module can be divided into a power supply which needs to work in the deep sleep state (i.e. a power supply module which still needs to work in the deep sleep state) and other standby power supplies (i.e. a conventional standby power supply module) except the power supply which needs to work in the deep sleep state, the standby power module further comprises a memory power supply, a small-voltage power supply and other conventional standby power supplies (i.e. a conventional standby power supply module) except the former two, and in addition, due to the specificity of the small-voltage power supply detection, a small-voltage detection module is specially used for detecting the power-on condition of the small-voltage power supply.

Furthermore, because the conventional standby power module, the power module still needing to work in the deep sleep state and the conventional standby power module all comprise a plurality of power sources, in order to realize sequential power-on, a plurality of discrete power sources in chain connection can be adopted in the modules, and a delay module is connected between the two discrete power sources, so that the chain power-on of the plurality of power sources is realized.

Referring to fig. 1, an embodiment of the present application discloses an X86 platform timing control apparatus 100, which includes a standby power module 1, a basic power supply power-on indication module 2, a power-on signal acquisition module 3, a standby power module 4, and a non-core power supply power-on indication module 5;

the input end of the standby power module 1 is connected with a power supply, the basic power supply power-on indication module 2 is connected with the output end of the standby power module 1 and is used for indicating whether the standby power module 1 is completely powered on, and when the standby power module 1 is completely powered on, the basic power supply power-on indication module 2 sends a first indication signal to an SOC of an X86 architecture; after the SOC of the X86 architecture receives the first indication signal, when the boot signal acquiring module 3 acquires a boot signal, the SOC of the X86 architecture enables the emergency power supply module 4 to be powered on; the non-core power supply power-on indication module 5 is respectively connected with the basic power supply power-on indication module 2 and the emergency power supply module 4, and is used for indicating whether the emergency power supply module 1 and the emergency power supply module 4 are completely powered on, when the emergency power supply module 1 and the emergency power supply module 4 are completely powered on, the non-core power supply power-on indication module 5 sends a second indication signal to the SOC of the X86 architecture, and indicates that the non-core power supply of the X86 platform is completely powered on;

the emergency power supply module 4 comprises a memory power supply module 41, a small-voltage power supply module 42, a conventional emergency power supply module 43 and a small-voltage detection module 44, the memory power supply module 41 and the conventional emergency power supply module 43 are respectively connected with the non-core power supply electrifying indication module 5, and the small-voltage power supply module 42 is connected with the non-core power supply electrifying indication module 5 through the small-voltage detection module 44.

When a power supply is powered on, a stock power supply module 1 is powered on firstly, and after the stock power supply module 1 is completely powered on, a basic power supply power-on indication module 2 sends a first indication signal to an SOC of an X86 architecture; after the SOC of the X86 architecture receives the first indication signal, when the boot signal acquiring module 3 acquires a boot signal, the SOC of the X86 architecture enables the emergency power supply module 4 to be powered on; when the memory power module 41, the small-voltage power module 42, and the conventional non-standby power module 43 in the non-standby power module 4 are all completely powered on, the non-core power-on indication module 5 sends a second indication signal to the SOC of the X86 architecture, indicating that all the non-core power supplies of the X86 platform are completely powered on; therefore, the technical effect of realizing power-on time sequence control without using a programming chip is achieved.

In a possible implementation manner, the stock power module 1 includes a conventional stock power module and a power module that still needs to work in a deep sleep state, and after the conventional stock power module is powered on, the power module that still needs to work in the deep sleep state is powered on by an SOC of an X86 architecture.

The conventional stock power supply module, the power supply module still needing to work in the deep sleep state and the conventional non-stock power supply module 43 respectively comprise a plurality of discrete power supply modules which are connected in sequence, and a delay module is connected between the two discrete power supply modules; the chain type driving electrification of the discrete power supply modules is realized through the discrete power supply modules which are sequentially connected and the time delay modules connected in every two discrete power supply modules.

The input end of the first discrete power supply module of the stock power supply module 1 is connected with a power supply, the last discrete power supply module of the stock power supply module is connected with the SOC of the X86 architecture, and when the last discrete power supply module of the stock power supply module is powered on, a third indication signal is sent to the SOC of the X86 architecture; the input end of the first discrete power module of the power module still needing to work in the deep sleep state is connected with the SOC of the X86 architecture, when the SOC of the X86 architecture receives a third indication signal, the power module still needing to work in the deep sleep state is powered on, and the last discrete power module of the power module still needing to work in the deep sleep state is connected with the basic power supply power-on indication module 2; therefore, after the conventional stock power supply module is completely powered on in a chain manner, the power supply module which still needs to work in a deep sleep state is powered on in a chain manner through the SOC of the X86 architecture; the input end of the first discrete power module of the conventional non-standby power module 43 is connected to the SOC of the X86 architecture, and the last discrete power module of the conventional non-standby power module 43 is connected to the non-core power supply power-on indication module 5.

The conventional power supply module, the power supply module which still needs to work in a deep sleep state and the conventional extraordinary power supply module 43 adopt a discrete power supply scheme, the power supplies are combined in a chain mode to achieve sequential control, control signals and the power supplies do not need to be accumulated in an area like a sequential control chip, the layout and wiring of the PCB can be achieved according to the nearby wiring of the power supply module, and the layout and wiring difficulty of the PCB is effectively reduced.

In a possible implementation manner, the basic power supply power-on indication module 2 includes a first and gate, where the first and gate receives a power-on signal of a last discrete power supply module of the conventional stock power supply module, a power supply working signal in the deep sleep state of the SOC of the X86 architecture, and a power-on signal of a last discrete power supply module of the power supply module still needing to work in the deep sleep state, and then performs a basic power supply power-on indication according to the received signals, that is, when the power supply modules still needing to work in the conventional stock power supply module and the deep sleep state are completely powered on, the first and gate indicates that the basic power supply is completely powered on.

In a possible implementation manner, the non-core power supply power-on indication module 5 includes a second and gate, where the second and gate receives the first indication signal of the basic power supply power-on indication module 2, the power-on signal of the memory power supply module 41, the detection signal of the small voltage detection module 44, and the power-on signal of the conventional non-standby power supply module 43, and then performs the non-core power supply power-on indication according to the received signals, that is, when the power-on of the conventional non-standby power supply module 1 and the power-on of the non-standby power supply module 4 is complete, the second and gate indicates that the power-on of the non-core power supply is complete, and the subsequent power-on of the core power supply can be performed.

Referring to fig. 2, in an embodiment, the X86 platform timing control apparatus 100 includes independent power supplies, low voltage power supplies and detection circuits thereof, a CPU integrated on an SOC of an X86 architecture, and a south bridge (PCH) for participating in timing control; among them, the time delay module (such as RC time delay circuit or small chip without programming) can be used to delay time between each power supply and the key time sequence, and the design of AND gate logic circuit is combined to reach the requirement of platform time sequence. The SOC in the figure is a chip packaged by an Intel CPU and a south bridge PCH, and is model J6425. In both the stock power supply module 1 and the conventional non-stock power supply module 43, separate power supply modules are used, and a scheme having a PG (PowerGood power supply output normal) signal is preferably selected. The standby power supply module 1 comprises a plurality of discrete power supply modules which are connected in sequence, a time delay module is connected between the discrete power supply modules, the input end of the first path of discrete power supply module of the standby power supply module 1 is connected with a power adapter, and the last path of discrete power supply module is connected with the basic power supply power-on indication module.

The standby power supply module 1 comprises a conventional standby power supply module and a power supply module which still needs to work in a deep sleep state; when the power adapter is connected, the power input end is connected with the enabling end through a voltage dividing resistor, a first path of power of the conventional standby power module is enabled by default, the first path of power outputs a PG signal, a second path of power is enabled by being driven by the delay module, the PG signal of the second path of power drives a third path of power … … by the delay module, and the like, and the PG signal of the last path of power is connected with a PMC _ DSW _ PWROK (namely a third indicating signal) of the CPU after passing through the delay module to indicate that the conventional standby power is completely powered on. The CPU will send back PMC _ SLP _ SUS # signal (to control the power operation in deep sleep state), and the X86 partial platform signal is also used to control the PCH auxiliary power. The power supply needing to work in the deep sleep state is the same as a conventional stock power supply and consists of discrete power supply modules and a delay module, the discrete power supply modules are sequentially powered on, a PG signal of the last path of power supply, PMC _ DSW _ PWROK and PMC _ SLP _ SUS # are used as AND gate logic (namely a basic power supply power-on indication module) together, then a PMC _ RSMRST # signal (namely a first indication signal) is output to a CPU, the basic power supply is indicated to be powered on completely, and a PMC _ PWRBTN # (power supply button is triggered to be started) signal is waited.

When the key is turned on to trigger the PMC _ PWRBTN # signal, the CPU sequentially provides a PMC _ SLP _ S4# signal, a PMC _ SLP _ S3# signal, and a VCCST _ EN signal, which respectively correspond to the enable memory power module 41, the conventional standby power module 43, and the low-voltage power module 42 (i.e., the sustain power module in the standby mode); the conventional standby power supply module 43 also sequentially powers up the conventional standby power supplies in the chain driving manner.

In a possible implementation manner, the small-voltage detection module 44 is implemented by matching a triode with a corresponding series resistor, and a later-stage circuit is built by using a MOS transistor and is used for detecting whether the signal output of the small-voltage power supply module 42 is normal. Then, the first indication signal output by the basic power supply power-on indication module 2, the power-on signal of the memory power supply module, the last PG signal of the conventional non-standby power supply module 43, and the signal of the small-voltage power supply detection module 44 are used as inputs of a second and gate (i.e., the non-Core power supply power-on indication module 5), and the and gate outputs ALL _ SYS _ PWRGD (i.e., the second indication signal) to indicate that the non-Core power supplies of the other platforms except the Core power supply (CPU Core power supply) and the GT power supply (graphics card power supply) are completely powered on. The signal enables an IMVP power supply (namely a core of a CPU and a display card power supply), and the IMVP power supply module outputs a PG signal VR-READY after self-checking. And a delay circuit is used for delaying for about 10ms, so that the signals are ensured to be stable. The delayed signal of ALL _ SYS _ PWRGD is sent to PMC _ SYS _ PWROK of the platform south bridge PCH (informing other systems that the power supply of the PCH is completely powered on), and the delayed signal of VR _ READY is sent to PMC _ PCH _ PWROK of the PCH (indicating that the basic power supply of the PCH and the CPU voltage are completely powered on). And finally, the PCH interior uses the PMC _ SYS _ PWROK, the PMC _ PCH _ PWROK and the PROC _ PWR _ GD for monitoring in the PCH interior to do and then output a final signal PMC _ PLTRST # of the whole power-on time sequence of the X86 platform. Thus, the power-on sequence of the X86 platform is normal, and the platform is completely powered on.

In one possible implementation, as shown in fig. 3, the delay module may adopt two stable, simple and commonly used delay circuits for ensuring stable power-on sequence context. The RC delay circuit used by the first delay module comprises a resistor R1, a capacitor C1 and a diode D1, wherein one end of the resistor R1 is connected with the input end, the other end of the resistor R1 is connected with the output end, the other end of the resistor R1 is grounded through the capacitor C1, the cathode of the diode D1 is connected with the input end, and the anode of the diode D1 is connected with the output end. The delay time can be adjusted by adjusting the sizes of the resistor R1 and the capacitor C1, and the engineering calculation formula of the delay time is as follows: t ≈ ln ((Vin-Vout)/Vin). times.RxC, where unit is second(s), volt (V), ohm (Ω), and Faraday (F); ln is a natural logarithm and is a logarithmic function with a constant e as a base number, Vin refers to an input voltage value of the delay circuit, Vout refers to an enable voltage threshold of a next stage circuit, R is a resistor R1 in the figure, and C is a capacitor C1 in the figure. The diode D1 in the figure is used as a quick discharge circuit of the building capacitor C1, and the delay circuit is prevented from being too slow in power-down speed and affecting power-down time sequence. The circuit in the figure is calculated to be Tdelay 0.693V multiplied by 1000 omega multiplied by 2.2uF multiplied by 1.5ms according to the above formula on the principle that the input is +3.3V and the enabling threshold of the next stage circuit is + 1.65V; the RC delay circuit engineering generally has a value range of 1 nanosecond to 10 seconds, and is practical. The time delay circuit has a slow rising edge of the time sequence, and when the time delay needs to reach the second level, the accuracy is not high, and the time delay circuit is generally used in the millisecond level in the embodiment.

The second delay module can be a simple delay chip which can be used without programming, and the SGM809 of Santa Claus, which can be optionally used in the design, can delay for about 240 ms. If necessary, a delay chip with delay reaching the second level can be selected. In the actual time sequence design of the X86 platform, time delay reaching the level of seconds is not needed temporarily, a chip is not needed, and the design requirement can be met by using a simple RC time delay circuit.

Fig. 4 shows a possible implementation manner of the small-voltage power supply module 42, where the small-voltage power supply module 42 includes: an NMOS transistor Q1, an NMOS transistor Q2, an NMOS transistor Q3, a resistor R4, a resistor R5, a resistor R6, a capacitor C2, a capacitor C3 and a capacitor C4; the G pole of the NMOS transistor Q3 is connected with a VCCST _ EN enabling pin, the S pole of the NMOS transistor Q3 is grounded, and the D pole of the NMOS transistor Q3 is connected with a + V3.3A power supply through the resistor R5; the G pole of the NMOS transistor Q2 is connected with the D pole of the NMOS transistor Q3, the S pole of the NMOS transistor Q2 is grounded, and the D pole of the NMOS transistor Q2 is connected with a + V5A power supply through the resistor R4; the G pole of the NMOS transistor Q1 is connected to the D pole of the NMOS transistor Q2 and grounded via the resistor R6, the D pole of the NMOS transistor Q1 is connected to + VCC1P05_ SOC _ OUT power supply and grounded via the capacitor C2, and the S pole of the NMOS transistor Q1 is connected to + VCCST power supply and grounded via the capacitor C3 and the capacitor C4, respectively.

During the power-up sequence of the X86 platform, there are many small voltage power supplies with their special control logic, and the CPU or south bridge will issue control-on signals, which are commonly seen as the holding voltage for the X86 master to operate in standby mode and debug mode. The small-voltage power supply is characterized in that: the voltage is small, the current is small, and the device can be used in a standing or a very standing way. Therefore, the design adopts MOS tube, triode and current switch, the source of the power supply takes the system agent power (VCCSA-SystemAgentpowerrail) in the normal power supply or the auxiliary power supply (VCCIN _ AUX-PCHFIVRinpower supply) for the south bridge integrated voltage regulating module. In this embodiment, there is an auxiliary power supply for an internal FIVR (integrated voltage regulation module) of the south bridge PCH in the standby power, and then there is + VCC1P05_ SOC _ OUT as shown in fig. 4, and the power supply is directly provided by the PCH; + VCCST is the processor's holding voltage in standby mode, its voltage amplitude is + 1.05V; q1, Q2 and Q3 are NMOS tubes, the turn-on threshold voltage of Q1 is higher, and the turn-on threshold voltage of Q3 is lower; the principle of the circuit is that the SOC provides an enable signal of VCCST, the signal voltage is adjusted to be 3.3V level through NMOS tube Q3 reverse logic, and the level of the signal voltage is adjusted to be 5V through NMOS tube Q2 reverse logic to control the connection and disconnection of NMOS tube Q1; when VCCST _ EN is high, NMOS transistor Q3 is on. At this time, the G electrode of the NMOS transistor Q2 is simultaneously conducted by the NMOS transistor Q3 to ground, and the NMOS transistor Q2 is not conducted. Then, the G-pole level of the NMOS transistor Q1 is pulled up to +5V by the resistor R4, the S-pole level is zero, Vgs (voltage difference between G-pole and S-pole) of the NMOS transistor Q1 is +5V greater than its turn-on threshold +1.3V, the NMOS transistor Q1 is turned on, and + VCC1P05_ SOC _ OUT power is directed to + VCCST. At this time, the level of + VCCST is +1.05V (at the same time, the S-pole level of the NMOS transistor Q1 is +1.05V), and as long as EN of VCCST is always high, the G-pole level of the NMOS transistor Q1 is always +5V, and the NMOS transistor Q1 is always kept in the on state.

Fig. 5 shows a possible implementation manner of the small voltage detection module 44, which includes: an NMOS transistor Q4, an NPN triode Q5, a resistor R7, a resistor R8 and a resistor R9; the B pole of the NPN triode Q5 is connected with a + VCCST power supply through the resistor R9, the E pole of the NPN triode Q5 is grounded, and the C pole of the NPN triode Q5 is connected with a + V3.3A power supply through the resistor R8; the G pole of the NMOS tube Q4 is connected with the C pole of the NPN triode Q5, the S pole of the NMOS tube Q4 is grounded, the D pole of the NMOS tube Q4 is connected with a + V3.3A power supply through the resistor R7, and the D pole of the NMOS tube Q4 is also connected with a VCCST _ PG pin.

The circuit is an important component part participating in time sequence design in the embodiment, and can detect whether the small-voltage power supply is completely powered up or not with low material cost. The small voltage of the circuit generally refers to + 0.7V- +1.5V, the level in the X86 platform timing sequence is generally +1.8V and +3.3V, the level around +1V can not directly participate in the timing logic, and the circuit can better solve the problem with little cost. Q4 is NMOS transistor, and Q5 is NPN transistor. In the design, a model 3904 is selected as the NPN tube Q5, and the current amplification factor is about 10 times; the NMOS transistor Q4 is 2N7002, and the conduction threshold between the G pole and the S pole is + 2V. The + VCCST is at a level of +1.05V, the resistor R9 is connected in series at the base input end of the triode Q5, and by using the current amplification characteristic of the triode, the voltage drop of the resistor R8 can reach 40V theoretically, and at this time, it can be ensured that the G-electrode level of the NMOS transistor Q4 is at a low level, the NMOS transistor Q4 is not turned on, the D-electrode level of the NMOS transistor Q4 is at +3.3V, that is, VCCST _ PG is at +3.3V, indicating that the + VCCST is completely powered on.

The embodiment of the utility model provides a theory of operation as follows:

when the power adapter is connected, a first discrete power supply of the stock power module 1 is enabled to be started by default, and then the next discrete power supply is driven in a delayed mode in sequence, so that the chain electrification of the stock power supply is realized; when the standby power supply is completely powered on, the basic power supply power-on indicating module 2 outputs a PMC _ RSMRST # signal to the CPU, indicating that the basic power supply is completely powered on.

After the startup signal acquisition module 3 acquires a button startup trigger PMC _ PWRBTN # signal, the CPU enables the emergency power supply module 4, where the emergency power supply module 4 includes a memory power supply module 41, a small-voltage power supply module 42, and a conventional emergency power supply module 43, and the small-voltage power supply module 42 detects whether it is completely powered up through a special small-voltage detection module 44; when the non-Core power supply power-on indication module 5 detects that the basic power supply power-on indication module 2 and the standby power supply module 4 are both successfully powered on, indicating that the power supplies of the other platforms except the Core power supply (CPU Core power supply) and the GT power supply (graphics display card power supply) are all completely powered on, sending a signal to the PMC _ SYS _ PWROK of the platform south bridge PCH, and finally, monitoring each signal inside the PCH and outputting a final signal PMC _ PLTRST #, which represents that the power-on time sequence of the X86 platform is normal, and the platform is completely powered on.

The embodiment of the utility model omits the development of a time sequence control chip, can realize power-on time sequence control without using a programming chip, effectively reduces the development period of a platform, and shortens the product research and development time; by designing the delay circuit and the small-voltage detection circuit, the material cost is reduced by about 20% compared with the cost of a time sequence control chip, and the material development cost of the platform is effectively reduced; the scheme of the discrete power supply is adopted, the sequential control can be achieved through the chain combination of the power supplies, control signals and the power supplies do not need to be accumulated in one area like a sequential control chip, the layout and wiring of the PCB can be arranged nearby according to the power supply module, and the layout and wiring difficulty of the PCB is effectively reduced; by providing the separated time sequence control, each spare power supply and each extra power supply can be flexibly configured, and other power supplies which are not in the platform time sequence can be designed and configured in a special use scene, so that the aim of flexible control is fulfilled.

Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.

Claims (8)

1. An X86 platform timing control device, characterized in that: the system comprises a standing power supply module, a basic power supply power-on indicating module, a starting signal acquiring module, a standing power supply module and a non-core power supply power-on indicating module;

the input end of the standby power module is connected with a power supply, the basic power supply power-on indicating module is connected with the output end of the standby power module and used for indicating whether the standby power module is completely powered on, and when the standby power module is completely powered on, the basic power supply power-on indicating module sends a first indicating signal to the SOC of the X86 architecture; after receiving the first indication signal, the SOC of the X86 architecture enables the emergency power supply module to be powered on when the power-on signal acquisition module acquires a power-on signal; the non-core power supply power-on indicating module is respectively connected with the basic power supply power-on indicating module and the non-standby power supply module and is used for indicating whether the standby power supply module and the non-standby power supply module are completely powered on, and when the standby power supply module and the non-standby power supply module are completely powered on, the non-core power supply power-on indicating module sends a second indicating signal to the SOC of the X86 architecture;

the standby power supply module comprises a memory power supply module, a small-voltage detection module and a conventional standby power supply module, wherein the memory power supply module and the conventional standby power supply module are respectively connected with the non-core power supply power-on indication module, and the small-voltage power supply module is connected with the non-core power supply power-on indication module through the small-voltage detection module.

2. The apparatus of claim 1, wherein the X86 stage timing control device comprises: the system comprises a power supply module, a power supply module and a time delay module, wherein the power supply module comprises a conventional power supply module and a power supply module which still needs to work in a deep sleep state, the conventional power supply module, the power supply module which still needs to work in the deep sleep state and the conventional power supply module respectively comprise a plurality of discrete power supply modules which are sequentially connected, and a time delay module is connected between the two discrete power supply modules;

the input end of the first discrete power supply module of the stock power supply module is connected with a power supply, the last discrete power supply module of the stock power supply module is connected with the SOC of the X86 architecture, and when the last discrete power supply module of the stock power supply module is powered on, a third indicating signal is sent to the SOC of the X86 architecture; the input end of the first discrete power supply module of the power supply module still needing to work in the deep sleep state is connected with the SOC of the X86 architecture, when the SOC of the X86 architecture receives a third indication signal, the power supply module still needing to work in the deep sleep state is powered on, and the last discrete power supply module of the power supply module still needing to work in the deep sleep state is connected with the basic power supply power-on indication module; the input end of the first path of discrete power supply module of the conventional emergency power supply module is connected with the SOC of an X86 architecture, and the last path of discrete power supply module of the conventional emergency power supply module is connected with the non-core power supply power-on indication module.

3. The apparatus of claim 2, wherein the X86 stage timing control device comprises: the time delay module comprises a resistor R1, a capacitor C1 and a diode D1, wherein one end of the resistor R1 is connected with the input end, the other end of the resistor R1 is connected with the output end and is grounded through the capacitor C1, the cathode of the diode D1 is connected with the input end, and the anode of the diode D1 is connected with the output end.

4. The apparatus of claim 2, wherein the X86 stage timing control device comprises: the discrete power supply module is a power supply module with PG signals.

5. The apparatus of claim 2, wherein the X86 stage timing control device comprises: the basic power supply power-on indication module comprises a first AND gate, the first AND gate receives a power-on signal of the last discrete power supply module of the conventional stock power supply module, a working signal of a power supply module still needing to work in a control deep sleep state of the SOC of the X86 architecture and a power-on signal of the last discrete power supply module of the power supply module still needing to work in the deep sleep state respectively, and then performs power-on indication on the basic power supply according to the received signals.

6. The apparatus of claim 1, wherein the X86 stage timing control device comprises: the non-core power supply power-on indication module comprises a second AND gate, the second AND gate receives a first indication signal of the basic power supply power-on indication module, a power-on signal of the memory power supply module, a detection signal of the small voltage detection module and a power-on signal of the conventional non-standby power supply module respectively, and then performs non-core power supply power-on indication according to the received signals.

7. The apparatus of claim 1, wherein the X86 stage timing control device comprises: the small-voltage power supply module includes: an NMOS transistor Q1, an NMOS transistor Q2, an NMOS transistor Q3, a resistor R4, a resistor R5, a resistor R6, a capacitor C2, a capacitor C3 and a capacitor C4;

the G pole of the NMOS transistor Q3 is connected with a VCCST _ EN enabling pin, the S pole of the NMOS transistor Q3 is grounded, and the D pole of the NMOS transistor Q3 is connected with a + V3.3A power supply through the resistor R5;

the G pole of the NMOS transistor Q2 is connected with the D pole of the NMOS transistor Q3, the S pole of the NMOS transistor Q2 is grounded, and the D pole of the NMOS transistor Q2 is connected with a + V5A power supply through the resistor R4;

the G pole of the NMOS transistor Q1 is connected to the D pole of the NMOS transistor Q2 and grounded via the resistor R6, the D pole of the NMOS transistor Q1 is connected to + VCC1P05_ SOC _ OUT power supply and grounded via the capacitor C2, and the S pole of the NMOS transistor Q1 is connected to + VCCST power supply and grounded via the capacitor C3 and the capacitor C4, respectively.

8. The apparatus of claim 1, wherein the X86 stage timing control device comprises: the small voltage detection module includes: an NMOS transistor Q4, an NPN triode Q5, a resistor R7, a resistor R8 and a resistor R9;

the B pole of the NPN triode Q5 is connected with a + VCCST power supply through the resistor R9, the E pole of the NPN triode Q5 is grounded, and the C pole of the NPN triode Q5 is connected with a + V3.3A power supply through the resistor R8;

the G pole of the NMOS tube Q4 is connected with the C pole of the NPN triode Q5, the S pole of the NMOS tube Q4 is grounded, the D pole of the NMOS tube Q4 is connected with a + V3.3A power supply through the resistor R7, and the D pole of the NMOS tube Q4 is also connected with a VCCST _ PG pin.

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