CN214753834U - Ceramic substrate and light-emitting device - Google Patents
Ceramic substrate and light-emitting device Download PDFInfo
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- CN214753834U CN214753834U CN202120405756.XU CN202120405756U CN214753834U CN 214753834 U CN214753834 U CN 214753834U CN 202120405756 U CN202120405756 U CN 202120405756U CN 214753834 U CN214753834 U CN 214753834U
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Abstract
The utility model discloses a ceramic substrate and a light-emitting device, the ceramic substrate comprises an upper copper layer, a middle ceramic layer and a lower copper layer, the upper copper layer is arranged on the upper surface of the middle ceramic layer, and the lower copper layer is arranged on the lower surface of the middle ceramic layer; the ceramic substrate is provided with a plurality of through holes, conductive materials are filled in the through holes, and the upper copper layer and the lower copper layer are electrically connected based on the conductive materials in the through holes; the upper copper layer has a thickness of D1, the lower copper layer has a thickness of D2,
the ceramic substrate and the finished product structure of the light-emitting deviceFor the design basis, improve ceramic substrate's structural composition and structural dimension, avoided because of the too big problems such as luminescent device product harmfully, fault rate height, short-lived that lead to of angularity, guaranteed luminescent device's quality, reduced luminescent device's manufacturing cost.
Description
Technical Field
The utility model relates to the base plate field, concretely relates to ceramic substrate and luminescent device.
Background
In the design of ceramic high-power LED devices at the present stage, the content of ceramic substrate circuit layer design, plating layer surface treatment, plating layer thickness design and the like mainly takes the processability of the ceramic substrate into consideration, and does not systematically take the process requirements of device packaging into consideration, wherein the content of warpage control, roughness control and the like of the ceramic substrate after being subjected to plating layer treatment has a great influence on the packaging process and the performance and yield of packaged devices.
The thicknesses of the upper layer and the lower layer of the conventional ceramic substrate circuit layer coating are designed to be the same, so that the warping degree of the ceramic substrate in the processing stage and the finished product structure of the ceramic substrate is ensured to be within 0.3%; however, in the die bonding process of high-power packaging, especially in the eutectic process, a new stress factor is formed on the ceramic substrate by the newly formed metal alloy connecting key, so that the warpage of the ceramic substrate is changed, the subsequent processing of the product is adversely affected, the ceramic substrate and the light-emitting chip are easily damaged by stress, the yield of packaged devices is reduced, the failure rate is increased, and the service life is greatly reduced.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defect of current ceramic substrate, the utility model provides a ceramic substrate considers to the device encapsulation, and the structure to ceramic substrate is constituteed and the structure size improves, has avoided because of the too big product that leads to of angularity is bad, product fault rate is high, short product life scheduling problem, has guaranteed light emitting device's quality, reduces light emitting device's manufacturing cost.
Correspondingly, the utility model also provides a ceramic substrate, which is characterized in that the ceramic substrate comprises an upper copper layer, a middle ceramic layer and a lower copper layer, wherein the upper copper layer is arranged on the upper surface of the middle ceramic layer, and the lower copper layer is arranged on the lower surface of the middle ceramic layer;
the ceramic substrate is provided with a plurality of through holes, any one of the through holes is filled with a conductive material, and the upper copper layer and the lower copper layer are electrically connected based on the conductive material in the through holes;
the upper copper layer has a thickness of D1, the lower copper layer has a thickness of D2,
in an alternative embodiment, the thickness D0 of the intermediate ceramic layer satisfies the condition: d0 ∈ [200 μm,1000 μm ].
In an alternative embodiment, the thickness D1 of the upper copper layer satisfies the condition: d1 ∈ [20 μm,80 μm ];
and/or the thickness D2 of the lower copper layer satisfies the condition: d2 ∈ [35 μm,105 μm ].
In an alternative embodiment, the ceramic substrate further comprises an upper plating layer overlying the upper copper layer;
and/or the ceramic substrate further comprises a lower plating layer, wherein the lower plating layer covers the lower copper layer.
In an alternative embodiment, the upper plating layer comprises a gold or silver plating layer on a side remote from the upper copper layer;
the lower plating layer comprises a gold plating layer or a silver plating layer on one side far away from the lower copper layer.
In an alternative embodiment, the surface of the upper plating layer has center line average roughness Ra1∈[0.1μm,4μm]Cross average roughness Rz of the surface of said upper plating layer1∈[0.5μm,8μm]；
And/or center line average roughness Ra of surface of the lower plating layer2∈[0.1μm,4μm]Cross average roughness Rz of the surface of said lower plating layer2∈[0.5μm,8μm]。
In an alternative embodiment, the volume filling rate a of the conductive material in the through-hole satisfies the condition: a belongs to [ 85%, 95% ].
In an alternative embodiment, the conductive material in the through hole covers an inner wall of the corresponding through hole, and the conductive material in the through hole has a cylindrical structure.
Correspondingly, the utility model also provides a light-emitting device, including luminous chip and above arbitrary any ceramic substrate, luminous chip is based on electrode solder layer bonding is in on the ceramic substrate.
In an alternative embodiment, the electrode solder layer has a thickness of 3 μm.
To sum up, the embodiment of the utility model provides a ceramic substrate and light emitting device, this ceramic substrate carry out ceramic substrate's structure and size design from final fashioned light emitting device structure to satisfy light emitting device's base plate angularity requirement, avoided because of the too big product that leads to of angularity bad, product fault rate height, short product life scheduling problem, guaranteed light emitting device's quality, reduced light emitting device's manufacturing cost.
Drawings
Fig. 1 is a schematic sectional structure diagram of an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of a light emitting device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Fig. 1 shows a schematic cross-sectional structure diagram of an embodiment of the present invention, and it should be noted that, because the ceramic substrate provided by the embodiment of the present invention is mainly applied to the production of high-power LED devices, the limitation on the partial size data in the ceramic substrate is obtained by taking the final product form of the LED device as an object, and the main purpose of the present invention is to ensure that the warpage of the substrate of the LED device is within 0.3%.
Specifically, the utility model provides a ceramic substrate, including last copper layer 11, middle ceramic layer 10 and lower copper layer 12, go up copper layer 11 with copper layer 12 covers respectively down two relative surperficial of middle ceramic layer 10 are the upper surface and the lower surface of middle ceramic layer 10 respectively in the embodiment of the utility model provides an in the embodiment.
The ceramic substrate is provided with a plurality of through holes 15, conductive materials 16 are filled in the through holes 15, and the upper copper layer 11 and the lower copper layer 12 are electrically connected based on the conductive materials 16 in the through holes.
In the specific processing, the intermediate ceramic layer 10 is used as a support, the upper copper layer 11 and the lower copper layer 12 are respectively processed on the intermediate ceramic layer 10, and then the through hole 15 is punched. The upper copper layer 11 is mainly used for die bonding and circuit arrangement of the light-emitting chip, the lower copper layer 12 is mainly used for external welding and electrical connection and plays a role in heat conduction, and the through hole 15 is filled with a conductive material 16 to meet the requirement for electrical connection of the upper copper layer 11 and the lower copper layer 12.
The upper copper layer 11 has a thickness of D1, the lower copper layer 12 has a thickness of D2,
further, the thickness D1 of the upper copper layer 11 and the thickness D2 of the lower copper layer 12 may have a proportional relationship with the thickness D0 of the intermediate ceramic layer 10 for practical application. Alternatively, the thickness D1 of the upper copper layer 11, the thickness D2 of the lower copper layer 12, and the thickness D0 of the intermediate ceramic layer 10 may be implemented based on the following limitations:
specifically, the linear expansion coefficient of copper is about 17ppm/K, the material of the intermediate ceramic layer 10 is generally alumina ceramic, the linear expansion coefficient thereof is about 7.3ppm/K, when the light emitting chip used in the LED device is a flip light emitting chip, the linear expansion coefficient of sapphire (alumina with higher purity) which is a main material of the flip light emitting chip is about 7.7ppm/K, the area ratio occupied by the light emitting chip during die bonding and the stress balance of the two surfaces of the intermediate ceramic layer 10 are considered, and the internal stress release degree to the ceramic substrate in the stress treatment process is considered, so that the warpage of the ceramic substrate after being packaged into the LED device is less than 0.3%, and the dimensional ratio relationship among the upper copper layer 11, the lower copper layer 12 and the intermediate ceramic layer 10 is correspondingly derived.
To the encapsulation of LED device, the embodiment of the utility model provides an absolute value of the size of last copper layer 11, lower copper layer 12 and middle ceramic layer 10 in to ceramic substrate has been injectd to selection when the construction.
Specifically, on the basis of the above definition, the thickness D1 of the upper copper layer 11 satisfies the condition: d1 ∈ [20 μm,80 μm ];
the thickness D2 of the lower copper layer 12 satisfies the condition: d2 ∈ [35 μm,105 μm ];
the thickness D0 of the intermediate ceramic layer 10 satisfies the condition: d0 ∈ [200 μm,1000 μm ].
Further, according to the proportional relationship between the thicknesses of the upper copper layer 11 and the lower copper layer 12, and in combination with the actual absolute size, in a specific implementation, for convenience of implementation, an optional implementation mode is that the thickness of the upper copper layer is D1 and the thickness of the lower copper layer is D2, which satisfy the following conditions: D2-D1 is not less than 15 mu m and not more than 40 mu m.
Specifically, based on protection of the copper layer, in an alternative embodiment, the ceramic substrate further includes an upper plating layer 13, and the upper plating layer 13 covers the upper copper layer 11; and/or the ceramic substrate further comprises a lower plating layer 14, the lower plating layer 14 covering the lower copper layer 12.
Common materials of the plating layer comprise nickel, silver, gold, palladium and other materials, and the forming structure of the plating layer has certain difference according to different processing modes of the plating layer. For example, if the plating layer is processed by electroless nickel-gold processing, in the processing of the plating layer, firstly, palladium element is replaced on the surface of a copper layer through chemical reaction, then, a nickel-phosphorus alloy layer is chemically plated on the basis of palladium nuclei, then, a layer of gold is plated on the surface of nickel through replacement reaction, and finally, the formed plating layer structure has structures such as a nickel layer and the like inside in addition to the gold layer on the surface layer. Specifically, any processing means is intended to form a protective layer on the surface of the copper layer to protect the copper layer, and generally, the processing means and the final plating structure used for the plating layer are determined based on the material trigger of the surface layer.
Specifically, in this embodiment, the upper plating layer 13 includes a gold plating layer or a silver plating layer on a side away from the upper copper layer 11; the lower plating layer 14 comprises a gold or silver plating layer on the side remote from the lower copper layer 12. Specifically, the thickness of the gold plating layer is generally greater than or equal to 0.075 μm and the thickness of the silver plating layer is generally greater than 0.4 μm, for protection.
Further, the coating serves as a barrier for migration of active metal copper so as to facilitate welding, the surface roughness of the coating can affect the welding effect, specifically, the coating has too high roughness, a molten solder is difficult to fill a concave part of the coating in the welding process, the fixing effect is poor, the coating is easy to fall off, and poor contact is easy to cause; the roughness of the plating layer is too low, the contact surface of the liquid solder and the substrate is small in the welding process, the wettability is poor, and the weldability is reduced.
Therefore, in the embodiment of the present invention, the following limitations are made to the roughness of the plating layer: center line average roughness Ra of the surface of the upper plating layer 131∈[0.1μm,4μm]Cross-like average roughness Rz of the surface of the upper plating layer 131∈[0.5μm,8μm](ii) a And/or the center line average roughness Ra of the surface of the lower plating layer 142∈[0.1μm,4μm]Cross-like average roughness Rz of the surface of the lower plating layer 142∈[0.5μm,8μm]。
It should be noted that the center line average roughness and the cross average roughness are defined according to the coating material.
In an alternative embodiment, the volume filling rate a of the conductive material 16 in the through hole 15 satisfies the condition: a belongs to [ 85%, 95% ]. Specifically, since copper has a larger thermal expansion coefficient than ceramic, a certain expansion space needs to be reserved for the conductive material 16 in the through hole 15. Specifically, if the conductive through holes are completely filled, the post-processing can extrude the intermediate ceramic layer after the copper material is heated and expanded in some technological processes with relatively high temperature change, and the risk of board cracking or dark cracking caused by excessive extrusion can be caused in the intermediate ceramic layer.
Specifically, for the construction method of the conductive material, the processing of the conductive material needs an attachment surface, and therefore, in an optional embodiment, the conductive material 16 in the through hole 15 covers the inner wall of the corresponding through hole 15, the conductive material 16 in the through hole 15 is in a cylindrical structure, and a space required for the copper layer to expand is left in the middle.
Fig. 2 shows a schematic cross-sectional structure diagram of a light emitting device according to an embodiment of the present invention.
Correspondingly, the utility model also provides a light-emitting device, including light-emitting chip 17 and above arbitrary any ceramic substrate, light-emitting chip 17 bonding is in on the ceramic substrate.
In an alternative embodiment, the light emitting chip 17 is a flip chip bonded on the ceramic substrate based on an electrode solder layer 18.
In an alternative embodiment, the electrode solder layer 18 has a thickness of 3 μm.
To sum up, the embodiment of the utility model provides a ceramic substrate and light emitting device, this ceramic substrate carry out ceramic substrate's structure and size design from final fashioned light emitting device structure to satisfy light emitting device's base plate angularity requirement, avoided because of the too big product that leads to of angularity bad, product fault rate height, short product life scheduling problem, guaranteed light emitting device's quality, reduced light emitting device's manufacturing cost.
The ceramic substrate and the light emitting device provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by using specific examples, and the descriptions of the above embodiments are only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.
Claims (10)
1. A ceramic substrate comprising an upper copper layer disposed on an upper surface of an intermediate ceramic layer, and a lower copper layer disposed on a lower surface of the intermediate ceramic layer;
the ceramic substrate is provided with a plurality of through holes, any one of the through holes is filled with a conductive material, and the upper copper layer and the lower copper layer are electrically connected based on the conductive material in the through holes;
the upper copper layer has a thickness of D1, the lower copper layer has a thickness of D2,
2. the ceramic substrate according to claim 1, wherein the thickness D0 of the intermediate ceramic layer satisfies the condition: d0 ∈ [200 μm,1000 μm ].
3. The ceramic substrate of claim 1, wherein the upper copper layer has a thickness D1 that satisfies the condition: d1 ∈ [20 μm,80 μm ];
and/or the thickness D2 of the lower copper layer satisfies the condition: d2 ∈ [35 μm,105 μm ].
4. The ceramic substrate of claim 1, further comprising an upper plating layer overlying the upper copper layer;
and/or the ceramic substrate further comprises a lower plating layer, wherein the lower plating layer covers the lower copper layer.
5. The ceramic substrate of claim 4, wherein the upper plating layer comprises a gold or silver plating layer on a side away from the upper copper layer;
the lower plating layer comprises a gold plating layer or a silver plating layer on one side far away from the lower copper layer.
6. The ceramic substrate according to claim 4, wherein the surface of the upper plating layer has a center line average roughness Ra1∈[0.1μm,4μm]Cross average roughness Rz of the surface of said upper plating layer1∈[0.5μm,8μm]；
And/or center line average roughness Ra of surface of the lower plating layer2∈[0.1μm,4μm]Cross average roughness Rz of the surface of said lower plating layer2∈[0.5μm,8μm]。
7. The ceramic substrate according to claim 1, wherein a volume filling rate a of the conductive material in the through-hole satisfies a condition: a belongs to [ 85%, 95% ].
8. The ceramic substrate according to claim 1, wherein the conductive material in the through-hole covers an inner wall of the corresponding through-hole, and the conductive material in the through-hole has a cylindrical structure.
9. A light-emitting device comprising a light-emitting chip and the ceramic substrate according to any one of claims 1 to 8, the light-emitting chip being bonded on the ceramic substrate based on an electrode solder layer.
10. A light emitting device according to claim 9, wherein the electrode solder layer has a thickness of 3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120405756.XU CN214753834U (en) | 2021-02-24 | 2021-02-24 | Ceramic substrate and light-emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120405756.XU CN214753834U (en) | 2021-02-24 | 2021-02-24 | Ceramic substrate and light-emitting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214753834U true CN214753834U (en) | 2021-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202120405756.XU Active CN214753834U (en) | 2021-02-24 | 2021-02-24 | Ceramic substrate and light-emitting device |
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| CN (1) | CN214753834U (en) |
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2021
- 2021-02-24 CN CN202120405756.XU patent/CN214753834U/en active Active
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