CN214753811U - Heterojunction cell with substrate formed with grooves and cell assembly - Google Patents

Abstract

The application is suitable for the technical field of solar cells and provides a heterojunction cell with a substrate provided with a groove and a cell module. The heterojunction cell having a groove formed in a substrate is sequentially stacked with: the first conductive layer, the first amorphous silicon layer, the first intrinsic layer, the silicon substrate, the second intrinsic layer, the second amorphous silicon layer and the second conductive layer; the silicon substrate is formed with a groove for receiving the electrode, and the depth of the groove is in the range of 30-70 μm. Thus, the photoelectric conversion efficiency is advantageously improved.

Description

Heterojunction cell with substrate formed with grooves and cell assembly

Technical Field

The application belongs to the technical field of solar cells, and particularly relates to a heterojunction cell with a substrate provided with a groove and a cell module.

Background

In the related art heterojunction cell, since the silicon wafer is thick and has a high requirement for minority carrier lifetime, the amorphous silicon layer is generally thick to provide a strong passivation capability. However, a thicker amorphous silicon layer absorbs more light, resulting in a lower photoelectric conversion efficiency of the heterojunction cell. Therefore, how to improve the photoelectric conversion efficiency of the heterojunction cell becomes a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

The application provides a heterojunction battery and a battery assembly with a substrate formed with a groove, and aims to solve the problem of how to improve the photoelectric conversion efficiency of the heterojunction battery.

In a first aspect, the present application provides a heterojunction cell having a substrate with a recess, in which: the first conductive layer, the first amorphous silicon layer, the first intrinsic layer, the silicon substrate, the second intrinsic layer, the second amorphous silicon layer and the second conductive layer; the silicon substrate is provided with a groove for accommodating an electrode, and the depth of the groove ranges from 30 μm to 70 μm.

Optionally, the depth of the grooves ranges from 40 μm to 60 μm.

Optionally, the width of the groove ranges from 20 μm to 200 μm.

Optionally, the heterojunction cell includes a first electrode and a second electrode respectively disposed on two sides of the silicon substrate, the number of the first electrode and the second electrode is plural, and at least one of the plural first electrodes and the plural second electrodes is disposed in the groove.

Optionally, the groove is formed on a side of the silicon substrate facing the first electrode, and at least one of the first electrodes is disposed in the groove;

or, the groove is formed on one side of the silicon substrate facing the second electrode, and at least one of the second electrodes is arranged in the groove;

or, the groove comprises a first groove and a second groove which are respectively arranged on two sides of the silicon substrate, at least one of the first electrodes is arranged in the first groove, and at least one of the second electrodes is arranged in the second groove.

Optionally, the difference between the widths of the groove and the electrode disposed in the groove ranges from 0.5 μm to 1.5 μm.

Optionally, the difference between the width of the groove and the width of the electrode disposed in the groove is 1 μm.

Optionally, at least one of the first conductive layer and the second conductive layer comprises a transparent conductive oxide.

Optionally, the first amorphous silicon layer includes an N-type amorphous silicon layer, the silicon substrate includes an N-type monocrystalline silicon wafer, and the second amorphous silicon layer includes a P-type amorphous silicon layer.

In a second aspect, the present application provides a battery assembly comprising a battery according to any one of the above.

In the heterojunction cell and the cell module with the groove formed on the substrate, the groove with the depth ranging from 30 micrometers to 70 micrometers is formed on the silicon substrate to accommodate the electrode, so that the movement path of a photon-generated carrier can be reduced, and recombination can be reduced. Moreover, passivation performance can be ensured, and meanwhile thinner amorphous silicon layers can be adapted, so that the absorption of light by the amorphous silicon layers is reduced. Thus, the photoelectric conversion efficiency is advantageously improved.

Drawings

Fig. 1 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 2 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 3 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 4 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 5 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 6 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 7 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application;

fig. 8 is a schematic structural view of a heterojunction cell in which a substrate is formed with a groove according to an embodiment of the present application.

Description of the main element symbols:

a heterojunction cell 10, a first electrode 11, a first conductive layer 12, a first amorphous silicon layer 13, a first intrinsic layer 14, a silicon substrate 15, a groove 151, a second intrinsic layer 16, a second amorphous silicon layer 17, a second conductive layer 18, and a second electrode 19.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the related art, the photoelectric conversion efficiency of the heterojunction cell is low. The substrate of the embodiment of the application is provided with the heterojunction battery with the groove, and the groove with the depth range of 30-70 mu m is formed on the substrate, so that the photoelectric conversion efficiency is improved.

Referring to fig. 1, a heterojunction cell 10 having a groove formed in a substrate according to an embodiment of the present application includes: a first conductive layer 12, a first amorphous silicon layer 13, a first intrinsic layer 14(i-a-Si: H), a silicon substrate 15, a second intrinsic layer 16(i-a-Si: H), a second amorphous silicon layer 17, and a second conductive layer 18; the silicon substrate 15 is formed with a groove 151 for receiving an electrode, and the depth of the groove 151 ranges from 30 μm to 70 μm.

The heterojunction cell 10 with the groove 151 formed on the substrate in the embodiment of the application forms the groove 151 with the depth ranging from 30 micrometers to 70 micrometers on the silicon substrate 15, so that the movement path of a photon-generated carrier can be reduced, and the recombination can be reduced. Moreover, passivation performance can be ensured, and meanwhile thinner amorphous silicon layers can be adapted, so that the absorption of light by the amorphous silicon layers is reduced. Thus, the photoelectric conversion efficiency is advantageously improved.

It can be understood that, since the silicon substrate 15 is formed with the groove 151 having a depth ranging from 30 μm to 70 μm, photogenerated carriers inside the silicon substrate 15 reach the amorphous silicon layer without moving a long path any more, and are collected by the electrode through the conductive layer. On a silicon substrate with the same thickness, the heterojunction cell 10 with the groove 151 is formed on the substrate of the embodiment of the application, so that the photoelectric conversion efficiency is higher, and the dependence on the minority carrier lifetime is reduced.

Specifically, the depth of the groove 151 is, for example, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 41 μm, 45 μm, 49 μm, 50 μm, 52 μm, 55 μm, 58 μm, 60 μm, 61 μm, 65 μm, 69 μm, 70 μm.

Preferably, the depth of the grooves 151 ranges from 40 μm to 60 μm. Examples thereof include 40 μm, 41 μm, 45 μm, 49 μm, 50 μm, 52 μm, 55 μm, 58 μm and 60 μm. Thus, the current collection capability can be improved, and the risk of silicon chip cracking can be reduced, so that the overall performance of the heterojunction battery 10 is better.

On a silicon substrate with the same thickness, the photoelectric conversion efficiency of the heterojunction cell without the groove is 23.8%, the photoelectric conversion efficiency of the heterojunction cell 10 with the groove depth of 41 micrometers in the application is 24.5%, and the photoelectric conversion efficiency of the heterojunction cell 10 with the groove depth of 50 micrometers in the application is 24.7%. It is apparent that the heterojunction cell 10 in which the substrate is formed with the groove 151 of the embodiment of the present application has higher photoelectric conversion efficiency than the heterojunction cell without the groove.

It is understood that, in the case that the number of the grooves 151 is plural, the depths of the plural grooves 151 may be the same or different.

Alternatively, the width of the grooves 151 may range from 20 μm to 200 μm. Examples thereof include 20 μm, 22 μm, 38 μm, 50 μm, 85 μm, 92 μm, 110 μm, 133 μm, 150 μm, 188 μm and 200 μm. Thus, the grooves can accommodate the electrodes, the risk of cracking of the silicon wafer can be reduced, and the overall performance of the heterojunction battery 10 is good.

Preferably, the width of the groove 151 ranges from 32 μm to 38 μm. For example, 32 μm, 33 μm, 34 μm, 35 μm, 36 μm, 37 μm, 38 μm. In this manner, the overall performance of the heterojunction cell 10 is made better.

It is understood that, in the case that the number of the grooves 151 is plural, the widths of the plural grooves 151 may be the same or different.

Alternatively, the difference between the widths of the groove 151 and the electrode provided in the groove 151 may be in the range of 0.5 μm to 1.5 μm. For example, 0.5. mu.m, 0.52. mu.m, 0.58. mu.m, 0.6. mu.m, 0.65. mu.m, 0.72. mu.m, 0.88. mu.m, 1.0. mu.m, 1.13. mu.m, 1.25. mu.m, 1.32. mu.m, 1.48. mu.m, 1.5. mu.m. Therefore, the width of the groove 151 is matched with that of the electrode, the situation that the electrode cannot be accommodated due to the fact that the width of the groove 151 is too small is avoided, and the situation that the silicon wafer is easy to break due to the fact that the width of the groove 151 is too large is avoided.

In this embodiment, the difference between the widths of the groove 151 and the electrode provided in the groove 151 is 1 μm. In this way, the width adaptation of the grooves 151 to the electrodes is best, resulting in a better overall performance of the heterojunction cell 10.

In the present embodiment, 1 electrode is provided in 1 groove 151. It is understood that in other embodiments, multiple electrodes may be provided in 1 recess.

In the present embodiment, the first amorphous silicon layer 13 includes an N-type amorphous silicon layer ((N +) a-Si: H), the silicon substrate 15 includes an N-type single crystal silicon wafer (N-Si), and the second amorphous silicon layer 17 includes a P-type amorphous silicon layer ((P +) i-a-Si: H). It is understood that in other embodiments, the silicon substrate 15 may comprise a P-type single crystal silicon wafer. Thus, the groove 151 has a wide adaptability to silicon wafers, and can improve photoelectric conversion efficiency regardless of being applied to an N-type monocrystalline silicon wafer or a P-type monocrystalline silicon wafer.

Optionally, at least one of the first Conductive layer 12 and the second Conductive layer 18 comprises a Transparent Conductive Oxide (TCO). Therefore, the conductive layer can transmit sunlight while being conductive, and the photoelectric conversion efficiency is favorably improved.

Specifically, only the first conductive layer 12 may include a transparent conductive oxide; only the second conductive layer 18 may include a transparent conductive oxide; the first conductive layer 12 and the second conductive layer 18 may each comprise a transparent conductive oxide.

Specifically, the transparent conductive Oxide includes, but is not limited to, at least one of Indium Tin Oxide (ITO), Fluorine-doped Tin Oxide (FTO), and Aluminum-doped Zinc Oxide (AZO). The specific type of TCO is not limited herein.

It is understood that in other embodiments, the first conductive layer 12 and/or the second conductive layer 18 may include a metal film system, a compound film system, a polymer film system, a composite film system, etc., other than an oxide film system. Such as PEDOT (polymer of EDOT (3, 4-ethylenedioxythiophene monomer), metal grids, carbon nanorod conductive Films (CNB Films), Silver Nanowires (SNW), Graphene (Graphene), and the like. The specific form of the first conductive layer 12 and the second conductive layer 18 is not limited herein.

Referring to fig. 1 again, optionally, the heterojunction cell 10 includes a plurality of first electrodes 11 and a plurality of second electrodes 19 respectively disposed on two sides of the silicon substrate 15, and at least one of the plurality of first electrodes 11 and the plurality of second electrodes 19 is disposed in the groove 151.

In this manner, current can be collected through the electrodes, ensuring proper operation of the heterojunction cell 10. And at least one electrode is arranged in the groove 151, so that the shielding of the electrode to light can be reduced, the utilization rate of light is improved, the motion path of a photon-generated carrier is reduced, and the photoelectric conversion efficiency can be improved.

It is understood that "at least one of the plurality of first electrodes 11 and the plurality of second electrodes 19 is provided in the groove 151" includes three cases: 1, 2, 3 or all of the first electrodes 11 are arranged in the groove 151, and none of the second electrodes 19 is arranged in the groove 151; 1, 2, 3 or all of the plurality of second electrodes 19 are arranged in the groove 151, and none of the plurality of first electrodes 11 is arranged in the groove 151; 1, 2, 3 or all of the plurality of first electrodes 11 are disposed in the groove 151, and 1, 2, 3 or all of the plurality of second electrodes 19 are disposed in the groove 151.

It is understood that in the case where a portion of the first electrode 11 is disposed in the groove 151 and none of the plurality of second electrodes 19 is disposed in the groove 151, the first electrodes 11 disposed in the groove 151 may be continuously distributed.

For example, the first surface of the heterojunction cell 10 can be divided into a first region and a second region, the first region is provided with a groove 151, the plurality of first electrodes 11 in the first region are all disposed in the groove 151, the second region is not provided with the groove 151, and the plurality of first electrodes 11 in the second region are not disposed in the groove 151.

Specifically, the number of the first electrodes 11 in the first region may be 10 to 20. For example, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20. Therefore, the effect of improving the photoelectric conversion efficiency is better.

It is understood that, in the case that a part of the first electrode 11 is disposed in the groove 151 and none of the plurality of second electrodes 19 is disposed in the groove 151, the first electrodes 11 disposed in the groove 151 may be distributed intermittently. For example, between two adjacent first electrodes 11 disposed in the groove 151, 1 first electrode 11 not disposed in the groove 151 is spaced.

Similarly, in the case where a portion of the second electrode 19 is disposed in the groove 151 and none of the plurality of first electrodes 11 is disposed in the groove 151, the second electrodes 19 disposed in the groove 151 may be continuously distributed.

For example, the second surface of the heterojunction cell 10 may be divided into a third region and a fourth region, the third region is provided with a groove 151, the plurality of second electrodes 19 in the third region are all disposed in the groove 151, the fourth region is not provided with the groove 151, and the plurality of second electrodes 19 in the fourth region are not disposed in the groove 151.

Specifically, the number of the second electrodes 19 in the third region may be 10 to 20. For example, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20. Therefore, the effect of improving the photoelectric conversion efficiency is better.

Further, the first region and the third region are provided with the grooves 151, the second region and the fourth region are not provided with the grooves 151, the first region and the fourth region overlap in the thickness direction, and the second region and the third region overlap in the thickness direction. In this way, the region in which the groove 151 is formed on one surface is offset from the region in which the groove 151 is formed on the other surface, and the risk of the heterojunction cell 10 breaking can be reduced.

It is understood that, in the case that a part of the second electrode 19 is disposed in the groove 151 and none of the plurality of first electrodes 11 is disposed in the groove 151, the plurality of second electrodes 19 disposed in the groove 151 may be distributed intermittently. For example, between two adjacent second electrodes 19 disposed in the groove 151, 1 second electrode 19 not disposed in the groove 151 is spaced.

Referring to fig. 1 and fig. 2, optionally, a groove 151 is formed on a side of the silicon substrate 15 facing the first electrode 11, and at least one of the plurality of first electrodes 11 is disposed in the groove 151. Specifically, in fig. 1, 1 first electrode 11 is provided in the groove 151, and none of the second electrodes 19 is provided in the groove 151. In fig. 2, 2 first electrodes 11 are disposed in the groove 151, and none of the second electrodes 19 is disposed in the groove 151.

Referring to fig. 3 and 4, alternatively, a groove 151 is formed on a side of the silicon substrate 15 facing the second electrode 19, and at least one of the second electrodes 19 is disposed in the groove 151.

Specifically, in fig. 3, 1 second electrode 19 is provided in the groove 151, and none of the first electrodes 11 is provided in the groove 151. In fig. 4, 2 second electrodes 19 are disposed in the groove 151, and none of the first electrodes 11 is disposed in the groove 151.

Referring to fig. 5, 6, 7 and 8, optionally, the groove 151 includes a first groove 1511 and a second groove 1512 respectively disposed on two sides of the silicon substrate 15, at least one of the first electrodes 11 is disposed in the first groove 1511, and at least one of the second electrodes 19 is disposed in the second groove 1512.

Specifically, in fig. 5, 1 first electrode 11 is disposed in the first groove 1511, and 1 second electrode 19 is disposed in the second groove 1512. In fig. 6, 2 first electrodes 11 are disposed in the first groove 1511, and 1 second electrode 19 is disposed in the second groove 1512. In fig. 7, 1 first electrode 11 is disposed in the first groove 1511, and 2 second electrodes 19 are disposed in the second groove 1512. In fig. 8, 2 first electrodes 11 are disposed in the first groove 1511, and 2 second electrodes 19 are disposed in the second groove 1512.

The specific arrangement of the grooves 151 and the electrodes is not limited herein.

Referring to fig. 8, in the present embodiment, the first electrodes 11 are disposed in the first grooves 1511, the second electrodes 19 are disposed in the second grooves 1512, the first grooves 1511 and the second grooves 1512 are disposed in a staggered manner in the thickness direction of the heterojunction cell 10, and the first electrodes 11 and the second electrodes 19 are disposed in a staggered manner in the thickness direction of the heterojunction cell 10.

In this way, all the electrodes are arranged in the grooves, so that the movement path of a photon-generated carrier can be reduced to the maximum extent, the recombination is reduced, and the photoelectric conversion efficiency is improved. Because first recess 1511 and second recess 1512 stagger the setting in the thickness direction of heterojunction battery 10, avoided first recess 1511 and second recess 1512 to overlap in the thickness direction of heterojunction battery 10 to can reduce the broken risk of heterojunction battery 10, be favorable to ensureing the intensity of heterojunction battery 10.

It is understood that "the first groove 1511 and the second groove 1512 are disposed to be staggered in the thickness direction of the heterojunction cell 10" means that an orthogonal projection of the first groove 1511 on the first surface in the thickness direction does not overlap with an orthogonal projection of the second groove 1512 on the first surface in the thickness direction.

Specifically, the sum of the depth of the first recess 1511 and the depth of the second recess 1512 may be smaller than the thickness of the silicon substrate 15. In this way, the risk of the heterojunction cell 10 breaking can be reduced.

Further, the difference between the silicon substrate 15 and the total depth of the groove, which is the sum of the depth of the first groove 1511 and the depth of the second groove 1512, ranges to be greater than 2 μm. For example, 2 μm, 3 μm, 4 μm, and 5 μm. In this way, the risk of the heterojunction cell 10 breaking can be further reduced.

In the present embodiment, the first electrode 11 and the second electrode 19 are silver electrodes. Therefore, the conductive effect is better. The first electrode 11 and the second electrode 19 may be screen printed from silver paste. Therefore, the manufacturing accuracy is high, and the efficiency is high.

In this embodiment, the silicon wafer may be grooved to form a groove, thereby obtaining the silicon substrate 15. In particular, the grooving can be performed using a laser. Therefore, the grooving accuracy is high, and the grooving efficiency is high.

In the present embodiment, texturing may be performed on the silicon substrate 15. In other words, the silicon substrate 15 may include a textured surface. Therefore, the reflection of sunlight by the heterojunction cell 10 can be reduced through the texture surface, which is beneficial to improving the photoelectric conversion efficiency.

In this embodiment, a first intrinsic layer 14 and a first amorphous silicon layer 13 may be sequentially deposited on the front surface of a silicon substrate 15, a second intrinsic layer 16 and a second amorphous silicon layer 17 may be sequentially deposited on the back surface of the silicon substrate 15, and a first conductive layer 12 and a second conductive layer 18 may be respectively plated on the front surface and the back surface of the silicon substrate 15. Finally, the first electrode 11 and the second electrode 19 are printed on the front surface and the back surface of the silicon substrate 15, respectively.

The battery module provided by the embodiment of the present application includes the solar cell 10 described above.

In the battery module of the embodiment of the application, the groove 151 with the depth ranging from 30 μm to 70 μm is formed in the silicon substrate 15, so that the motion path of a photon-generated carrier can be reduced, and recombination can be reduced. Moreover, passivation performance can be ensured, and meanwhile thinner amorphous silicon layers can be adapted, so that the absorption of light by the amorphous silicon layers is reduced. Thus, the photoelectric conversion efficiency is advantageously improved.

For the explanation and explanation of the battery assembly, reference is made to the foregoing description, and the description is omitted here for the sake of avoiding redundancy.

The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims (10)

1. A heterojunction cell having a substrate with a recess formed therein, characterized in that: the first conductive layer, the first amorphous silicon layer, the first intrinsic layer, the silicon substrate, the second intrinsic layer, the second amorphous silicon layer and the second conductive layer; the silicon substrate is provided with a groove for accommodating an electrode, and the depth of the groove ranges from 30 μm to 70 μm.

2. The heterojunction cell of claim 1 wherein said substrate is formed with a recess, wherein the depth of said recess is in the range of 40 μm to 60 μm.

3. A heterojunction cell with a substrate formed with grooves according to claim 1, wherein the width of the grooves is in the range of 20 μm to 200 μm.

4. The heterojunction cell according to claim 1, wherein the substrate is formed with a groove, the heterojunction cell comprises a plurality of first electrodes and a plurality of second electrodes respectively disposed on two sides of the silicon substrate, and at least one of the plurality of first electrodes and the plurality of second electrodes is disposed in the groove.

5. The heterojunction cell according to claim 4 wherein the substrate is formed with a recess formed in a side of the silicon substrate facing the first electrodes, at least one of the first electrodes being provided in the recess;

or, the groove is formed on one side of the silicon substrate facing the second electrode, and at least one of the second electrodes is arranged in the groove;

or, the groove comprises a first groove and a second groove which are respectively arranged on two sides of the silicon substrate, at least one of the first electrodes is arranged in the first groove, and at least one of the second electrodes is arranged in the second groove.

6. The heterojunction cell according to claim 1 wherein the substrate is formed with a groove, wherein the difference between the width of the groove and the width of the electrode provided in the groove is in the range of 0.5 μm to 1.5 μm.

7. The heterojunction cell according to claim 6 wherein the substrate is formed with a recess, wherein the difference between the width of the recess and the width of the electrode provided in the recess is 1 μm.

8. The substrate-formed grooved heterojunction cell of claim 1 wherein at least one of the first and second conductive layers comprises a transparent conductive oxide.

9. The heterojunction cell of claim 1 wherein said first amorphous silicon layer comprises an N-type amorphous silicon layer, said silicon substrate comprises an N-type monocrystalline silicon wafer, and said second amorphous silicon layer comprises a P-type amorphous silicon layer.

10. A battery pack comprising the battery according to any one of claims 1 to 9.

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