CN214707250U

CN214707250U - Integrated device, battery management chip and system and isolated power supply

Info

Publication number: CN214707250U
Application number: CN202120916920.3U
Authority: CN
Inventors: 周号; 段伟
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2021-11-12
Anticipated expiration: 2031-04-29

Abstract

The present disclosure provides an integrated device, can provide charge control signal and discharge control signal for charge control switch and the discharge control switch that control battery package charges and discharges to can provide power control signal for isolated power supply, the series circuit of charge control switch and discharge control switch is connected to between the positive terminal of battery package and the positive terminal of load/charger, integrated device includes: a high side driving part generating a charge control signal and a discharge control signal to control on and off of the charge control switch and the discharge control switch by the charge control signal and the discharge control signal, thereby controlling charge and discharge of the battery pack; and an isolated power supply control part which controls a power supply control signal of the isolated power supply so as to control a circuit of the isolated power supply by the power supply control signal, thereby generating an output voltage by the isolated power supply. The disclosure also provides an integrated device, a battery management chip and system and an isolated power supply.

Description

Integrated device, battery management chip and system and isolated power supply

Technical Field

The present disclosure relates to an integrated device, a battery management chip and system, and an isolated power supply.

Background

In a battery management system, it is necessary to control a switch for controlling charging and discharging of a battery pack so as to perform efficient charging and discharging, and in some applications, it is also necessary to generate a predetermined voltage to supply power to other components or systems.

In many cases, the control can be realized by using a discrete device, and the control is complex, large in size and the like.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides an integrated device, a battery management chip and system, and an isolated power supply.

According to one aspect, an integrated device capable of providing a charge control signal and a discharge control signal to a charge control switch and a discharge control switch that control charging and discharging of a battery pack and capable of providing a power supply control signal to an isolated power supply, a series circuit of the charge control switch and the discharge control switch being connected between a positive terminal of the battery pack and a positive terminal of a load/charger, the integrated device comprising:

a high side driving part generating the charge control signal and the discharge control signal to control on and off of the charge control switch and the discharge control switch by the charge control signal and the discharge control signal, thereby controlling charge and discharge of the battery pack; and

an isolated power supply control section that provides a power supply control signal of the isolated power supply to control a circuit of the isolated power supply by the power supply control signal to generate an output voltage by the isolated power supply.

According to at least one embodiment, the source of the charge control switch is connected to the positive terminal of the battery pack, the drain of the charge control switch is connected to the drain of the discharge control switch, the source of the discharge control switch is connected to the positive terminal of the charger/load, the gates of the charge control switch and the discharge control switch are respectively connected to an integrated device, and the integrated device provides the charge control signal and the discharge control signal to control the on and off of the charge control switch and the discharge control switch.

According to at least one embodiment, the source of the charge control switch is connected to the positive terminal of the battery pack, the source of the discharge control switch is connected to the positive terminal of the battery pack, the drain of the charge control switch is connected to the positive terminal of the load, the drain of the discharge control switch is connected to the positive terminal of the charger, the gates of the charge control switch and the discharge control switch are respectively connected to the integrated device, and the integrated device provides the charge control signal and the discharge control signal to control the on and off of the charge control switch and the discharge control switch.

According to at least one embodiment, the charge control switch is a charge control switch formed by connecting two or more NMOS transistors in parallel, and/or the discharge control switch is a discharge control switch formed by connecting two or more NMOS transistors in parallel.

According to at least one embodiment, the integrated device further comprises a pre-charge control switch, wherein the pre-charge control switch is a PMOS transistor, the drain of the pre-charge control switch is connected with the positive terminal of the battery pack, the source of the pre-charge control switch is connected with the drain of the charge control switch, and the grid of the pre-charge control switch receives a pre-charge control signal from the integrated device; or the pre-charge control switch is an NMOS transistor, the source of the pre-charge control switch is connected to the positive terminal of the battery pack, the drain of the pre-charge control switch is connected to the drain of the charge control switch, and the gate of the pre-charge control switch receives a pre-charge control signal from the integrated device; and/or

The pre-discharge control switch is an NMOS transistor, the drain electrode of the pre-discharge control switch is connected with the drain electrode of the discharge control switch, the source electrode of the pre-discharge control switch is connected with the positive electrode end of a load, and the grid electrode of the pre-discharge control switch receives a pre-discharge control signal from the integrated device; or the pre-discharge control switch is a PMOS transistor, the source electrode of the pre-discharge control switch is connected with the drain electrode of the discharge control switch, the drain electrode of the pre-discharge control switch is connected with the positive electrode end of the load, and the grid electrode of the pre-discharge control switch receives a pre-discharge control signal from the integrated device.

According to at least one embodiment, the integrated device supplies a charge control signal higher than a battery side voltage of the positive terminal of the battery pack by a first voltage to a gate of the charge control switch, and the integrated device supplies a discharge control signal higher than a load/charger side voltage of the positive terminal of the load/charger by the first voltage to a gate of the discharge control switch.

According to at least one embodiment, further comprising a first charge pump unit that generates a charge control switch charge pump voltage of a sum of the battery side voltage and the first voltage, and the integrated device generates a charge control signal based on the charge control switch charge pump voltage; and/or

Further included is a second charge pump unit that generates a discharge control switch-use charge pump voltage of a sum of the load/charger-side voltage and the first voltage, and the integrated device generates a discharge control signal based on the discharge control switch-use charge pump voltage.

According to at least one embodiment, the high-side driving section includes a first oscillating unit that generates an oscillating signal for the charge control signal and a second oscillating unit that generates an oscillating signal for the discharge control signal.

According to at least one embodiment, a precharge level conversion unit is further included, the precharge level conversion unit providing a precharge control signal to control the precharge control switch by the precharge control signal in a case where the precharge control switch is included.

According to at least one embodiment, the pre-discharge control unit further comprises a pre-discharge level conversion unit, wherein the pre-discharge level conversion unit provides a pre-discharge control signal so that the pre-discharge control switch is controlled by the pre-discharge control signal under the condition that the pre-discharge control switch is included.

According to at least one embodiment, the battery pack further comprises a load detection unit, wherein the load detection unit detects whether the battery pack is connected with a load; and/or

The battery pack charger further comprises a charger detection unit which detects whether the battery pack is connected with the charger or not, and/or

Further comprising a first voltage conversion unit for generating the first voltage, and/or

The power supply further comprises a second voltage conversion unit which is used for generating a second voltage.

According to at least one embodiment, the isolated power supply control section includes:

the feedback voltage sampling unit is used for collecting feedback voltage from a circuit of the isolation power supply;

an error amplifier comparing a feedback voltage provided from the feedback voltage sampling unit with a reference voltage to generate a comparison voltage;

a timer that generates a maximum switching frequency and a minimum switching frequency from the comparison voltage;

the current sampling unit is used for collecting current through an external sampling resistor;

a comparison unit generating a PWM stop signal according to the comparison voltage and the voltage from the current sampling unit;

a state control unit providing a protection signal according to the feedback unit;

the DEM/QR detection unit generates a DEM/QR control signal according to the feedback unit;

the logic unit is used for receiving the maximum switching frequency, the minimum switching frequency, the PWM stop signal, the protection signal, the DEM/QR control signal, and the overcurrent protection threshold signal and the minimum sampling current signal from the current sampling voltage to generate a PWM signal;

a power device controlled by the PWM signal and a drain terminal of the power device providing the power supply control signal.

According to at least one embodiment, the isolation power supply control section further includes an under-voltage locking unit that generates an under-voltage locking signal and an under-voltage release signal according to an input voltage.

According to one aspect, a chip for battery management includes:

parts of an integrated device as described above; and

the gating unit is used for selecting the battery sections in the battery pack;

the acquisition unit is used for measuring the battery section selected by the gating unit; and

a logic control unit receiving the output signal of the acquisition unit and generating a logic control signal to be provided at least to the high-side driving part.

According to one aspect, a battery management system comprises:

an integrated device as described above;

a charging control switch and a discharging control switch which are turned on or off by the control of the integrated device so as to charge or discharge the battery pack;

a controller to provide control signals to the integrated device.

According to one aspect, a battery management system comprises:

the battery management chip as described above;

a charging control switch and a discharging control switch which are switched on or off by the control of the battery management chip so as to charge or discharge the battery pack;

and the controller provides a control signal for the battery management chip.

According to at least one embodiment, the isolated power supply circuit provides power to the controller in response to a power control signal from the isolated power supply control.

According to at least one embodiment, the circuit of the isolated power supply comprises:

an isolation transformer including a first primary coil, a second primary coil, and a first secondary coil,

the isolated power supply control part receives the battery side voltage of the battery pack, generates a power supply control signal for controlling the first primary coil according to the feedback voltage formed by the second primary coil, and generates a power supply output voltage through the first secondary coil according to the power supply control signal.

According to at least one embodiment, the feedback terminal of the isolated power supply control part receives the feedback voltage, the feedback voltage is formed by a resistor connected to both sides of the second primary coil, the isolated power supply control part generates a supply voltage according to the battery voltage, and the supply voltage is supplied to the second primary coil.

According to one aspect, an integrated device capable of providing a switch control signal for a switch controlled to be turned on and off and a power supply control signal for an isolated power supply, the integrated device comprising:

a switch driving part generating the switch control signal so as to control on and off of the switch by the switch control signal; and

According to another aspect, an isolated power supply, comprising: an integrated device as described above, and an isolated power supply circuit, wherein:

the isolation power supply circuit comprises a transformer, the transformer comprises a first primary coil, a second primary coil and a secondary coil, one end of the second primary coil is grounded, a first resistor and a second resistor are connected to two ends of the second primary coil, the connection point of the first resistor and the second resistor is connected with the feedback end of the integrated device, the connection point of the first resistor and the second resistor is connected to the voltage supply end of the integrated device through a first diode, the voltage supply end is connected to one end of the first primary coil through a triode, the other end of the first primary coil is connected to the drain end of a built-in power tube in the integrated device, a first capacitor is connected between the emitter of the triode and the ground, the collector of the triode is connected with one end of the first primary coil, the base and the collector of the triode are connected with a third resistor, and a second diode is connected between the base of the triode and the ground, a second capacitor is connected between the collector of the triode and the ground, a series circuit of a third capacitor and a third diode is connected between the two ends of the first primary coil, the connection point of the third capacitor and the second diode is connected to one end of the first primary coil through a fourth resistor, one end of the secondary coil is used as a negative output end of output voltage, and the other end of the secondary coil is connected with the fourth diode and then used as a positive output end of the output voltage; and a capacitor is connected between the anode output end and the cathode output end, and a series circuit formed by a fifth resistor and a fourth capacitor is connected to two ends of the fourth diode.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 2 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a charge pump for charging according to one embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of a charge pump for discharging according to one embodiment of the present disclosure.

FIG. 8 shows a schematic diagram of an integrated device according to one embodiment of the present disclosure.

FIG. 9 shows a schematic diagram of an integrated device according to one embodiment of the present disclosure.

FIG. 10 shows a schematic diagram of a device according to one embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 12 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 13 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

FIG. 14 shows an isolated power supply control schematic according to one embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

According to one embodiment of the present disclosure, an integrated device of a charge control switch and a discharge control switch is provided.

Fig. 1 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure. As shown in fig. 1, the charge control switch 10 and the discharge control switch 20 are connected in series between the positive terminal B + of the battery pack 30 and the positive terminal P + of the charger/load. The charge control switch 10 and the discharge control switch 20 are NMOS transistors, the source S of the charge control switch 10 is connected to the positive terminal B + of the battery pack 30, the drain D of the charge control switch 10 is connected to the drain D of the discharge control switch 20, and the source S of the discharge control switch 20 is connected to the positive terminal P + of the charger/load. The gates G of the charge control switch 10 and the discharge control switch 20 are connected to the integrated device 40, respectively, and the integrated device 40 provides a charge control signal and a discharge control signal to control the on and off of the charge control switch 10 and the discharge control switch 20. The negative terminal P-of the charger/load is connected to the negative terminal B-of the battery pack 30.

As shown in fig. 1, the battery management system may further include an isolated power supply circuit 50, wherein the isolated power supply circuit 50 may be provided with a signal by the integrated device 40 to generate an output voltage by the isolated power supply circuit 50.

The control unit 60 may provide control signals to the integrated device 40, and the integrated device 40 generates the charging and discharging control signals and the control signal of the isolated power circuit according to the control signals provided by the control unit 60.

Wherein the control unit 60 may act as a master chip and the integrated device 40 may act as a slave chip, such that the integrated device 40 may be provided with input signals via the control unit 60.

Fig. 2 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure. The embodiment shown in fig. 2 differs from the embodiment shown in fig. 1 in that: in fig. 1, the charge control switch 10 and the discharge control switch 20 are connected in series and formed in the same current path, and in fig. 2, the charge control switch 10 and the discharge control switch 20 are provided in two current paths.

As shown in fig. 2, the source S of the charge control switch 10 is connected to the positive terminal B + of the battery pack 30, and the source S of the discharge control switch 20 is connected to the positive terminal B + of the battery pack 30. The drain D of the charge control switch 10 is connected to the positive terminal C + of the load, and the drain D of the discharge control switch 20 is connected to the positive terminal D + of the charger. Thus, in fig. 2, a separate charging path and a separate discharging path may be formed. The charging and discharging of the battery pack 30 is controlled by controlling the charge control switch 10 and the discharge control switch 20, respectively.

Fig. 3 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure. The embodiment shown in fig. 3 differs from the embodiment shown in fig. 1 in that: in fig. 1, the number of the charge control switches 10 and the number of the discharge control switches 20 are one, respectively, whereas in fig. 3, the number of the charge control switches 10 and the number of the discharge control switches 20 are two or more, respectively.

As shown in fig. 3, two or more charge control switches 10 are connected in parallel to form a charge control switch, and each of the charge control switches 10 connected in parallel receives a control signal from the integrated device 40 to be turned on or off. Two or more discharge control switches 20 are connected in parallel to form a charge control switch, and each of the discharge control switches 20 connected in parallel receives a control signal from the integrated device 40 to be turned on or off. In this way, the on-resistances of the charge control switch and the discharge control switch can be effectively reduced, thereby avoiding power loss.

Further, in the present disclosure, it is preferable that two or more discharge control switches 20 are connected in parallel only for the discharge control switch, and only one charge control switch 10 is used for the charge control switch.

In addition, the embodiment of fig. 2 may be changed with reference to the arrangement of the charge control switch and the discharge control switch in fig. 3. For example, the charge control switch and the discharge control switch of fig. 2 are provided in the form of a plurality of charge control switches and discharge control switches connected in parallel, respectively, or the discharge control switch is provided in the form of a plurality of discharge control switches connected in parallel.

Fig. 4 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure. The embodiment of fig. 4 differs from the embodiment of fig. 1 in that the embodiment of fig. 4 includes a precharge control switch 70.

The pre-charge control switch 70 is a PMOS transistor, and the drain D of the pre-control charge switch 70 is connected to the positive terminal B + of the battery pack 30, the source S of the pre-charge control switch 70 is connected to the drain of the charge control switch 10, and the gate G of the pre-charge control switch 70 receives the pre-charge control signal from the integrated device 40. Further, the pre-charge control switch 70 may be an NMOS transistor, and the source S of the pre-charge control switch 70 is connected to the positive terminal B + of the battery pack 30, the drain D of the pre-charge control switch 70 is connected to the drain of the charge control switch 10, and the gate G of the pre-charge control switch 70 receives the pre-charge control signal from the integrated device 40. Thus, during the pre-charging process, the pre-charging control switch 70 is controlled to be turned on and off by the pre-charging control signal provided by the integrated device 40, thereby implementing the pre-charging control of the battery management system. Further, a resistor may be connected in series between the positive terminal B + of the battery pack 30 and the precharge control switch 70.

It should be understood by those skilled in the art that the precharge control switch 70 shown in fig. 4 can also be provided in the embodiments shown in fig. 2 and fig. 3, etc., and the principle is the same, and will not be described herein again.

Fig. 5 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure. The embodiment of fig. 5 differs from the embodiment of fig. 1 in that the embodiment of fig. 5 includes a pre-discharge control switch 80.

The pre-discharge control switch 80 is an NMOS transistor, and the drain D of the pre-discharge control switch 80 is connected to the drain of the discharge control switch 20, the source S of the pre-discharge control switch 80 is connected to the positive terminal P + of the load, and the gate G of the pre-discharge control switch 80 receives a pre-discharge control signal from the integrated device 40. Further, the pre-discharge control switch 80 may be a PMOS transistor, and the source S of the pre-discharge control switch 80 is connected to the drain of the discharge control switch 20, the drain D of the pre-discharge control switch 80 is connected to the positive terminal P + of the load, and the gate G of the pre-discharge control switch 80 receives the pre-discharge control signal from the integrated device 40. In this way, during the pre-discharge process, the pre-discharge control signal provided by the integrated device 40 controls the on/off of the pre-discharge control switch 80, so as to implement the pre-discharge control of the battery management system. Further, a resistor may be connected in series between the positive terminal P + of the load and the pre-discharge control switch 80.

It should be understood by those skilled in the art that the pre-discharge control switch 80 shown in fig. 5 can also be provided in the embodiments shown in fig. 2 to 4, etc., and the principle thereof is the same, and will not be described herein again.

Fig. 6 shows a first charge pump unit 300 for charge control switch control according to an embodiment of the present disclosure.

As shown in fig. 6, the first charge pump unit 300 may include a circuit block, wherein the circuit block may include a first PMOS transistor 301, a second PMOS transistor 302, a first resistor 303, a third PMOS transistor 304, a first NMOS transistor 305, and a first inverter 306.

The source of the first PMOS transistor 301 and the first terminal of the first resistor 303 are connected to the source of the third PMOS transistor 304, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 301 is connected to the gate, and the drain of the first PMOS transistor 301 is connected to the source of the second PMOS transistor 302, the drain of the second PMOS transistor 302 is connected to the gate, the drain of the second PMOS transistor 302 is connected to the drain of the first NMOS transistor 305, and the source of the first NMOS transistor 305 is grounded. The drain of the second PMOS transistor 302 is connected to the other end of the first resistor 303 and the gate of the third PMOS transistor 304. The gate of the first NMOS transistor 305 is connected to the output of the first inverter 306. The drain of the third PMOS transistor 304 serves as a second connection point.

The input of the first inverter 306 is connected to the pulse signal (generated by the oscillator). And the pulse signal is also connected to the gate of the second NMOS transistor 307, the source of the second NMOS transistor 307 is grounded, and the drain of the second NMOS transistor 307 is connected to the drain of the third PMOS transistor 304 and constitutes a second connection point.

The first connection point may be connected to a positive terminal voltage VB + of the battery pack, the second connection point may be connected to one end of a first capacitor 310, the other end of the first capacitor 310 is connected to a cathode of a first diode 308, an anode of the first diode 308 is connected to the first voltage, a cathode of the first diode 308 is further connected to an anode of a second diode 309, a cathode of the second diode 309 is connected to one end of a second capacitor 311, the other end of the second capacitor 311 is connected to the positive terminal voltage VB + of the battery pack, and a connection point between the cathode of the second diode 309 and one end of the second capacitor 311 serves as an output terminal of the charge pump voltage VCP1 for charge control switch.

Fig. 7 shows a second charge pump unit 400 for discharge control switch control according to an embodiment of the present disclosure.

As shown in fig. 7, the second charge pump unit 400 may include a circuit block, wherein the circuit block may include a first PMOS transistor 401, a second PMOS transistor 402, a first resistor 403, a third PMOS transistor 404, a first NMOS transistor 405, and a first inverter 406.

The source of the first PMOS transistor 401 and the first end of the first resistor 403 are connected to the source of the third PMOS transistor 404, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 401 is connected to the gate, and the drain of the first PMOS transistor 401 is connected to the source of the second PMOS transistor 402, the drain of the second PMOS transistor 402 is connected to the gate, the drain of the second PMOS transistor 402 is connected to the drain of the first NMOS transistor 405, and the source of the first NMOS transistor 405 is grounded. The drain of the second PMOS transistor 402 is connected to the other end of the first resistor 403 and the gate of the third PMOS transistor 404. The gate of the first NMOS transistor 405 is connected to the output terminal of the first inverter 406. The drain of the third PMOS transistor 404 serves as a second connection point.

The input of the first inverter 406 is connected to the pulse signal (generated by the oscillator). And the pulse signal is also connected to the gate of the third NMOS transistor 407, the source of the third NMOS transistor 407 is grounded, and the drain of the third NMOS transistor 407 is connected to the drain of the third PMOS transistor 404 and constitutes a second connection point.

The first connection point may be connected to a positive terminal voltage VP + of the load/charger, the second connection point may be connected to one terminal of a third capacitor 410, the other terminal of the third capacitor 410 is connected to a cathode of a third diode 408, an anode of the third diode 408 is connected to the first voltage, a cathode of the third diode 408 is further connected to an anode of a fourth diode 409, a cathode of the fourth diode 409 is connected to one terminal of a fourth capacitor 411, the other terminal of the fourth capacitor 411 is connected to a positive terminal voltage VP + of the load/charger, and a connection point between the cathode of the fourth diode 409 and one terminal of the fourth capacitor 411 serves as an output terminal of the charge pump voltage VCP2 for the discharge control switch.

Fig. 8 shows a circuit diagram of an integrated device according to an embodiment of the present disclosure. In fig. 8, a charging integrated device 100 of the charging control switch 10 and a discharging integrated device 200 of the discharging control switch 20 are respectively shown. In this embodiment, the charge control switch 10 and the discharge control switch 20 are connected in series in the same current path, and the charge and discharge of the battery pack are controlled by controlling both the switches simultaneously.

The integrated device 100 will be described in detail below.

The charging integrated device 100 may include two of the above-described circuit blocks.

A first circuit block of the two circuit blocks may include a first PMOS transistor 101, a second PMOS transistor 102, a first resistor 103, a third PMOS transistor 104, a first NMOS transistor 105, and a first inverter 106.

The source of the first PMOS transistor 101 and the first end of the first resistor 103 are connected to the source of the third PMOS transistor 104, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 101 is connected to the gate, the drain of the first PMOS transistor 101 is connected to the source of the second PMOS transistor 102, the drain of the second PMOS transistor 102 is connected to the gate, the drain of the second PMOS transistor 102 is connected to the drain of the first NMOS transistor 105, and the source of the first NMOS transistor 105 is grounded. The drain of the second PMOS transistor 102 is connected to the other end of the first resistor 103 and the gate of the third PMOS transistor 104. The gate of the first NMOS transistor 105 is connected to the output terminal of the first inverter 106. The drain of the third PMOS transistor 104 serves as a second connection point. The first connection point of the first circuit module is connected to the charge pump voltage VCP1 for the charge control switch of the first charge pump circuit 300. The second connection point of the first circuit module is connected to the gate of the charge control switch 30.

The output terminal of the second inverter 107 is connected to the input terminal of the first inverter 106 of the first circuit block, and the second inverter 107 is connected to the charge enable signal CHG _ EN so as to charge the control switch 10 according to the charge enable signal.

The second of the two circuit blocks may include a first PMOS transistor 108, a second PMOS transistor 111, a first resistor 109, a third PMOS transistor 110, a first NMOS transistor 112, and a first inverter 113.

The source of the first PMOS transistor 108 and the first end of the first resistor 109 are connected to the source of the third PMOS transistor 110, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 108 is connected to the gate, the drain of the first PMOS transistor 108 is connected to the source of the second PMOS transistor 111, the drain of the second PMOS transistor 111 is connected to the gate, the drain of the second PMOS transistor 111 is connected to the drain of the first NMOS transistor 112, and the source of the first NMOS transistor 112 is grounded. The drain of the second PMOS transistor 111 is connected to the other end of the first resistor 109 and the gate of the third PMOS transistor 110. The gate of the first NMOS transistor 112 is connected to the output terminal of the first inverter 113, and the input terminal of the first inverter 113 is connected to the charge enable signal CHG _ EN. The drain of the third PMOS transistor 110 serves as a second connection point.

The first connection point of the second circuit module is connected to the charge pump voltage VCP1 for the charge control switch of the first charge pump circuit 300.

The second connection point of the second circuit module is connected to the drain of the fourth NMOS transistor 114, the drain of the fourth NMOS transistor 114 is connected to the gate, the source of the fourth NMOS transistor 114 is connected to the drain of the fifth NMOS transistor 115, the drain of the fifth NMOS transistor 115 is connected to the gate, and the source of the fifth NMOS transistor 115 is connected to the positive terminal voltage VB + of the battery pack. The drain of the fourth NMOS transistor 114 is connected to a first terminal of the second resistor 116 and to the gate of the sixth NMOS transistor 117, and a second terminal of the second resistor 116 is connected to the positive terminal voltage VB + of the battery pack. The source of the sixth NMOS transistor 117 is connected to the positive terminal voltage VB + of the battery pack, and the drain of the sixth NMOS transistor 117 is connected to the drain of the third PMOS transistor 104 of the first circuit block.

The discharge integration device 200 will be described in detail below.

The discharge integrated device 100 may include two of the above-described circuit blocks.

A first circuit block of the two circuit blocks may include a first PMOS transistor 201, a second PMOS transistor 202, a first resistor 203, a third PMOS transistor 204, a first NMOS transistor 205, and a first inverter 206.

The source of the first PMOS transistor 201 and the first end of the first resistor 203 are connected to the source of the third PMOS transistor 204, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 201 is connected to the gate, the drain of the first PMOS transistor 201 is connected to the source of the second PMOS transistor 202, the drain of the second PMOS transistor 202 is connected to the gate, the drain of the second PMOS transistor 202 is connected to the drain of the first NMOS transistor 205, and the source of the first NMOS transistor 205 is grounded. The drain of the second PMOS transistor 202 is connected to the other end of the first resistor 203 and the gate of the third PMOS transistor 204. The gate of the first NMOS transistor 205 is connected to the output terminal of the first inverter 206. The drain of the third PMOS transistor 204 serves as a second connection point. The first connection point of the first circuit module is connected to the charge pump voltage VCP2 for the charge control switch of the second charge pump circuit 400. The second connection point of the first circuit module is connected with the grid of the discharge control switch.

An output terminal of the third inverter 207 is connected to an input terminal of the first inverter 206 of the first circuit block, and an input terminal of the third inverter 207 is connected to the discharge enable signal DSG _ EN so as to discharge the control switch 10 according to the discharge enable signal.

The second of the two circuit blocks may include a first PMOS transistor 208, a second PMOS transistor 211, a first resistor 209, a third PMOS transistor 210, a first NMOS transistor 212, and a first inverter 213.

The source of the first PMOS transistor 208 and the first terminal of the first resistor 209 are connected to the source of the third PMOS transistor 210, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 208 is connected to the gate, and the drain of the first PMOS transistor 208 is connected to the source of the second PMOS transistor 211, the drain of the second PMOS transistor 211 is connected to the gate, the drain of the second PMOS transistor 211 is connected to the drain of the first NMOS transistor 212, and the source of the first NMOS transistor 212 is grounded. The drain of the second PMOS transistor 211 is connected to the other end of the first resistor 209 and the gate of the third PMOS transistor 210. The gate of the first NMOS transistor 212 is connected to the output terminal of the first inverter 213, and the input terminal of the first inverter 213 is connected to the discharge enable signal DSG _ EN. The drain of the third PMOS transistor 210 serves as a second connection point.

The first connection point of the second circuit module is connected to the charge pump voltage VCP2 for the discharge control switch of the second charge pump circuit 400.

The second connection point of the second circuit module is connected to the drain of the seventh NMOS transistor 214, the drain of the seventh NMOS transistor 214 is connected to the gate, the source of the seventh NMOS transistor 214 is connected to the drain of the eighth NMOS transistor 215, the drain of the eighth NMOS transistor 215 is connected to the gate, and the source of the eighth NMOS transistor 215 is connected to the positive terminal voltage VP + of the load/charger. The drain of the seventh NMOS transistor 214 is connected to a first terminal of the third resistor 216 and to the gate of the ninth NMOS transistor 217, and a second terminal of the third resistor 216 is connected to the positive terminal voltage VP + of the load/charger. The source of the ninth NMOS transistor 217 is connected to the positive terminal voltage VP + of the load/charger, and the drain of the ninth NMOS transistor 217 is connected to the drain of the third PMOS transistor 204 of the first circuit block.

Fig. 9 shows a circuit diagram of an integrated device according to one embodiment of the present disclosure. In fig. 9, a charging integrated device 100 of the charging control switch 10 and a discharging integrated device 200 of the discharging control switch 20 are respectively shown. In this embodiment, the charge control switch 10 and the discharge control switch 20 are connected in series in different current paths, and charge and discharge of the battery pack are controlled by controlling the two switches separately.

The integrated device 100 will be described in detail below.

The discharge integration device 200 will be described in detail below.

The source of the first PMOS transistor 201 and the first end of the first resistor 203 are connected to the source of the third PMOS transistor 204, and the connection point constitutes a first connection point. The drain of the first PMOS transistor 201 is connected to the gate, the drain of the first PMOS transistor 201 is connected to the source of the second PMOS transistor 202, the drain of the second PMOS transistor 202 is connected to the gate, the drain of the second PMOS transistor 202 is connected to the drain of the first NMOS transistor 205, and the source of the first NMOS transistor 205 is grounded. The drain of the second PMOS transistor 202 is connected to the other end of the first resistor 203 and the gate of the third PMOS transistor 204. The gate of the first NMOS transistor 205 is connected to the output terminal of the first inverter 206. The drain of the third PMOS transistor 204 serves as a second connection point. The first connection point of the first circuit module is connected to the charge pump voltage VCP2 for the charge control switch of the second charge pump circuit 400. The second connection point of the first circuit module is connected to the gate of the discharge control switch 40.

Fig. 10 shows a schematic block diagram of a high-side drive section of an integrated device according to the present disclosure.

The charging integrated device outputs a charging control signal to the charging control switch through the pin CHG. And receives the charge enable signal through pin CHG _ EN. The discharging integrated device outputs a discharging control signal to the discharging control switch through a pin DSG. And receives the discharge enable signal through pin DSG _ EN.

The first charge pump unit receives a charge pump enable signal through a pin CP _ EN, supplies a charge pump voltage VDDCP1 through a pin, and connects an external capacitance through pins FC1A and FC 1B.

The second charge pump unit receives a charge pump enable signal (which is the same pin) through a pin CP _ EN, supplies a charge pump voltage VDDCP2 through the pin, and connects an external capacitance through pins FC2A and FC 2B.

The integrated device may further include a first oscillation unit that generates an oscillation signal as a pulse signal supplied to the input terminal of the first inverter 306 according to the positive terminal voltage BAT of the battery pack, and a second oscillation unit. The second oscillating unit generates an oscillating signal as a pulse signal supplied to the input terminal of the above-described first inverter 406, based on the positive terminal voltage PACK of the load/charger.

The integrated device may further include a pre-discharge level shift unit, wherein the pre-discharge level shift unit may receive a pre-discharge enable signal through a pin PDSG _ EN to perform a pre-discharge operation. And a pre-discharge control signal may be provided through the pin PDSG, which is provided to the pre-discharge control switch 80, thereby implementing management of pre-discharge. The pre-discharge level conversion unit may generate the pre-discharge control signal according to the charge pump voltage VDDCP2 and the voltage PACK of the positive terminal of the load/charger.

The integrated device may further include a load detection unit for detecting whether a load is connected according to the voltage BAT of the positive terminal of the battery PACK and the voltage PACK of the positive terminal of the load/charger.

The integrated device may further include a charger detection unit for detecting whether or not a charger is connected, based on the voltage BAT of the positive terminal of the battery PACK and the voltage PACK of the positive terminal of the load/charger. Wherein the charger detection unit provides a charger detection signal through pin CHA _ IN.

The integrated device may further include a first voltage conversion unit for generating the first voltage (e.g., 12V) described above. The first voltage conversion unit may generate the first voltage from a voltage BAT of a positive terminal of the battery pack. And the first voltage is supplied to the first charge pump unit and the second charge pump unit. The first voltage may also be provided to the outside of the device through pin VDD12 for use by other components.

The integrated device may further include a second voltage converting unit for generating a second voltage (e.g., 5V). The second voltage converting unit may generate the second voltage from the voltage BAT of the positive terminal of the battery pack, or may generate the second voltage from the first voltage of the first voltage converting unit. The second voltage may be supplied to the first oscillation unit, the second oscillation unit, the charging integrated device, the discharging integrated device, the pre-charge level conversion unit, the pre-discharge level conversion unit, and the like. The second voltage may also be provided to the outside of the device through pin VDD5 for use by other components.

The integrated device may also include a BAT pin, a PACK pin, a GND pin, and the like.

According to the integrated device disclosed by the invention, the charge control switch and the discharge control switch which are arranged between the positive terminal of the battery pack and the positive terminal of the load/charger can be effectively and stably controlled, and low power consumption and the like can be realized. And the charge and discharge control switch realizes independent control, can already bear high voltage, and can adopt a universal or independent charge and discharge path.

Fig. 11-13 illustrate battery management systems according to various embodiments of the present disclosure.

First, as shown in fig. 13, other components for battery pack control may be integrated with the respective parts of the integrated device in one chip (components indicated by a dashed line frame) to form a battery management chip. Wherein, the chip for battery management may include: parts of an integrated device as described above; the gating unit is used for selecting the battery sections in the battery pack; the acquisition unit is used for measuring the battery section selected by the gating unit; and a logic control unit receiving the output signal of the acquisition unit and generating a logic control signal to be supplied at least to the high-side driving part.

The battery management system will be described in detail below. As shown in fig. 11, the battery management system may include the integrated device described above; a charging control switch and a discharging control switch which are turned on or off by the control of the integrated device so as to charge or discharge the battery pack; a controller (MCU) to provide control signals to the integrated device. As shown in figure 13 of the drawings, in which,

in addition, as shown in fig. 13, a battery management system includes: the battery management chip as described above; a charging control switch and a discharging control switch which are switched on or off by the control of the battery management chip so as to charge or discharge the battery pack; and the controller provides a control signal for the battery management chip.

As shown in fig. 11, the battery management system may include an integrated device and a charge control switch and a discharge control switch. Wherein the integrated device may provide control signals for the charge control switch and the discharge control switch. A resistor R2 may be connected between the gate and the source of the charge control switch, and a resistor R3 may be connected between the gate and the source of the discharge control switch. The integrated device may also provide a precharge control signal to the precharge control switch.

The BAT terminal of the integrated device may be connected to the positive terminal of the battery pack through a filter circuit formed by resistors R1 and C1. In addition, the FC1A and FC1B terminals of the integrated device may be connected with a capacitor C3, the VDDCP1 terminal may be connected to the BAT terminal through a capacitor C2, the VDDCP2 terminal of the integrated device may be connected to the PACK terminal through a resistor C4, and the PACK terminal may be connected to PACK + through a resistor R11, and a capacitor C6 may be connected between the PACK + and a ground terminal. The capacitor C5 may be connected to the FC2 and FC2 terminals of the integrated device. In addition, the PACKDIV terminal of the integrated device may be connected to one end of the resistor R4, the other end of the resistor R4 is connected to one end of the resistor R5, the other end of the resistor R5 is grounded, and a connection point of the resistor R4 and the resistor R5 may be connected to the ADC.

An isolated power supply circuit is shown in each of fig. 11 to 13, and the output of the isolated power supply circuit may provide a voltage for the MCU, fig. 11 shows that the integrated device may receive a control signal of the MCU; fig. 12 shows that the gating unit, the collecting unit, and the logic control unit may be integrated in one device, and receive the control signal of the MCU and provide the control signal for the integrated device; as shown in fig. 13, each part of the integrated device may be integrated with the gating unit, the collecting unit, and the logic control unit in one chip.

The circuit for isolating a power supply includes: the isolation power supply control part receives the battery side voltage of the battery pack, generates a power supply control signal for controlling the first primary coil according to a feedback voltage formed by the second primary coil, and generates a power supply output voltage through the first secondary coil according to the power supply control signal.

The feedback end of the isolation power supply control part receives the feedback voltage, the feedback voltage is formed by resistors connected to two sides of a second primary coil, the isolation power supply control part generates a supply voltage according to the voltage measured by the battery, and the supply voltage is provided to the second primary coil.

The present disclosure also provides an isolated power supply, as shown in fig. 11 to 13, wherein the isolated power supply circuit may include a transformer, which may include a first primary coil PL1, a second primary coil PL2, and a secondary coil SL. One end of the second primary coil PL2 is grounded, and a first resistor R6 and a second resistor R7 are connected to both ends of the second primary coil, a connection point of the first resistor and the second resistor is connected to the feedback terminal FB of the integrated device, a connection point of the first resistor and the second resistor is connected to the voltage supply terminal VDD of the integrated device through a first diode D3, the voltage supply terminal is connected to one end of the first primary coil through a triode, the other end of the first primary coil is connected to the DRAIN terminal DRAIN of the built-in power tube in the integrated device, a first capacitor C7 is connected between the emitter of the triode and the ground, the collector of the triode is connected to one end of the first primary coil, the base and the collector of the triode are connected to a third resistor R8, a second diode D1 is connected between the base of the triode and the ground, a second capacitor C8 is connected between the collector of the triode and the ground, a series circuit of the third capacitor C9 and a third diode D2 is connected between both ends of the first primary coil, a connection point of the third capacitor C9 and the second diode D2 is connected to one end of the first primary coil through a fourth resistor R9, one end of the secondary coil is used as a negative output end of the output voltage, and the other end of the secondary coil is connected to the fourth diode D4 and then used as a positive output end of the output voltage; capacitors C10 and C11 are connected between the positive output terminal and the negative output terminal, and a series circuit formed by a fifth resistor R10 and a fourth capacitor is connected to both ends of the fourth diode.

Furthermore, although the integrated device is described above with reference to battery pack control, it will be understood by those skilled in the art that the integrated device may also provide a drive signal for any other switch, and therefore the present disclosure also provides an integrated device capable of providing a switch control signal for a switch controlled to be turned on and off and a power supply control signal for an isolated power supply, the integrated device comprising: a switch driving part generating the switch control signal so as to control on and off of the switch by the switch control signal; and an isolated power supply control section that provides a power supply control signal of the isolated power supply to control a circuit of the isolated power supply by the power supply control signal, thereby generating an output voltage by the isolated power supply.

Further, according to a further embodiment of the present disclosure, fig. 14 shows an isolated power supply control section according to one example of the present disclosure. As shown in fig. 14, the isolated power supply control section may receive the feedback voltage through a pin FB, and may receive VDD through a pin, and may receive the detection current through a pin CS (for example, the current may be detected by a current sampling resistor connected to the charge and discharge loop), and may output the power supply control signal through a pin DRAIN.

The isolation power supply control unit may generate the under-voltage lock signal and the under-voltage release signal according to VDD. The feedback voltage sampling unit receives the feedback voltage and transmits the feedback voltage to the error amplifier, the error amplifier generates a comparison voltage according to the feedback voltage and a reference voltage (the isolated power supply control part may also comprise a reference voltage generating unit), the comparison voltage may be output to the timer and the comparison unit, the timer outputs a maximum switching frequency and a minimum switching frequency to the logic unit, the comparison unit generates a PWM stop signal (for example, the comparison voltage may be compared with the voltage from the current sampling unit) according to the comparison voltage and the voltage from the current sampling unit, the current sampling unit may further provide an overcurrent protection threshold value and a minimum sampling current signal to the logic unit, the logic unit further receives a protection signal of the state control unit, the DEM/QR detection unit generates a control signal and provides the control signal to the logic unit, and the signals generated by the state control unit and the DEM/QR detection unit are generated based on the feedback voltage, the logic unit provides a PWM signal according to the received signal, and the PWM signal is provided to a driving device (built-in power tube), and the drain terminal of the driving device provides a power supply control signal.

The battery pack of the present disclosure may be a lithium battery pack, and may be used in various scenes in which a rechargeable battery is used, such as an electric automobile, an electric bicycle, an electric motorcycle, a portable tool, a backup battery, and the like.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. An integrated device capable of providing a charge control signal and a discharge control signal to a charge control switch and a discharge control switch that control charging and discharging of a battery pack, and capable of providing a power supply control signal to an isolated power supply, a series circuit of the charge control switch and the discharge control switch being connected between a positive terminal of the battery pack and a positive terminal of a load/charger, the integrated device comprising:

2. The integrated device of claim 1, wherein a source of the charge control switch is connected to a positive terminal of the battery pack, and a drain of the charge control switch is connected to a drain of the discharge control switch, and a source of the discharge control switch is connected to a positive terminal of the charger/load, gates of the charge control switch and the discharge control switch are respectively connected to an integrated device, and the integrated device provides the charge control signal and the discharge control signal to control on and off of the charge control switch and the discharge control switch.

3. The integrated device of claim 1, wherein a source of the charge control switch is connected to a positive terminal of the battery pack, and a source of the discharge control switch is connected to a positive terminal of the battery pack, a drain of the charge control switch is connected to a positive terminal of a load, and a drain of the discharge control switch is connected to a positive terminal of a charger, gates of the charge control switch and the discharge control switch are respectively connected to the integrated device, and the integrated device provides the charge control signal and the discharge control signal to control on and off of the charge control switch and the discharge control switch.

4. The integrated device according to claim 1, wherein the charge control switch is a charge control switch in which two or more NMOS transistors are connected in parallel, and/or the discharge control switch is a discharge control switch in which two or more NMOS transistors are connected in parallel.

5. The integrated device of claim 1, further comprising a precharge control switch, the precharge control switch being a PMOS transistor, a drain of the precharge control switch being connected to the positive terminal of the battery pack, a source of the precharge control switch being connected to the drain of the charge control switch, and a gate of the precharge control switch receiving a precharge control signal from the integrated device; or the pre-charge control switch is an NMOS transistor, the source of the pre-charge control switch is connected to the positive terminal of the battery pack, the drain of the pre-charge control switch is connected to the drain of the charge control switch, and the gate of the pre-charge control switch receives a pre-charge control signal from the integrated device; and/or

6. The integrated device of claim 5, wherein the integrated device provides a charge control signal to a gate of the charge control switch that is higher than a battery-side voltage of the positive terminal of the battery pack by a first voltage, and the integrated device provides a discharge control signal to a gate of the discharge control switch that is higher than a load/charger-side voltage of the positive terminal of the load/charger by the first voltage.

7. The integrated device of claim 6, further comprising a first charge pump unit that generates a charge control switch charge pump voltage of a sum of the battery side voltage and the first voltage, and the integrated device generates a charge control signal based on the charge control switch charge pump voltage; and/or

8. The integrated device according to claim 7, wherein the high-side driving section includes a first oscillation unit that generates an oscillation signal for the charge control signal and a second oscillation unit that generates an oscillation signal for the discharge control signal.

9. The integrated device of claim 8, further comprising a precharge level conversion unit that provides a precharge control signal to control the precharge control switch by the precharge control signal if a precharge control switch is included.

10. The integrated device of claim 9, further comprising a pre-discharge level shift unit that provides a pre-discharge control signal to control the pre-discharge control switch by the pre-discharge control signal if included.

11. The integrated device of claim 10,

the battery pack connection device further comprises a load detection unit, wherein the load detection unit detects whether the battery pack is connected with a load or not; and/or

12. The integrated device of claim 1, wherein the isolated power supply control portion comprises:

the state control unit provides a protection signal according to the feedback voltage sampling unit;

the DEM/QR detection unit generates a DEM/QR control signal according to the feedback voltage sampling unit;

13. The integrated device of claim 12, wherein the isolated power supply control further comprises an under-voltage-lockout cell, the under-voltage-lockout voltage generating an under-voltage-lockout signal and an under-voltage-release signal based on an input voltage.

14. A chip for battery management, comprising:

portions of an integrated device according to any one of claims 1 to 13; and

the gating unit is used for selecting the battery sections in the battery pack;

15. A battery management system, comprising:

an integrated device as claimed in any one of claims 1 to 13;

a controller to provide control signals to the integrated device.

16. A battery management system, comprising:

the chip for battery management according to claim 14;

and the controller provides a control signal for the battery management chip.

17. The battery management system of claim 15 or 16, wherein the isolated power supply circuit provides power to the controller in response to a power control signal from the isolated power supply control.

18. The battery management system of claim 17, wherein the circuit to isolate the power source comprises:

19. The battery management system of claim 18, wherein the feedback terminal of the isolated power control receives the feedback voltage, the feedback voltage is formed by a resistor connected across a second primary winding, the isolated power control generates a supply voltage from the battery voltage, and the supply voltage is provided to the second primary winding.

20. An integrated device capable of providing a switch control signal to a switch and a power supply control signal to an isolated power supply, the switch being controlled to turn on and off, the integrated device comprising:

21. An isolated power supply, comprising:

an integrated device as claimed in any one of claims 1 to 13; and

an isolated power supply circuit, wherein: the isolation power supply circuit comprises a transformer, the transformer comprises a first primary coil, a second primary coil and a secondary coil, one end of the second primary coil is grounded, a first resistor and a second resistor are connected to two ends of the second primary coil, the connection point of the first resistor and the second resistor is connected with the feedback end of the integrated device, the connection point of the first resistor and the second resistor is connected to the voltage supply end of the integrated device through a first diode, the voltage supply end is connected to one end of the first primary coil through a triode, the other end of the first primary coil is connected to the drain end of a built-in power tube in the integrated device, a first capacitor is connected between the emitter of the triode and the ground, the collector of the triode is connected with one end of the first primary coil, the base and the collector of the triode are connected with a third resistor, and a second diode is connected between the base of the triode and the ground, a second capacitor is connected between the collector of the triode and the ground, a series circuit of a third capacitor and a third diode is connected between the two ends of the first primary coil, the connection point of the third capacitor and the second diode is connected to one end of the first primary coil through a fourth resistor, one end of the secondary coil is used as a negative output end of output voltage, and the other end of the secondary coil is connected with the fourth diode and then used as a positive output end of the output voltage; and a capacitor is connected between the anode output end and the cathode output end, and a series circuit formed by a fifth resistor and a fourth capacitor is connected to two ends of the fourth diode.