JP3728622B2 - Charger - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charging device, and more particularly to a charging device that accumulates electric energy in a capacitor bank including a plurality of electric double layer capacitors as power elements.
[0002]
[Prior art]
Conventionally, methods such as constant current charging, constant voltage charging, constant voltage pulse charging, and the like are used for charging secondary batteries such as lead storage batteries and alkaline storage batteries. When a secondary battery is charged by these charging methods, the change in terminal voltage due to charging is very small. Therefore, when detecting the end state (end time) of charging, a minute voltage fluctuation is detected, or the battery It was necessary to adopt a technique such as detecting a temperature change. Therefore, in order to accurately detect the charging state and perform the charging operation efficiently, the configuration and control of the apparatus are complicated, and there is a problem that the apparatus is enlarged and the manufacturing cost is increased.
[0003]
On the other hand, in recent years, application of a charging circuit (apparatus) including a capacitor type storage battery such as an electric double layer capacitor as a driving power source for an electric vehicle or the like has been studied.
In general, a voltage (charge voltage) V across a capacitor including an electric double layer capacitor is represented by the following equation, where Q is the charge amount and C is the capacitor capacity.
V = Q / C (11)
The charge amount Q is expressed by the following equation, where IB is a current flowing through the capacitor (charging current) and t is a charging time.
Q = IB · t (12)
[0004]
Therefore, for example, as shown in FIG. 8, by supplying a predetermined charging current IB from the power supply circuit 100 to the capacitor bank 200 including a plurality of electric double layer capacitors C101 to C104, the electric double layer capacitor C101 is provided. A charge corresponding to the current value is accumulated in each of .about.C104. Here, by performing a charging operation by connecting a plurality of electric double layer capacitors C101 to C104 constituting the capacitor bank 200 in series, it is possible to configure a charging device in which the combined capacitance is reduced and the current value of the charging current is reduced. .
[0005]
In FIG. 8, reference numerals 301 to 304 denote voltage monitoring circuits (or parallel monitors), which are connected between terminals of the electric double layer capacitors C101 to C104 so that the charging voltage does not exceed the withstand voltage of the electric double layer capacitors. Is connected in parallel to detect and monitor the charging voltage value, and when the charging voltage value exceeds the reference voltage withstand voltage (guaranteed voltage), the electric double layer capacitor is bypassed by bypassing the charging current to the electric double layer capacitor. Has a function of stopping the charging operation.
[0006]
As described above, according to the charging device including the capacitor-type storage battery, the charge amount Q stored in the capacitor increases in proportion to the lapse of the charging time t, so that the charging voltage V of the capacitor also increases with the charging time t. In addition to the above-mentioned characteristics, it has the advantages that it is extremely light compared to the secondary batteries such as the lead storage battery and alkaline storage battery described above, can be rapidly charged, and has a long cycle life due to repeated charge and discharge. are doing. In such an electric double layer capacitor, for example, Japanese Patent Application Laid-Open No. 7-87668 discloses that a charging method for supplying a constant current is used to improve charging efficiency.
[0007]
[Problems to be solved by the invention]
However, the above-described prior art has the following problems.
(1) Since the charging device to which the electric double layer capacitor is applied has a characteristic that the charging voltage V of the capacitor increases with the charging time t, the charging voltage is detected and monitored as shown in FIG. Therefore, it is necessary to connect a voltage monitor circuit for each electric double layer capacitor in parallel. For this reason, there has been a problem that the scale of the charging device becomes extremely large and the product cost increases.
[0008]
(2) When the charging current is bypassed by the voltage monitor circuit, the amount of heat W corresponding to the power consumption and the number of connections of the voltage monitor circuit (that is, the number of connections of the electric double layer capacitor) is generated. The size reduction of the device was made more difficult. The amount of heat W generated when the charging current is bypassed by the voltage monitor circuit is expressed by the following equation (13), where IB is the charging current and VL is the terminal voltage (withstand voltage withstand voltage) of the electric double layer capacitor. The amount of heat corresponding to the power consumption of the voltage monitor circuit is generated, and the amount of heat proportional to the number n of the voltage monitor circuits (electric double layer capacitors) is generated in the entire charging device.
W = IB ・ VL (13)
[0009]
(3) Furthermore, in a charging device to which an electric double layer capacitor is applied, the electric double layer capacitor can be rapidly charged while further improving the charging efficiency, and the charging voltage of the capacitor can be used for future practical use. Therefore, there is a strong demand to accurately control the charging operation. Therefore, it is necessary to further improve the degree of design freedom in order to realize such charging characteristics according to various needs.
[0010]
Therefore, in view of the above-described problems, the present invention can simplify the circuit configuration and improve the degree of freedom in design in a charging device to which an electric double layer capacitor is applied. An object of the present invention is to provide a charging device that can appropriately rapidly charge a double layer capacitor.
[0011]
[Means for Solving the Problems]
The charging device according to claim 1, wherein a power supply circuit that generates and outputs a charging voltage including a predetermined DC voltage or a pulsating current, an oscillation circuit that generates an output signal having an arbitrary signal width and an arbitrary period, and An intermittent charging circuit that intermittently outputs an output current generated based on the charging voltage at a predetermined timing of an output signal, and a plurality of capacitors or a plurality of capacitor stacks configured by stacking a plurality of capacitors A capacitor-type storage battery that stores electrical energy corresponding to the output current, and the plurality of capacitors or the plurality of capacitor stacks are connected in series in synchronization with a predetermined timing of the output signal. A connection state switching circuit for controlling switching. The connection state switching circuit connects the plurality of capacitors, or the plurality of capacitor stacks in series from parallel to each other at the timing when the output current is output from the intermittent charging circuit, Alternatively, electrical energy corresponding to the output current is accumulated in each capacitor stack, and at the timing when the output current from the intermittent charging circuit is cut off, the plurality of capacitors or the plurality of capacitor stacks are connected to each other. Connected in series to parallel to equalize the charging voltage charged in each capacitor or each capacitor stack. It is characterized by that.
[0013]
Claim 2 The charging device according to claim 1 In the charging device described above, the charging device is connected to the plurality of capacitors by the connection state switching circuit. S A voltage monitor circuit is provided for detecting and monitoring the charging voltage charged in the capacitor or the capacitor stack when the capacitor stacks or the capacitor stacks are connected in parallel.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a charging device according to the present invention will be described in detail with reference to an embodiment.
<First Embodiment>
A first embodiment of a charging device according to the present invention will be described with reference to the drawings.
FIG. 1 is a schematic circuit diagram showing a first embodiment of a charging apparatus according to the present invention.
[0015]
As shown in FIG. 1, the charging apparatus according to the present embodiment includes a power supply circuit 10 that supplies a predetermined DC voltage, an oscillation circuit 20 that outputs a pulse signal at a predetermined timing, and a predetermined timing of the pulse signal. An intermittent charging circuit 30 for intermittently supplying a charging current IA based on the DC voltage Vin, a charging capacitor 50 including a plurality of electric double layer capacitors (hereinafter simply referred to as “capacitors”), and the pulse signal A connection state switching circuit 40 that switches and controls a connection state between a plurality of capacitors constituting the charging capacitor 50 at a predetermined timing, and a voltage monitor circuit 60 that detects and monitors the voltage charged in the charging capacitor 50. Configured.
[0016]
Each configuration will be described below.
FIG. 2 is a schematic configuration diagram illustrating an example of the intermittent charging circuit 30 applied to the charging device according to the present embodiment. FIG. 3 illustrates a charging capacitor 50 and connection state applied to the charging device according to the present embodiment. FIG. 4 is a schematic configuration diagram illustrating an example of the switching circuit 40, FIG. 4 is a timing chart illustrating switching control of the connection state of the charging capacitor 50 by the connection state switching circuit 40, and FIG. 5 is applied to the connection state switching circuit 40. It is a schematic block diagram which shows an example of the selector switch used.
[0017]
The power supply circuit 10 supplies a DC voltage necessary for generating a predetermined charging current IA in the intermittent charging circuit 30 described later between the high potential side power supply line HL and the low potential side power supply line LL. Note that the power supply circuit is not limited to a constant voltage supplied from a battery power source or the like as long as it can supply a predetermined DC voltage, and rectifies an AC voltage of a commercial AC power supply (for example, AC 100 V) to obtain a predetermined voltage. Even a pulsating flow obtained by extracting only a voltage component of the polarity or a rectified and smoothed AC voltage can be applied satisfactorily.
The oscillation circuit 20 generates a pulse signal Pa having a predetermined timing, that is, an arbitrary signal width and an arbitrary period, and outputs the pulse signal Pa to the intermittent charging circuit 30 and the connection state switching circuit 40. Here, the pulse signal Pa generated and output by the oscillation circuit 20 is output at an arbitrary timing independent of the DC voltage supply cycle in the power supply circuit 10 described above.
[0018]
The intermittent charging circuit 30 is based on the timing of the pulse signal Pa output from the oscillation circuit 20 and the DC voltage V supplied from the power supply circuit 10. _in Is generated and supplied to a charging capacitor 50 described later intermittently.
Specifically, as shown in FIG. 2, the intermittent charging circuit 30 includes a switching transistor (hereinafter referred to as “switching FET”) 31 and an inductance (coil) L1 connected in series to the high potential side power line HL. The resistor 33 for detecting current, the amplifier 33 that receives the potential difference between both ends of the resistor R1, the output of the amplifier 33 as one (−) input, and the output of the PWM (Pulse Width Modulation) oscillation circuit 35 as the other The input of (+) is the comparator 34, the output of the comparator 34, the output signal (pulse signal Pa) of the oscillation circuit 20, and the output signal (control signal Sc) of the voltage monitor circuit 60 to be described later. 3-input logic connected to the gate terminal of the switching FET 31 product An element (hereinafter referred to as an “AND gate”) 32, a switching FET 31, and a rectifying element D1 connected between a contact point between the inductance L1 and the low-potential-side power line LL.
[0019]
Here, the PWM oscillator 35 connected to the + side input terminal of the comparator 34 outputs a pulse wave having a sawtooth signal waveform, for example, at a predetermined cycle. As the intermittent charging circuit 30 shown in FIG. 2, for example, a circuit in which a part of the configuration is integrated and marketed as a single IC can be applied. The configuration shown in the present embodiment is a circuit configuration to which a general DC-DC converter is applied, and does not limit the configuration of the present invention.
[0020]
That is, the intermittent charging circuit 30 receives the signal from the power supply circuit 10 based on the output of the comparator 34 when the pulse signal Pa from the oscillation circuit 20 and the control signal Sc from the voltage monitor circuit 60 are at a high level. The supplied DC voltage Vin is converted into a predetermined constant voltage and applied to the resistance element R1, and the switching FET 31 is changed according to the voltage drop at the both ends of the resistance element R1 (that is, the current value flowing down the resistance element R1). It has the function of what is called a DC-DC converter which performs conduction | electrical_connection / cut-off control.
[0021]
Therefore, in the intermittent charging circuit 30, the voltage drop of the resistance element R 1 (corresponding to the charging current IA supplied to the charging capacitor 50) by the comparator 34 and the signal voltage of the sawtooth pulse signal from the PWM oscillator 35. When the comparison process is performed and the voltage drop of the resistance element R1 becomes small (the charging current value becomes small), a high level is outputted to the input terminal of the AND gate 32, the conduction of the switching FET 31 is controlled, and the resistance element R1 When the voltage drop increases (the charging current value increases), a low level is output to the input terminal of the AND gate 32. Thereby, a charging current IA is generated at a predetermined timing and output to the charging capacitor 50. A specific operation will be described later.
[0022]
The connection state switching circuit 40 performs control to switch the connection states of a plurality of capacitors constituting the charging capacitor 50 in series or in parallel based on the timing of the pulse signal Pa output from the oscillation circuit 20 described above. In particular, in the above-described intermittent charging circuit 30, the output from the oscillation circuit 20 to the AND gate 32 is at a high level, and the switching FET 31 is turned on according to the output of the comparator 34. In synchronization with the timing at which the charging current IA is supplied, the plurality of capacitors are switched to the serial connection state, and the switching FET 31 is in the cut-off (OFF) state, and in synchronization with the timing at which the supply of the charging current IA is stopped. Then, control is performed to switch the capacitors to the parallel connection state.
[0023]
The charging capacitor 50 includes a plurality of electric double layer capacitors, and the connection state between the capacitors is switched by the connection state switching circuit 40 based on the timing of the pulse signal Pa output from the oscillation circuit 20 described above.
Specifically, as shown in FIG. 3, the connection state switching circuit 40 and the charging capacitor 50 are provided between the high potential side power supply line HL and the low potential side power supply line LL, with a capacitor C1, a changeover switch SW11, and a capacitor C2. The changeover switch SW12, the capacitor C3, the changeover switch SW13, and the capacitor C4 are sequentially connected in series via the contacts N11, N12, N21, N22, N31, and N32.
[0024]
Further, selector switches SW21 to SW23 are provided between the high potential side power supply line HL and the contact N12, between the high potential side power supply line HL and the contact N22, and between the high potential side power supply line and the contact N32, respectively. Changeover switches SW31 to SW33 are provided between the line LL and the contact point N11, between the low potential side power supply line LL and the contact point N21, and between the low potential side power supply line LL and the contact point N31, respectively.
Here, as shown in FIG. 4, the changeover switches SW11 to SW13 are controlled to perform ON / OFF operations all at a predetermined timing based on the pulse signal Pa output from the oscillation circuit 20. Further, the change-over switches SW21 to SW23 and SW31 to 33 are controlled so as to perform ON / OFF operations all at the same time as the change-over switches SW11 to SW13.
[0025]
As described above, the connection state switching circuit 40 and the charging capacitor 50 applied to this embodiment include the capacitors C1 to C4 and the changeover switches SW11 to SW13 that switch the connection states of these capacitors C1 to C4 in series or in parallel. , SW21 to SW23, SW31 to SW33, a so-called capacitor bank is configured.
[0026]
In addition, as a specific configuration of the above-described change-over switches SW11 to SW13, SW21 to SW23, SW31 to SW33, as shown in FIG. 5, for example, based on a pulse signal Pa output from the oscillation circuit 20, a predetermined value is used. A photodiode group PD that emits light of a wavelength, a light receiving element PS that receives a light from the photodiode group PD to generate a potential difference, and a field effect transistor MOST that is electrically conductive based on the potential difference. A so-called photocoupler (also referred to as an optical coupling transistor) can be used. According to the changeover switch having such a configuration, the input side (pulse signal Pa) and the output side (switch operation) can be electrically separated, and the conduction control corresponding to the signal level of the pulse signal Pa accurately. Can be realized.
[0027]
The voltage monitor circuit 60 is connected in parallel with the charging capacitor 50 between the high potential side power supply line HL and the low potential side power supply line LL, and the amount of charge accumulated in the capacitors C1 to C4 is converted into a monitor voltage (charging voltage). ) And a comparison with a predetermined reference voltage (withstand voltage guaranteed voltage) value to determine whether or not the monitor voltage value has reached the reference voltage value. When the monitor voltage value reaches the reference voltage value, the control signal Sc (low level) is output to the AND gate 32 of the intermittent charging circuit 30, and the supply of the charging current IA to the charging capacitor 50 is cut off.
[0028]
Next, the operation of the charging apparatus having the above-described configuration will be described with reference to the drawings.
FIG. 6 is a timing chart showing the relationship between the switching control of the charging operation / voltage monitoring operation and each voltage level in the charging apparatus according to the present embodiment, and the change in the charging voltage of the charging capacitor. In addition, here, it demonstrates, referring the structure of the charging device (refer FIG. 1 thru | or FIG. 4) mentioned above as needed.
[0029]
First, a state where no charge is accumulated in the capacitors C1 to C4 constituting the charging capacitor 50, that is, a state where the charging voltage Vm is 0V will be described as an initial state. At this time, a high-level control signal Sc is output from the voltage monitor circuit 60 and is input to the input terminal (1) of the AND gate 32 of the intermittent charging circuit 30 shown in FIG.
When the high-level pulse signal Pa is output from the oscillation circuit 20 at a predetermined timing, the charging device is in a chargeable state. That is, when the pulse signal Pa is input to the input terminal (2) of the AND gate 32 of the intermittent charging circuit 30, the high-level control signal Sc is also input to the input terminal (1) of the AND gate 32. Therefore, in the AND gate 32, the conduction state of the switching FET 31 is controlled based on the output level from the comparator 34 input to the input terminal (3).
[0030]
Further, the pulse signal Pa is also input to the connection state switching circuit 40 in synchronization with the input to the intermittent charging circuit 30, and the change-over switches SW11 to SW13 shown in FIG. SW21 to SW23 and SW31 to SW33 are simultaneously set to the OFF state, and the capacitors C1 to C4 are connected in series.
Here, when the output from the amplifier circuit 33 is at a low level, that is, when the potential difference between both ends of the resistance element R1 is small and the flowing current value is small, the timing when the signal period (high level) output from the PWM oscillator 35 is reached. Therefore, since the high level signal is intermittently output from the comparator 34, all the inputs to the AND gate 32 are at the high level, the high level is applied to the gate electrode of the switching FET 31, and the switching FET 31 is Intermittently conducting. Thus, the voltage applied to the resistance element R1 through the inductance L1 is controlled to increase.
[0031]
On the other hand, when the output from the amplifier circuit 33 is at a high level, that is, when the potential difference between both ends of the resistance element R1 is large and the flowing current value is large, a low level signal is constantly output from the comparator 34. A low level is applied to the gate electrode, and the switching FET 31 is cut off.
Due to such intermittent conduction / cut-off operation of the switching FET 31, charges are intermittently accumulated in the inductance L1 via the diode D1, and the voltage applied to the resistance element R1 is controlled. Based on this voltage, the resistance element R1 The charging current IA is intermittently supplied to the charging capacitor 50 through the charging, and the charging operation is performed.
[0032]
In particular, the charging operation is performed by switching m capacitors C1 to Cm (in this embodiment, m = 4) to the serial connection state and performing charging operation, compared with the case where the charging capacitor 50 is configured by a single capacitor and charged. The capacitance value of the charging capacitor 50 is 1 / m ² (In this embodiment, since it can be reduced to 1/16), the charging current value can be reduced to 1 / m (= 1/4) times according to the division ratio by the capacitor.
[0033]
Next, when the low-level pulse signal Pa is output from the oscillation circuit 20 at a predetermined timing, the charging device enters a voltage monitoring state. That is, when the pulse signal Pa is input to the input terminal (2) of the AND gate 32 of the intermittent charging circuit 30, a low level is always applied to the gate electrode of the switching FET 31, and the switching FET 31 is controlled to be cut off. .
At this time, since the pulse signal Pa is also input to the connection state switching circuit 40 in synchronization with the input to the intermittent charging circuit 30, the change-over switches SW11 to SW13 shown in FIG. At the same time, the change-over switches SW21 to SW23 and SW31 to SW33 are simultaneously set to the ON state, and the capacitors C1 to C4 are connected in parallel. The capacitors C <b> 1 to C <b> 4 connected in parallel are commonly connected to a single voltage monitor circuit 60.
[0034]
As a result, the voltages across the terminals that are non-uniform due to variations in the capacitances of the capacitors C1 to C4 are made uniform by being commonly connected. It is possible to detect (monitor) the converted voltage at both ends as the charging voltage Vm of each of the capacitors C1 to C4 without variation. Further, by connecting the divided capacitors C1 to C4 in parallel, the capacity of the charging capacitor 50 can be increased and the load driving capability can be improved.
[0035]
As shown in FIG. 6, a specific voltage monitoring operation in the voltage monitor circuit 70 is performed by the above-described uniformed and detected charging voltage Vm and a reference voltage (withstand voltage) set in advance based on the withstand voltages of the capacitors C1 to C4. (Guaranteed voltage) Vz and if the charging voltage Vm is not equal to or higher than the reference voltage Vz, the AND gate 32 of the intermittent charging circuit 30 is set to the high level so that the charging operation is continuously performed after the voltage monitoring operation is completed. The control signal Sc is output. On the other hand, when the charging voltage Vm becomes equal to or higher than the reference voltage Vz, the low level control signal Sc is supplied to the AND gate 32 of the intermittent charging circuit 30 so as to forcibly cut off the supply of the charging current IA to the charging capacitor 50. Is output to end the charging operation.
[0036]
Therefore, by repeatedly performing the charging operation and the voltage monitoring operation as described above based on the pulse signal Pa having an arbitrary signal width and an arbitrary period set in the oscillation circuit 20, the DC voltage Vin in the power supply circuit 10 is obtained. The charging progress of the charging capacitor 50 can be controlled at an arbitrary timing without depending on the supply cycle (for example, the AC cycle of the commercial power supply), etc., thereby improving the design flexibility of the charging device. Thus, a quicker and more stable charging operation can be performed while guaranteeing the withstand voltage of the charging capacitor 50.
[0037]
In addition, during the voltage monitoring operation, the capacitors C1 to C4 constituting the charging capacitor 50 are connected in parallel so that the charging voltage Vm of the capacitors C1 to C4 can be made uniform, so that the charging voltage Vm can be monitored accurately. Since the charging voltage Vm can be detected by the single voltage monitor circuit 60, the scale of the charging device can be reduced, and the amount of heat generated and the power consumption in the voltage monitor circuit 60 can be reduced. Reduction can be achieved.
[0038]
<Second Embodiment>
Next, a second embodiment of the charging device according to the present invention will be described with reference to the drawings.
FIG. 7 is a schematic configuration diagram showing a second embodiment of the charging device according to the present invention. Here, about the structure equivalent to embodiment mentioned above, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
[0039]
In the first embodiment described above, the connection state switching circuit 40 applied to the charging device and the individual capacitors C1 to C4 constituting the charging capacitor 50 are switched to a series connection state or a parallel connection state at a predetermined timing. Although the configuration has been described, the present invention is not limited to this. Therefore, for example, the present invention can be applied to a stack capacitor in which a plurality of capacitors are stacked and controlled to be switched to a serial connection state or a parallel connection state based on the same technical idea.
[0040]
Specifically, as shown in FIG. 7, the connection state switching circuit 40 and the charging capacitor 50 according to the present embodiment include a plurality of capacitor stacks in which a plurality of capacitors are stacked, and the high potential side power supply line HL and the low potential Capacitor stacks CS1, CS2, CS3,... In which a plurality of capacitors C11 to C31, C12 to C32, C13 to C33,..., C1n to C3n are connected (laminated) in series between the power supply lines LL. , CSn and the capacitor stacks CS1, CS2, CS3,..., CSn, the capacitors C11 to C31, C12 to C32, C13 to C33,..., C1n to C3n are controlled in parallel for each layer. Changeover switch group SWA11 to SWA1m, SWA21 to SWA2m, SWA31 to SWA3m, and each capacitor stack CS , CS2, CS3,..., CSn are connected to the switch groups SWB1 to SWBm that control the series connection of each other, and the capacitor stacks CS1, CS2, CS3,. The switch groups SWA41 to SWA4m to be controlled are included.
[0041]
Here, the changeover switch groups SWA11 to SWA1m, SWA21 to SWA2m, SWA31 to SWA3m, SWA41 to SWA4m, and SWB1 to SWBm have the same configuration as that of the above-described embodiment (see FIG. 4), and the oscillation circuit is not illustrated. Based on the timing of the pulse signal Pa output from 20, the capacitor stacks CS1, CS2, CS3,..., CSn are connected in series, or the capacitor stacks CS1, CS2, CS3,. Each capacitor constituting CSn is controlled to be switched to a parallel connection state.
[0042]
In the connection state switching circuit 40 and the charging capacitor 50 having such a configuration, in the charging operation, the switching switches SWB1 to SWBm are turned on and the switching switches SWA11 to SWA1m at the timing when the pulse signal Pa becomes high level. , SWA21 to SWA2m, SWA31 to SWA3m, and SWA41 to SWA4m are controlled to be switched off.
[0043]
By such switching control of the switch SWA11 to SWA1m, SWA21 to SWA2m, SWA31 to SWA3m, SWA41 to SWA4m, SWB1 to SWBm, the charging capacitor 50 is connected between the high potential side power supply line HL and the low potential side power supply line LL. In addition, the capacitors C11, C21, C31, C12, C22,..., C2n, C3n are connected in series, and the charging capacitor IA is supplied by the charging current IA supplied from the intermittent charging circuit 30 to the high potential side power supply line HL. 50 charging is performed.
[0044]
On the other hand, in the voltage monitoring operation, at the timing when the pulse signal Pa becomes low level, the changeover switches SWB1 to SWBm are turned off, and the changeover switches SWA11 to SWA1m, SWA21 to SWA2m, SWA31 to SWA3m, and SWA41 to SWA4m are turned on. Control switching to the state.
[0045]
By such switching control, the charging capacitor 50 has capacitors C11 to C1n of the same hierarchy connected in parallel between the high potential side power supply line HL and the signal line L1 connecting the contacts N21 to N2n, and the signal line L1. Capacitors C21 to C2n on the same level are connected in parallel between the signal lines L2 that connect the contacts N31 to N3n, and further, on the same level between the signal lines L2 and the signal lines L3 that connect the contacts N41 to N4n. The capacitors C31 to C3n are connected in parallel. In the capacitor groups C11 to C1n, C21 to C2n, and C31 to C3n connected in parallel, the charging voltage of each capacitor is equalized, and each capacitor group is connected to an individual voltage monitor circuit 61, 62, 63, Charging voltages charged (equalized) in the capacitor groups C11 to C1n, C21 to C2n, and C31 to C3n are detected and monitored.
[0046]
Then, as shown in the above-described embodiment (see FIG. 5), by repeatedly executing the charging operation and the voltage monitoring operation, the charging voltage is periodically detected during the charging period, and the reference voltage (withstand voltage guarantee voltage) is detected. ), The charging state is monitored, and the charging operation to the charging capacitor 50 can be controlled by the control signal Sc input to the AND gate 33 of the intermittent charging circuit 30, thereby realizing stable rapid charging operation characteristics. can do.
Therefore, according to the charging capacitor 50 using such a capacitor stack, in addition to the function and effect in the above-described embodiment, the connection state of the integrated electric double layer capacitor having a stack structure can be easily switched and controlled. In addition, since the capacity during charging can be extremely reduced, the charging time can be shortened and the charging characteristics can be further improved while reducing the size of the charging device.
[0047]
In each of the embodiments described above, an example of a configuration in which a plurality of individual capacitors constituting the charging capacitor 50 or a plurality of capacitor stacks in which a plurality of capacitors are stacked is switched to a serial connection or a parallel connection state is an example. However, the present invention is not limited to this. In short, the charging state and the voltage monitoring operation are repeated periodically (intermittently) by switching the connection state between capacitors or a group of capacitors. If it performs, it can be applied satisfactorily.
[0048]
【The invention's effect】
According to the first aspect of the present invention, the charging current is intermittently supplied to the charging capacitor by the intermittent charging circuit based on the pulse signal having an arbitrary signal width and an arbitrary period output from the oscillation circuit, and In synchronization with the pulse signal, the connection state switching circuit is controlled so as to perform charging operation by switching a plurality of capacitors constituting a capacitor-type storage battery or a plurality of capacitor stacks in a series state. Regardless of the voltage supply cycle, etc., it is possible to control the progress of charging the capacitor-type storage battery at an arbitrary timing, improve the design freedom of the charging device, and perform a quicker charging operation. it can.
[0049]
According to the second aspect of the present invention, the electric device connects a plurality of capacitors or a plurality of capacitor stacks in series at a timing when the output current is supplied from the intermittent charging circuit by the connection state switching circuit. Since the charging operation is performed, the capacity value of the capacitor-type storage battery can be greatly reduced compared to the case where the capacitor-type storage battery is configured with a single capacitor, and power consumption is reduced by reducing the charging current. Can be achieved.
In addition, at the timing when the output current from the intermittent charging circuit is cut off, it is controlled to perform the operation of equalizing the charging voltage by connecting a plurality of capacitors or a plurality of capacitor stacks in parallel. Thus, the capacitor voltage charged in the capacitor-type storage battery can be accurately detected without variation.
[0050]
According to the invention of claim 3, when a plurality of capacitors or a plurality of capacitor stacks are connected in parallel by the connection state switching circuit, the capacitor or a single connected in parallel to the capacitor stack Since the charging voltage can be detected and monitored by this voltage monitoring circuit, the scale of the charging device can be reduced, and the amount of heat generation and power consumption in the voltage monitoring circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic circuit diagram showing a first embodiment of a charging apparatus according to the present invention.
FIG. 2 is a schematic configuration diagram showing an example of an intermittent charging circuit applied to the charging device according to the present embodiment.
FIG. 3 is a schematic configuration diagram showing an example of a charging capacitor and a connection state switching circuit applied to the charging device according to the present embodiment.
FIG. 4 is a timing chart showing switching control of a charging capacitor connection state by a connection state switching circuit according to the present embodiment;
FIG. 5 is a schematic configuration diagram illustrating an example of a selector switch applied to the connection state switching circuit according to the embodiment.
FIG. 6 is a timing chart showing the relationship between the switching control of the charging operation / voltage monitoring operation and each voltage level in the charging apparatus according to the present embodiment, and the change in the charging voltage of the charging capacitor.
FIG. 7 is a schematic configuration diagram showing a second embodiment of the charging device according to the present invention.
FIG. 8 is a schematic configuration diagram showing an example of a charging device in the prior art.
[Explanation of symbols]
10 Power supply circuit
20 Oscillator circuit
30 Intermittent charging circuit
40 Connection state switching circuit
50 Charging capacitor
31 Switching FET
32 AND gate
34 Comparator
33 Amplifier
35 PWM oscillator
60 Voltage monitor circuit
Pa pulse signal
Sc control signal
HL High potential power line
LL Low potential power line

Claims (2)

A power supply circuit that generates and outputs a charging voltage composed of a predetermined DC voltage or pulsating current;
An oscillation circuit for generating an output signal having an arbitrary signal width and an arbitrary period;
An intermittent charging circuit that intermittently outputs an output current generated based on the charging voltage at a predetermined timing of the output signal;
A plurality of capacitors, or a capacitor type storage battery comprising a plurality of capacitor stacks configured by stacking a plurality of capacitors, and storing electrical energy corresponding to the output current;
In synchronization with a predetermined timing of the output signal, the plurality of capacitors, or a connection state switching circuit for switching and controlling the plurality of capacitor stacks in a series connection state,
Equipped with,
The connection state switching circuit connects the plurality of capacitors or the plurality of capacitor stacks in series from parallel to each other at the timing when the output current is output from the intermittent charging circuit, or , Storing electrical energy corresponding to the output current in each capacitor stack,
At the timing when the output current from the intermittent charging circuit is cut off, the plurality of capacitors or the plurality of capacitor stacks are connected in series to parallel to each capacitor or each capacitor stack. A charging device characterized by equalizing a charged charging voltage . The charging device, the plurality of capacitors each other by the connection state switching circuitry, or, when the plurality of capacitor stack mutually connected in parallel, the capacitor, or the charging voltage charged in the capacitor stack detection, the charging device according to claim 1, characterized in that it comprises a voltage monitoring circuit for monitoring.

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