CN214670577U

CN214670577U - Serial port extension circuit

Info

Publication number: CN214670577U
Application number: CN202120754201.6U
Authority: CN
Inventors: 李映秀
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-04-13
Filing date: 2021-04-13
Publication date: 2021-11-09
Anticipated expiration: 2031-04-13

Abstract

The utility model discloses a serial port expansion circuit, which comprises a controller and an expansion circuit, wherein the expansion circuit comprises an FPGA; the controller comprises N control signal output ends, the FPGA comprises a sending enabling control end, a receiving enabling control end, N signal selection ends and 2^NEach output channel, wherein N is more than or equal to 2 and is an integer; the sending enabling control end is connected with a serial port sending end of the controller, and the receiving enabling control end is connected with a serial port receiving end of the controller; the control signal output end is connected with the signal selection end, and the output channel is used for being connected with external equipment. The utility model discloses a through being connected controller and FPGA, can select the quantity of serial ports extension according to the demand of actual extension serial ports, occupy a small amount of singlechip IO mouth moreover, can expand out the cluster of more quantity enoughThe wire harness is simple in connection, avoids messy wire harnesses, and has the characteristics of saving circuit volume and reducing circuit cost. The utility model discloses can wide application in electronic circuit technical field.

Description

Serial port extension circuit

Technical Field

The utility model relates to an electronic circuit technical field especially relates to a serial ports extension circuit.

Background

When the controller/processor communicates with the external device, the controller/processor is usually implemented by adopting a serial port communication mode, when the number of devices to be controlled by the controller/processor is large, the number of the controller/processor is increased, or the serial port is expanded, and compared with the increase of the number of the controller/processor, the number of the controllers/processors used can be reduced by expanding the serial port, so that the production cost is obviously reduced.

In the prior art, the serial port is expanded by using the three-eight decoder, but the number of the required three-eight decoders is multiplied along with the increase of the number of the required serial ports, so that the circuit area is increased and the circuit cost is increased.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model aims to provide a: a serial port expansion circuit is provided.

The utility model adopts the technical proposal that:

a serial port expansion circuit comprises a controller and an expansion circuit, wherein the expansion circuit comprises an FPGA;

the controller comprises N control signal output ends, the FPGA comprises a sending enabling control end, a receiving enabling control end, N signal selection ends and 2^NEach output channel, wherein N is more than or equal to 2 and is an integer;

the sending enabling control end is connected with a serial port sending end of the controller, and the receiving enabling control end is connected with a serial port receiving end of the controller;

the control signal output end is connected with the signal selection end, and the output channel is used for being connected with external equipment.

Further, the output channel comprises a sending end and a receiving end;

the transmitting end is used for connecting with a receiving port of the external equipment, and the receiving end is used for connecting with the receiving port of the external equipment.

Further, the serial port expansion circuit also comprises an indicator light module, wherein the indicator light module comprises a sending indicator light and a receiving indicator light;

the sending indicator light is connected with the controller, and the receiving indicator light is connected with the controller.

Further, the controller comprises a single chip microcomputer of which the model is STM32F030K6T 6.

Further, the model of the FPGA is EP3C16F484I 7N.

The utility model has the advantages that: through being connected controller and FPGA, can select the quantity of serial ports extension according to the demand of actual extension serial ports, occupy a small amount of singlechip IO mouth moreover, can expand out more serial ports, the line connection is simple, avoided the pencil in disorder, has the characteristics of saving the circuit volume moreover, reduction circuit cost.

Drawings

Fig. 1 is a schematic circuit diagram of a serial port expansion circuit according to the related art;

fig. 2 is a schematic circuit diagram of a serial port extension circuit of the present invention.

Detailed Description

This section will describe in detail the embodiments of the present invention, preferred embodiments of the present invention are shown in the attached drawings, which are used to supplement the description of the text part of the specification with figures, so that one can intuitively and vividly understand each technical feature and the whole technical solution of the present invention, but they cannot be understood as the limitation of the protection scope of the present invention.

In the present invention, if there is a description of directions (up, down, left, right, front and back), it is only for convenience of description of the technical solution of the present invention, and it is not intended to indicate or imply that the technical features indicated must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

In the utility model, the meaning of a plurality of is one or more, the meaning of a plurality of is more than two, and the meaning of more than two is understood as not including the number; the terms "above", "below", "within" and the like are understood to include the instant numbers. In the description of the present invention, if there is any description of "first" and "second" only for the purpose of distinguishing technical features, it is not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the precedence of the indicated technical features.

In the present invention, unless otherwise explicitly defined, the terms "set", "install", "connect", and the like are to be understood in a broad sense, and for example, may be directly connected or may be indirectly connected through an intermediate medium; can be fixedly connected, can also be detachably connected and can also be integrally formed; may be mechanically coupled, may be electrically coupled or may be capable of communicating with each other; either as communication within the two elements or as an interactive relationship of the two elements. The technical skill in the art can reasonably determine the specific meaning of the above words in the present invention by combining the specific contents of the technical solution.

The invention will be further explained and explained with reference to the drawings and the embodiments in the following description.

In the related art, when the controller IC3 communicates with a plurality of external devices, a plurality of serial ports are required. However, referring to fig. 1, in order to solve the technical problem of limited serial number, in the related art, a serial expansion is usually performed by using three-eight decoders, three IO ports of a controller IC3 output control signals to three signal selection pins (control signal is A, B, C) of a first three-eight decoder IC1 and a second three-eight decoder IC2, a serial transmitting end of a single chip microcomputer controls an enabling end G1 of the first three-eight decoder IC1, a serial receiving end of the single chip microcomputer controls an enabling end G1 of the second three-eight decoder IC2, eight output ends Tx1-Tx8 of the first three-eight decoder IC1 are respectively connected to receiving ports of eight external devices, eight output ends Rx1-Rx8 of the second three-eight decoder IC2 are respectively connected to transmitting ports of the eight external devices, and the transmitting end and the serial receiving end of the controller IC3 are used in cooperation, the working states of the first third eight decoder IC1 and the second third eight decoder IC2 are controlled, so that data transmission and data reception between the controller IC3 and eight external devices are realized, and the function of enabling the controller IC3 and a plurality of external devices is realized.

It can be seen from the above description that two three-eight decoders (i.e. a set of three-eight decoders including the first three-eight decoder IC1 and the second three-eight decoder IC2) are used to expand one serial port of the controller IC3 into eight serial ports for communicating with eight external devices, when the controller IC3 needs to communicate with more external devices, for example, 256 external devices, 32(256/8, i.e. 32) sets of three-eight decoders need to form a serial port expansion circuit, the controller IC3 needs to provide 96(3 × 32, i.e. 96) IO ports to implement a serial port expansion function, and a serial port transmitting end and a serial port receiving end of the controller IC3 need to be connected to the 32 sets of three-eight decoders to control transmission enable and reception enable, which means that the serial port expansion circuit needs a large number of chips, a large circuit size, a large number of chips, and a large number of chips, The circuit cost is high, more IO ports need to be provided by the controller, the circuit connection is complex, and the wiring harness is messy.

To at least partially solve one of the above problems, referring to fig. 2, the present invention provides a serial port expansion circuit, which includes a controller and an expansion circuit, wherein the serial port expansion circuit includes an FPGA IC 5;

the controller IC4 comprises N control signal output ends, the FPGA comprises a sending enable control end, a receiving enable control end, N signal selection ends and 2^NEach output channel, wherein N is more than or equal to 2 and is an integer;

the sending enabling control end is connected with a serial port sending end of the controller IC4, and the receiving enabling control end is connected with a serial port receiving end of the controller IC 4;

Specifically, a Field-Programmable Gate Array (FPGA) appears as a semi-custom circuit in the Field of application-specific integrated circuits (ASICs), which not only solves the disadvantages of custom circuits, but also overcomes the drawback of limited Gate circuits of the original Programmable devices.

The control signal output end of the controller IC4 mainly refers to an IO port of the controller IC4, the signal selection end of the FPGA mainly refers to an IO port of the FPGA IC5, and N control signal output ends of the controller IC4 are connected with N signal selection ends of the FPGA IC5, so that the controller IC4 outputs channel selection signals to the FPGA IC5, and the control selection 2 is controlled^NThe specific output channel of the output channels has a principle similar to that of a three-eight decoder, wherein the ith output channel of the FPGA IC5 comprises a sending end Txi and a receiving end Rxi, wherein i is an integer and is not less than 1 and not more than N, and 2^NAn output channel and 2^NStation external device connection (connection of the transmission channel Txi and the reception port of the i-th station external device, connection of the reception channel Rxi and the transmission port of the i-th station external device). In addition, both the receiving enabling control end and the receiving enabling control end of the FPGAIC5 can be realized by using an IO port of the FPGA IC5, a serial port transmitting end of the controller IC4 is connected with a transmitting enabling control end of the FPGA IC5, and a serial port receiving end of the controller IC4 is connected with a receiving enabling control end of the FPGA IC5, so that the controller IC4 can control an output channel of the FPGA IC5 to be in a transmitting or receiving state, that is, control a transmitting end Txi or a receiving end Rxi of an ith output channel to be in a working state.

In a specific embodiment, the controller IC4 adopts a single chip microcomputer with a model number of STM32F030K6T6, the FPGA IC5 adopts an FPGA with a model number of EP3C16F484I7N, and the single chip microcomputer with the model number of STM32F030K6T6 and the FPGA with the model number of EP3C16F484I7N are used to expand one serial port into 256 serial ports, which specifically includes the following steps:

eight IO ports of an STM32F030K6T6 singlechip are selected as control signal output ends (eight IO ports including PA0 and PA8-PA14 are selected in FIG. 2), eight control signals A-H are output to eight signal selection ends (eight IO ports including pins 1-8) of an EP3C16F484I7N FPGA, a serial port transmitting end (PB6 pin) of the STM32F030K6T6 singlechip is connected to a pin 9 of the EP3C16F484I7N FPGA, and a serial port receiving end (PB7 pin) of the STM32F030K6T6 singlechip is connected to a pin 10 of the EP3C16F484I7N FPGA.

The output channel of the EP3C16F484I7N FPGA is selected by eight control signals A-H, a serial port sending end of the single chip microcomputer sends a high level signal, a serial port receiving end of the single chip microcomputer sends a low level signal to the FPGA so as to control the sending end in the output channel of the FPGA to be in a working state, and therefore the purpose that the controller IC4 sends data to external equipment is achieved.

It can be seen by this application embodiment, this application is connected controller IC4 and FPGA IC5, can select the quantity of serial ports extension according to the demand of actual extension serial ports, occupies a small amount of singlechip IO mouth moreover, can expand out more quantity's serial ports, and the line connection is simple, avoided the pencil in disorder, has the characteristics of saving the circuit volume, reducing circuit cost moreover.

As a further optional implementation, the serial port expansion circuit further includes an indicator light module, and the indicator light module includes a sending indicator light and a receiving indicator light;

the transmission indicator lamp is connected to the controller IC4, and the reception indicator lamp is connected to the controller IC 4.

Specifically, the indicator light module is used to indicate that the controller IC4 is in a state of transmitting data or a state of receiving data. When the controller IC4 transmits data to the external device, the sending indicator lamp is turned on, and the operator can know that the controller IC4 is sending a control signal to the external device to control the operation of the external device, and when the controller IC4 receives data from the external device, the receiving indicator lamp is turned on, and the operator can know that the controller IC4 is receiving data uploaded from the external device. When the sending indicator light or the receiving indicator light is always in a non-lighted state, the worker may perform the fault detection in time in consideration of whether the communication of the external device with the controller IC4 is blocked.

Finally, it should be noted that the serial port expansion circuit of the present application can be applied not only to serial port expansion, but also to expansion of digital interfaces and analog interfaces according to actual requirements.

While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are intended to be included within the scope of the present invention as defined by the appended claims.

Claims

1. A serial port expansion circuit is characterized by comprising a controller and an expansion circuit, wherein the expansion circuit comprises an FPGA;

the controller comprises N control signalsAn output terminal, the FPGA comprises a sending enable control terminal, a receiving enable control terminal, N signal selection terminals and 2^NEach output channel, wherein N is more than or equal to 2 and is an integer;

2. The serial port expansion circuit according to claim 1, wherein the output channel comprises a transmitting end and a receiving end;

the transmitting end is used for connecting with a receiving port of the external equipment, and the receiving end is connected with the receiving port of the external equipment.

3. The serial port expansion circuit according to claim 1, further comprising an indicator light module, wherein the indicator light module comprises a sending indicator light and a receiving indicator light;

4. The serial port expansion circuit according to claim 1, wherein the controller comprises a single chip microcomputer of the type STM32F030K6T 6.

5. The serial port expansion circuit of claim 1, wherein the model number of the FPGA is EP3C16F484I 7N.