CN214583711U - A Numerically Controlled Variable Resistor Optimization Circuit - Google Patents
A Numerically Controlled Variable Resistor Optimization Circuit Download PDFInfo
- Publication number
- CN214583711U CN214583711U CN202120354371.5U CN202120354371U CN214583711U CN 214583711 U CN214583711 U CN 214583711U CN 202120354371 U CN202120354371 U CN 202120354371U CN 214583711 U CN214583711 U CN 214583711U
- Authority
- CN
- China
- Prior art keywords
- mos transistor
- pole
- resistor
- mos
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005457 optimization Methods 0.000 title claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 24
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052744 lithium Inorganic materials 0.000 claims description 4
- 239000003381 stabilizer Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Direct Current Feeding And Distribution (AREA)
Abstract
本实用新型公开了一种数控可变电阻优化电路，包括NTC模拟口P1、稳压器LDO1、MOS管Q9、MOS管Q10、MOS管Q11、MOS管Q12、MOS管Q13、MOS管Q14、MOS管Q15、MOS管Q16、MOS管Q17、MOS管Q18、MOS管Q19、MOS管Q20、MOS管Q21、MOS管Q22、MOS管Q23、MOS管Q24、单片机MCU，本实用新型大大简化了电路，使用器件变少，更利于使用成本低的单片机，成本低，体积小。
The utility model discloses a numerical control variable resistance optimization circuit, which comprises an NTC analog port P1, a voltage regulator LDO1, a MOS tube Q9, a MOS tube Q10, a MOS tube Q11, a MOS tube Q12, a MOS tube Q13, a MOS tube Q14, and a MOS tube Tube Q15, MOS tube Q16, MOS tube Q17, MOS tube Q18, MOS tube Q19, MOS tube Q20, MOS tube Q21, MOS tube Q22, MOS tube Q23, MOS tube Q24, MCU, the utility model greatly simplifies the circuit, Fewer devices are used, which is more conducive to the use of low-cost single-chip microcomputers, which are low in cost and small in size.
Description
Technical Field
The utility model relates to a numerical control variable resistance optimization circuit.
Background
With the progress and development of society, the intellectualization in the aspects of storage, family, trip and the like, the diversification of mobile consumer electronic products, and the adoption of batteries as clean energy providers, the batteries are more and more popular and favored by consumers and become an indispensable part of electronic products. In the application process, the battery is taken as an output end of energy, whether the performance of the battery core meets the use condition or not is considered through test items such as charging, discharging, high-temperature group storage, low-temperature group storage testing and the like under certain conditions, the safety and the operation coefficient in the application are improved, the battery is helped to reduce the failure rate in the use process in the long-term use process, more secure service is provided for a user in the use process, the user acceptance is improved, and the method becomes a significant research subject. When testing a BMS protection board or other systems with NTC, NTC temperature sampling needs to be verified, and the existing method is shown in fig. 1, and it is seen from fig. 1 that 40-way switches and MOS transistors have high cost and a single chip with more io ports needs to be used.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming not enough in the current product, providing a numerical control variable resistance optimization circuit.
In order to achieve the purpose, the utility model is realized by the following technical scheme:
a numerical control variable resistance optimization circuit comprises an NTC analog port P1, a voltage regulator LDO1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a resistor R4, a MOS tube Q4, a power supply pin of the LDO 3 is connected with a GND signal of the single-chip microcomputer of the voltage regulator LDO 4, the other end of the single chip LDO 4 is connected with a GND signal of the single chip microcomputer 4, the power supply pin of the single chip microcomputer 4 is connected with the single chip microcomputer C4, the single chip microcomputer 4, the single chip is connected with the GND 3, the single chip microcomputer 4, the single chip microcomputer 4, the single chip is connected with the single chip microcomputer 4, the single chip is connected with the single chip microcomputer 4, the single chip microcomputer 4, the single chip is connected with the single chip microcomputer 4, the single chip microcomputer is connected with the single chip microcomputer 4, the single chip microcomputer is connected with the single chip microcomputer, the other end of the resistor R is connected with a ground signal GND through a capacitor C, the capacitor C is connected with the capacitor C in parallel, the D pole of the MOS tube Q is connected with the ground signal GND, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through the resistor R, the G pole of the MOS tube Q, the MCU are connected, the S pole of the MOS tube Q is connected with the D pole of the MOS tube Q through the resistor R, the S pole of the MOS tube Q is connected with the S pole of the MOS tube Q, the S pole of the MOS tube Q is connected with the single chip microcomputer through the resistor R, the S pole of the MOS tube Q is connected with the D pole of the MOS tube Q, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the S pole of the MOS tube Q is connected with the D pole of the MOS tube Q, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the S pole of the MOS tube Q is connected with the D pole of the MOS tube Q through a resistor R, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the S pole of the MOS transistor Q16 is connected to the D pole of a MOS transistor Q20, the D pole of the MOS transistor Q20 is connected to the S pole of the MOS transistor Q37 through a resistor R37, the S pole of the MOS transistor Q37 is connected to the D pole of the MOS transistor Q37, the D pole of the MOS transistor Q37 is connected to the S pole of the MOS transistor Q37 through a resistor R37, the S pole of the MOS transistor Q37 is connected to the S pole of the MOS transistor Q37 through a resistor R37, the D pole of the MOS transistor Q37 is connected to the S pole of the MOS transistor Q37 through a resistor R37, the S pole of the MOS transistor Q37 is connected to the D pole of the MOS transistor Q37, the S pole of the MOS transistor Q37 is connected to the D pole of the NTC 37, the MOS transistor Q37 is connected to the n pole of the MOS transistor Q37, the n pole of the MOS transistor Q37 is connected to the n, the MOS transistor Q37, the n pole of the MOS transistor Q37 is connected to the n pole of the MOS transistor Q37, the n is connected to the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37 is connected to the negative pole of the MOS transistor Q37, and the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37 is connected to the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37 is connected to the negative pole of the MOS transistor Q37, and the negative pole of the MOS transistor Q37, the MOS transistor Q37 is connected to the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q37, the MOS transistor Q37 is connected to the MOS transistor Q37, the negative pole of the MOS transistor Q37, the negative pole of the MOS transistor Q36, the positive input end IN + of the NTC analog port P1 is connected with a ground signal GND.
Preferably, the power source VCC is powered by two lithium batteries or a switching power supply.
Preferably, the power source VCC is 5V.
Preferably, MOS transistor Q9, MOS transistor Q10, MOS transistor Q11, MOS transistor Q12, MOS transistor Q13, MOS transistor Q14, MOS transistor Q15, MOS transistor Q16, MOS transistor Q17, MOS transistor Q18, MOS transistor Q19, MOS transistor Q20, MOS transistor Q21, MOS transistor Q22, MOS transistor Q23, and MOS transistor Q24 are all N-channel MOS transistors.
Preferably, the resistor R26 is 10K, the resistor R27 is 1K, the resistor R28 is 0.01K, the resistor R29 is 0.1K, the resistor R30 is 20K, the resistor R31 is 2K, the resistor R32 is 0.02K, the resistor R33 is 0.2K, the resistor R34 is 20K, the resistor R35 is 2K, the resistor R36 is 0.02K, the resistor R37 is 0.2K, the resistor R38 is 50K, the resistor R39 is 5K, the resistor R40 is 0.05K, and the resistor R41 is 0.5K.
The utility model has the advantages as follows: the utility model discloses do not need the numerical control NTC analog resistance system of booster pump, the utility model discloses simplify the circuit greatly, use the device to become few, more do benefit to the singlechip that use cost is low, with low costs, it is small.
Drawings
FIG. 1 is a schematic circuit diagram of the background art;
fig. 2 is a schematic circuit diagram of the present invention.
Detailed Description
The technical scheme of the utility model is further explained by combining the attached drawings of the specification:
as shown in FIG. 2, a digital controlled variable resistance optimization circuit comprises an NTC analog port P1, a voltage regulator LDO1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a MOS transistor Q28, a power supply pin of the LDO 3, a single-chip microcomputer C3, a ground, a single-side of the voltage regulator, a single-chip microprocessor, a power supply pin of the single chip LDO 3, a GND, a single chip microcomputer C, a GND, a single chip microcomputer C, a power supply pin of the single chip, a single chip microcomputer, a 2 pin of the regulator LDO1 is connected to one end of a resistor R1, the other end of the resistor R1 is connected to a ground signal GND through a capacitor C1, the capacitor C1 is connected in parallel with the capacitor C1, a D pole of the MOS transistor Q1 is connected to the ground signal GND, a D pole of the MOS transistor Q1 is connected to an S pole of the MOS transistor Q1 through the resistor R1, a G pole of the MOS transistor Q1, a MOS transistor Q pole of the MOS transistor Q1, a resistance Q1, a D pole of the MOS transistor Q1, a resistance Q1, a MOS transistor Q pole of the MOS transistor Q1, a resistance Q pole of the MOS transistor Q1, a resistance Q pole of the MOS transistor Q1, a resistance Q1, a MOS transistor Q pole of the MOS transistor Q1, a resistance Q pole of the MOS transistor Q1, a resistance Q1, a resistance Q pole of the MOS transistor Q1, a resistance, a, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the S pole of the MOS tube Q is connected with the D pole of the MOS tube Q through a resistor R, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the S pole of the MOS tube Q is connected with the D pole of the MOS tube Q, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the D pole of the MOS tube Q is connected with the D pole of the MOS tube Q through a resistor R, the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, and the D pole of the MOS tube Q is connected with the S pole of the MOS tube Q through a resistor R, the D pole of MOS pipe Q passes through resistance R and connects the S pole of MOS pipe Q, the S pole of MOS pipe Q is connected to the S pole of MOS pipe Q, the D pole of MOS pipe Q passes through resistance R and connects the S pole of MOS pipe Q, the D pole of MOS pipe Q is connected to the S pole of MOS pipe Q, the S pole of MOS pipe Q is connected through resistance R to the D pole of MOS pipe Q, the D pole of MOS pipe Q is connected to the S pole of MOS pipe Q, the D pole of MOS pipe Q is connected through resistance R to the D pole of MOS pipe Q, the S pole of MOS pipe Q is connected through resistance R to the S pole of MOS pipe Q, the S pole of MOS pipe Q is connected to the S pole of MOS pipe Q, the D pole of MOS pipe Q is connected through resistance R to the S pole of MOS pipe Q, the S pole of MOS pipe Q is connected to the negative pole of MOS pipe Q, the positive input end IN + of the NTC analog port P1 is connected with a ground signal GND.
As shown in fig. 2, a power supply VCC is powered by two lithium batteries or a switching power supply, the power supply VCC is 5V, the MOS transistor Q9, the MOS transistor Q10, the MOS transistor Q11, the MOS transistor Q12, and the MOS transistor Q12 are all N-channel MOS transistors, the resistor R12 is 10K, the resistor R12 is 1K, the resistor R12 is 0.01K, the resistor R12 is 0.1K, the resistor R12 is 20K, the resistor R12 is 2K, the resistor R12 is 0.02K, the resistor R12 is 0.2K, the resistor R12 is 20K, the resistor R12 is 2K, the resistor R12 is 0.02K, the resistor R12 is 365K, and the resistor R12 is 0.05K. The G pole of MOS transistor Q9 is labeled GPIO _1, the G pole of MOS transistor Q10 is labeled GPIO _5, the G pole of MOS transistor Q11 is labeled GPIO _13, the G pole of MOS transistor Q12 is labeled GPIO _9, the G pole of MOS transistor Q13 is labeled GPIO _2, the G pole of MOS transistor Q14 is labeled GPIO _6, the G pole of MOS transistor Q15 is labeled GPIO _14, the G pole of MOS transistor Q16 is labeled GPIO _10, the G pole of MOS transistor Q17 is labeled GPIO _3, the G pole of MOS transistor Q18 is labeled GPIO _7, the G pole of MOS transistor Q19 is labeled GPIO _15, the G pole of MOS transistor Q20 is labeled GPIO _11, the G pole of MOS transistor Q21 is labeled GPIO _4, the G pole of MOS transistor Q22 is labeled GPIO _8, the G pole of MOS transistor Q13 is labeled GPIO _16, and the G pole of MOS transistor Q8516 is labeled GPIO _ 6.
The power supply part is powered by two lithium batteries or a switching power supply (workshop protection board test tool), and is subjected to voltage reduction by a voltage stabilizer LDO1 to form 3.3V and then is used for supplying power to the single chip microcomputer system, the NTC analog circuit is connected in series by 4 paths of selectable resistors, each path is connected in series by 4 resistors, and the single chip microcomputer controls GPIO _ 1-GPIO _16 to generate different resistance values.
The main characteristic of the power supply part is that the positive input end IN + of the NTC analog port P1 is used as the ground IN the power supply ground, and whether the input of the NTC analog port P1 is pulse or continuous, the power supply VCC of the singlechip is ensured to be higher than that of the positive input end of the NTC analog port P1
The main characteristic of the resistance analog part circuit is that the MOS tube determines which resistance is connected in series, thereby realizing the series connection of the variable resistance, and the booster pump is not needed to drive the N tube, because the potential of the GPIO _ port of the singlechip is always higher than the S level.
Assuming that 30k resistors are simulated, as long as the single chip microcomputer drives GPIO _1 and all io ports GPIO _3.4.5.6.7.8.9.10.11.12.13.14.15.16 except GPIO _2 are IN high level, after entering the NTC input end, only R26/R30 is not short-circuited and returns to the negative input end IN-of the NTC simulation port P1, a simulated 10k series 20k resistor is formed, and therefore different temperature values are simulated.
The utility model discloses different resistances are simulated to the accessible singlechip to realize the automatic analog temperature of protection shield test.
The utility model discloses do not need the numerical control NTC analog resistance system of booster pump, the utility model discloses simplify the circuit greatly, use the device to become few, more do benefit to the singlechip that use cost is low, with low costs, it is small.
It should be noted that the above list is only one specific embodiment of the present invention. Obviously, the present invention is not limited to the above embodiments, and many modifications can be made, and in short, all modifications that can be directly derived or suggested by the person skilled in the art from the disclosure of the present invention should be considered as the protection scope of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120354371.5U CN214583711U (en) | 2021-02-08 | 2021-02-08 | A Numerically Controlled Variable Resistor Optimization Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120354371.5U CN214583711U (en) | 2021-02-08 | 2021-02-08 | A Numerically Controlled Variable Resistor Optimization Circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214583711U true CN214583711U (en) | 2021-11-02 |
Family
ID=78316185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120354371.5U Expired - Fee Related CN214583711U (en) | 2021-02-08 | 2021-02-08 | A Numerically Controlled Variable Resistor Optimization Circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214583711U (en) |
-
2021
- 2021-02-08 CN CN202120354371.5U patent/CN214583711U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109659905B (en) | An IPM overcurrent and overtemperature protection circuit | |
| CN104569846B (en) | A kind of single battery test system | |
| CN110832332A (en) | Voltage measuring device and method | |
| CN109245237B (en) | Intelligent adaptation power supply and adaptation method thereof | |
| CN214583711U (en) | A Numerically Controlled Variable Resistor Optimization Circuit | |
| CN110032107A (en) | The flogic system and control method of 4 road signal on-off are controlled by 3 relays | |
| CN109991492A (en) | Simulated battery circuit | |
| US10395743B2 (en) | Method and system for implementing one-wire programmable circuit | |
| CN208043276U (en) | Temperature-detecting device and charging gun, charging socket equipped with the temperature-detecting device | |
| WO2021063290A1 (en) | Battery and automotive diagnostic tablet | |
| Wu et al. | Design of battery management system for electric vehicles | |
| CN107305526A (en) | A kind of debugger for microcontroller | |
| CN110601296A (en) | Active equalization circuit of battery management system | |
| CN102122834B (en) | Power battery management chip supporting multi-series connection | |
| CN204089176U (en) | Battery pack protection plate circuit, battery pack protection plate, battery component | |
| CN203658883U (en) | Temperature and humidity monitoring system for power battery pack of electric vehicle | |
| US8266348B2 (en) | System and method of communicating with portable devices | |
| CN213874737U (en) | Numerical control variable resistance circuit | |
| CN108733100A (en) | A kind of SCM Based water temperature control system and method | |
| CN110737257A (en) | CAN-based programmable automobile temperature sensor resistance signal output device | |
| CN206525996U (en) | The integral control circuit and dust catcher of a kind of dust catcher | |
| CN207677471U (en) | The passive balanced safety circuit of electric vehicle | |
| CN204214969U (en) | A kind of li-ion cell protection device checkout equipment | |
| CN215300612U (en) | Multichannel isolation simulation changes pwm simulation sampling circuit | |
| CN220693354U (en) | Drive circuit of hand warmer and hand warmer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20211102 |