CN214542246U

CN214542246U - Novel high-voltage VDMOS device

Info

Publication number: CN214542246U
Application number: CN202120636868.6U
Authority: CN
Inventors: 陈利
Original assignee: Xiamen Xinyidai Integrated Circuit Co ltd
Current assignee: Xiamen Xinyidai Integrated Circuit Co ltd
Priority date: 2021-03-29
Filing date: 2021-03-29
Publication date: 2021-10-29
Anticipated expiration: 2031-03-29

Abstract

The utility model discloses a novel high pressure VDMOS device, it includes: the transistor comprises an N-type heavily doped substrate, an N-type lightly doped buffer region, a P-type well region, an N-type heavily doped source region, a P-type heavily doped source region, a high-K insulating layer, a gate polysilicon region, a gate electrode, a source electrode and a drain electrode; the drain electrode is formed on the lower surface of the N-type heavily doped substrate, an N-type lightly doped buffer region is arranged on the upper surface of the N-type heavily doped substrate, two P-type well regions are arranged on the upper surface of the N-type lightly doped buffer region, two N-type heavily doped source regions and one P-type heavily doped source region are arranged on the upper surface of each P-type well region, high-K insulating layers are arranged on the upper surfaces of the two P-type well regions and the N-type lightly doped buffer region, a grid polycrystalline silicon region is arranged on the upper surface of each high-K insulating layer, a grid electrode is arranged on the upper surface of each grid polycrystalline silicon region, and source electrodes are arranged on the upper surfaces of the two N-type heavily doped source regions and the P-type heavily doped source region.

Description

Novel high-voltage VDMOS device

Technical Field

The utility model relates to a semiconductor power technical field, concretely relates to novel high-pressure VDMOS device.

Background

The VDMOS device is an electronic switch, the switching state of which is controlled by the gate voltage, and the conduction is performed by electrons or holes when the VDMOS device is turned on, and the VDMOS device has the advantages of simple control and fast switching, and thus is widely applied to power electronic systems, mainly including a switching power supply, a motor drive, and the like. The threshold voltage and the specific on-resistance are two main parameters of the power VDMOS, wherein the specific on-resistance of the power VDMOS also increases sharply with the increase of the threshold voltage of the power device, and the specific on-resistance is more obvious for the high-voltage VDMOS device.

The silicon carbide material has excellent electrical properties, such as larger forbidden band width, higher thermal conductivity, higher electron saturation drift velocity and higher critical breakdown electric field, so that the silicon carbide material becomes an ideal semiconductor material in high-temperature, high-frequency, high-power and anti-radiation application occasions. Silicon carbide semiconductor materials are widely used in the power field for the preparation of high-power electronic devices. Currently, silicon carbide electronic devices are subject to interference from the surrounding environment, which causes the electronic devices to be damaged to varying degrees, affecting their electrical performance, and even causing the devices to fail permanently, such as: the effect of the radiated signal.

Therefore, a new high-voltage VDMOS device is needed to reduce the influence of radiation signals on the device.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: the novel high-voltage VDMOS device is prepared by utilizing the characteristics of high temperature resistance, high critical electric field, high thermal conductivity and the like of SiC, the influence of radiation signals on the threshold voltage and the specific on-resistance of the device can be effectively reduced by adopting the VDMOS with an N-type channel, and the switching speed can be improved under the high-frequency condition.

In order to solve the technical problem, the technical scheme of the utility model is specifically as follows:

a novel high voltage VDMOS device comprising: the semiconductor device comprises an N-type heavily doped substrate, an N-type lightly doped buffer region, a P-type well region, an N-type heavily doped source region, a P-type heavily doped source region, a high-K insulating layer, a grid polysilicon region, a grid electrode, a source electrode and a drain electrode.

Further, the drain electrode is formed on the lower surface of the N-type heavily doped substrate, the N-type lightly doped buffer region is arranged on the upper surface of the N-type heavily doped substrate, two P-type well regions are arranged on the upper surface of the N-type lightly doped buffer region, a gap is formed between the two P-type well regions, the two P-type well regions are symmetrical about a central line of the device, two N-type heavily doped source regions and one P-type heavily doped source region are arranged on the upper surface of each P-type well region, the P-type heavily doped source region is arranged between the two N-type heavily doped source regions, the N-type heavily doped source regions and the P-type heavily doped source regions are connected with each other, and gaps are formed between the side edges of the N-type heavily doped source regions and the side edges of the P-type well regions.

Furthermore, a high-K insulating layer is arranged on the upper surfaces of the two P-type well regions and the N-type lightly doped buffer region, two side edges of the high-K insulating layer are arranged on the two N-type heavily doped source regions close to the central line of the device, the upper surface of the high-K insulating layer is provided with the gate polysilicon region, the upper surface of the gate polysilicon region is provided with a gate electrode, and the upper surfaces of the two N-type heavily doped source regions and one P-type heavily doped source region are provided with the source electrode.

Further, the thickness of the N-type lightly doped buffer region is greater than that of the N-type heavily doped substrate.

Further, the thickness of the N-type lightly doped buffer region is greater than that of the P-type well region.

Further, the high-K insulating layer is a high-K insulating material of a single substance or a compound.

Further, the source electrode, the gate electrode, and the drain electrode are made of a copper material or an aluminum material.

Further, the semiconductor substrate material is a semiconductor SiC-based material.

Advantageous effects

The utility model discloses a novel high pressure VDMOS device utilizes characteristics such as high temperature resistant, high critical electric field and the high thermal conductivity of SiC, carries out the preparation of VDMOS device to it, adopts the VDMOS of N type channel, can realize effectively reducing the influence of radiation signal to the threshold voltage of device and than on-resistance, can also improve switching speed under the high frequency condition.

Drawings

Fig. 1 is a schematic structural diagram of the novel high-voltage VDMOS device of the present invention.

Reference numerals: 1. an N-type heavily doped substrate; 2. an N-type lightly doped buffer region; 3. a P-type well region; 4. an N-type heavily doped source region; 5. a P-type heavily doped source region; 6. a high-K insulating layer; 7. a gate polysilicon region; s, a source electrode; D. a drain electrode; G. a gate electrode.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a novel high-voltage VDMOS device according to the present invention.

The utility model provides a pair of novel high pressure VDMOS device, include: the transistor comprises an N-type heavily doped substrate 1, an N-type lightly doped buffer region 2, a P-type well region 3, an N-type heavily doped source region 4, a P-type heavily doped source region 5, a high-K insulating layer 6, a gate polysilicon region 7, a gate electrode G, a source electrode S and a drain electrode D;

the drain electrode D is formed on the lower surface of the N-type heavily doped substrate 1, the N-type lightly doped buffer region 2 is arranged on the upper surface of the N-type heavily doped substrate 1, two P-type well regions 3 are arranged on the upper surface of the N-type lightly doped buffer region 2, a gap is formed between the two P-type well regions 3, the two P-type well regions 3 are symmetrical about the central line of the device, two N-type heavily doped source regions 4 and one P-type heavily doped source region 5 are arranged on the upper surface of each P-type well region 3, the P-type heavily doped source region 5 is arranged between the two N-type heavily doped source regions 4, the N-type heavily doped source regions 4 and the P-type heavily doped source regions 5 are connected with each other, and a gap is formed between the side edge of the N-type heavily doped source region 4 and the side edge of the P-type well region 3;

two the upper surface of P type trap district 3 with N type lightly doped buffer 2 is equipped with high K insulating layer 6, two sides of high K insulating layer 6 are established and are close to two of device central line on the heavily doped source region 4 of N type, the upper surface of high K insulating layer 6 is equipped with grid polysilicon region 7, the upper surface of grid polysilicon region 7 is equipped with gate electrode G, two heavily doped source region 4 of N type and one the upper surface of P type heavily doped source region 5 is equipped with source electrode S.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A novel high-voltage VDMOS device is characterized by comprising: the transistor comprises an N-type heavily doped substrate (1), an N-type lightly doped buffer region (2), a P-type well region (3), an N-type heavily doped source region (4), a P-type heavily doped source region (5), a high-K insulating layer (6), a gate polysilicon region (7), a gate electrode (G), a source electrode (S) and a drain electrode (D);

wherein the drain electrode (D) is formed on the lower surface of the N-type heavily doped substrate (1), the upper surface of the N-type heavily doped substrate (1) is provided with the N-type lightly doped buffer region (2), two P-type well regions (3) are arranged on the upper surface of the N-type lightly doped buffer region (2), a space is arranged between the two P-type well regions (3), the two P-type well regions (3) are symmetrical with the central line of the device, two N-type heavily doped source regions (4) and a P-type heavily doped source region (5) are arranged on the upper surface of each P-type well region (3), the P-type heavily doped source region (5) is arranged between the two N-type heavily doped source regions (4), and the N-type heavily doped source region (4) and the P-type heavily doped source region (5) are connected to each other, a space is arranged between the side edge of the N-type heavily doped source region (4) and the side edge of the P-type well region (3);

two the upper surface of P type well region (3) with N type lightly doped buffer region (2) is equipped with high K insulating layer (6), establish two sides of high K insulating layer (6) be close to the device central line two on N type heavily doped source region (4), the upper surface of high K insulating layer (6) is equipped with grid polysilicon region (7), the upper surface of grid polysilicon region (7) is equipped with gate electrode (G), two N type heavily doped source region (4) and one the upper surface of P type heavily doped source region (5) is equipped with source electrode (S).

2. A new type of high voltage VDMOS device according to claim 1, characterized in that the thickness of the N-type lightly doped buffer (2) is larger than the thickness of the N-type heavily doped substrate (1).

3. A new type of high voltage VDMOS device according to claim 1, characterized by the fact that the thickness of the N-type lightly doped buffer (2) is greater than the thickness of the P-type well (3).

4. A new type of high voltage VDMOS device according to claim 1, characterized by the fact that the high-K dielectric layer (6) is a simple or compound high-K dielectric material.

5. The new high-voltage VDMOS device according to claim 1, wherein the material of the source electrode (S), the gate electrode (G) and the drain electrode (D) is copper material or aluminum material.

6. The novel high-voltage VDMOS device as recited in claim 1, wherein the semiconductor substrate material is a semiconductor SiC-based material.