CN214378472U - Single crystalline silicon solar cell for increasing output voltage - Google Patents
Single crystalline silicon solar cell for increasing output voltage Download PDFInfo
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- CN214378472U CN214378472U CN202120577450.2U CN202120577450U CN214378472U CN 214378472 U CN214378472 U CN 214378472U CN 202120577450 U CN202120577450 U CN 202120577450U CN 214378472 U CN214378472 U CN 214378472U
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Abstract
The utility model relates to a single crystalline silicon solar cell for increasing output voltage, which is provided with a crystalline silicon wafer; the crystal silicon wafer is divided into a plurality of small battery units which are mutually electrically insulated by the front side electric insulation region; the front surface of each small cell is provided with a confluence layer for collecting electrons and a main grid electrode area for receiving the electrons collected by the confluence layer; back electrode regions are arranged on the back of each small cell, and back electric insulation regions are arranged between adjacent back electrode regions; the main grid electrode area is provided with at least one through hole which penetrates through the crystal silicon wafer; one end of the through hole, which is positioned on the back surface of the crystal silicon wafer, is positioned in the back electrode area of the other small cell; the through hole is filled with solidified conductive slurry; the last small battery unit is connected with the next small battery unit in series through the conductive slurry solidified in the through hole; the small battery unit connected with the next small battery unit in series is not required to be provided with a through hole. The utility model discloses can reach the purpose that increases single battery output voltage and reduce single battery output current.
Description
Technical Field
The utility model relates to a photovoltaic module, in particular to a single crystalline silicon solar cell for increasing output voltage.
Background
The output voltage of the crystalline silicon solar cell is limited by the indirect band gap structure of the crystalline silicon material, the maximum power point output voltage (Vmpp) generally fluctuates within the range of 0.5-0.7V, while Impp is much larger than Vmpp and generally fluctuates within the range of 9A-11A, and in order to solve the value mismatch between Vmpp and Impp, the problem that Vmpp is much smaller than Impp is solved by connecting 20 or 24 solar cells in parallel at the photovoltaic module end, so that the size of the prepared photovoltaic module is large.
In the process step of preparing the PN junction by the diffusion of the POCl3 in the single cell, the uniform doping of the diffusion gas cannot be realized due to the too small gap between the loading positions of the cell plates in the quartz boat, so that the prepared PN junction is not uniform, namely, high and low junctions are manufactured in the single cell plate, thereby causing the recombination loss of photogenerated carriers in the PN high and low junctions,
in addition, because the number of solar cells connected in series in a cell string is large, the collected carrier loss caused by uneven diffused PN junctions in a single solar cell and the power loss caused by series mismatch between the solar cells connected in series are caused, and the dual power loss factor greatly reduces the output power of the photovoltaic module.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a single crystalline silicon solar cell for increasing output voltage, it constructs the structure of series connection hookup between battery cell through laser scribing a plurality of independent battery cell each other electrical insulation on single crystalline silicon solar cell to reach the purpose that increases single battery output voltage and reduce single battery output current.
Realize the utility model discloses the technical scheme of purpose is: the utility model has a crystal silicon wafer; the front side of the crystal silicon wafer is engraved with at least one front side electric insulation area, and the crystal silicon wafer is divided into a plurality of small battery units which are mutually electrically insulated by the front side electric insulation area; the front side electric insulation region is a groove with the etching depth exceeding the PN junction but not penetrating through the crystal silicon wafer; the front surface of each small cell is provided with a confluence layer for collecting electrons and a main grid electrode area for receiving the electrons collected by the confluence layer; back electrode regions are arranged on the back of each small cell, and back electric insulation regions are arranged between adjacent back electrode regions; the main grid electrode area is provided with at least one through hole which penetrates through the crystal silicon wafer; one end of the through hole, which is positioned on the back surface of the crystal silicon wafer, is positioned in the back electrode area of the other small cell; filling solidified conductive slurry in the through hole; the last small battery unit is connected with the next small battery unit in series through the conductive slurry solidified in the through hole; the small battery unit connected with the next small battery unit in series is not required to be provided with a through hole.
The front side electrically insulating region can be prepared in a number of ways, not limited to: laser etching to remove the diffused doped layer, laser etching or printing etching slurry to remove the silicon material with the depth larger than the PN junction depth, printing insulating slurry and depositing a dielectric layer.
The front side of the crystal silicon wafer is divided into four small battery units which are respectively an A area, a B area, a C area and a D area through four front side electric insulation areas; the four front side electric insulation areas are arranged in a cross shape; the main gate electrode area of the area A is arranged close to the front side electric insulation area between the area A and the area B; the main gate electrode area of the B area is arranged close to the front side electric insulation area between the B area and the C area; the main gate electrode region of region C is disposed against the front electrically insulating region between region C and region D.
As a variant, the front surface of the crystalline silicon wafer is divided into a plurality of battery cells by a plurality of front surface electric insulation regions which are arranged in parallel at intervals. As a further optimization design, the front surface of the crystal silicon wafer is divided into four small battery units by three front surface electric insulation regions which are arranged in parallel at intervals.
Each main grid electrode area is provided with a plurality of through holes along the extending direction.
And also has a front passivation layer and a back passivation layer; the front passivation layer covers the front side of the crystal silicon wafer and is positioned below the confluence layer and the main gate electrode area; the back passivation layer covers the back of the crystal silicon wafer and is positioned above the back electrode area.
The front passivation layer is a SiNx layer or a laminated passivation layer of SiO2 and SiNx; the back passivation layer is an aluminum back surface field, a SiNx layer, a double-layer passivation layer of the SiNx and the aluminum back surface field, a laminated passivation layer of Al2O3 and SiNx, a laminated passivation layer of SiO2 and SiNx, or a multi-layer passivation layer of SiO2, Al2O3 and SiNx.
The bus layer comprises a printed fine grid and a fine main grid; the thin main grid is connected with the thin main grid, and the thin main grid is connected with the electrode area of the main grid.
The back side electric insulation area is a non-pattern printing area when the back electrode area is printed. When the back electrode areas are printed, no graph is printed between the adjacent back electrode areas, and the electric insulation effect is realized through a passivation layer prepared on the surface of the crystal silicon wafer.
The conductive paste can be silver paste. And can be consistent with the materials used for printing the manifold layer, the main gate electrode region and the back electrode region.
The crystal silicon wafer is a P-type crystal silicon wafer or an N-type crystal silicon wafer.
The thickness of the current crystal silicon wafer is generally 160-200 um, the P-type crystal silicon wafer is subjected to high-temperature diffusion to prepare a PN junction with the diffusion depth of generally 0.1-0.3um, compared with the thickness of the whole crystal silicon wafer, the depth of the PN junction is very shallow, the PN junction can be used as a dangling bond for photon-generated carrier recombination due to the fact that the complete crystal structure of the silicon wafer is broken when laser is etched on the surface of the silicon wafer, and the shallow PN junction creates a precondition for laser etching of small cells of a battery which are electrically insulated from each other on a large-area crystal silicon wafer and reducing damage caused by laser etching. On the basis of the theory, the depth of the groove can be selected to be larger than the depth of the PN junction and smaller than the thickness of the silicon wafer. Because the crystalline silicon belongs to a semiconductor material, the conductivity of the P-type doped crystalline silicon substrate is very low, even if partial phosphorus atoms penetrate into the silicon wafer after the PN junction is diffused, the high-temperature diffusion process can manufacture a shallow PN junction with high sheet resistance by damaging the ordered structure of the crystalline silicon and manufacturing more photon-generated carrier recombination centers due to the fact that the phosphorus atoms are diffused and doped in the high-temperature diffusion process, and the shallow PN junction only needs to be manufactured by laser to be a shallow layer serving as an electrically insulated groove. Photogenerated carriers are transported towards a higher conductivity junction layer rather than a lower conductivity silicon substrate, which creates a feasible theoretical basis for fabricating small cells of individual cells on a silicon wafer that are electrically isolated from each other.
The utility model discloses has positive effect: (1) the utility model discloses a divide a plurality of battery subelements with single crystal silicon piece, and the PN junction homogeneity of battery subelement is superior to single crystal silicon piece, but the carrier composite loss that this kind of PN junction of light-harvesting charge carrier greatly reduced brought in the subelement.
(2) The utility model discloses divide into a plurality of battery cell with single crystalline silicon solar cell, and the battery structural design through series connection between the cell, the output voltage of multiplicable single crystalline silicon solar cell, because single crystalline silicon solar cell's output voltage increases, the number of battery cluster series connection 20 or 24 battery pieces of reducible current conventional photovoltaic module in photovoltaic module end, structural design is more nimble, and because the power loss that the current mismatch between the battery cluster leads to can also be reduced to the battery cluster figure of establishing ties reduces.
(3) The utility model discloses because single crystalline silicon solar cell divides into the independent battery cell that the quantity is unequal, consequently the electric current of single battery piece reduces, and single crystalline silicon solar cell's resistance is unchangeable on the whole, therefore the current transmission loss greatly reduced between the single crystalline silicon solar cell, further explains through following formula:
assuming that a single crystalline silicon solar cell is divided into 4 independent small cells as shown in fig. 1, the output current of the single crystalline silicon solar cell is IoResistance is RoThe current and resistance of each small battery cell after being divided into 4 small battery cells are respectively
The power loss of a single crystalline silicon solar cell when not scribed as an independent cell small unit is
And the power loss after division into 4 small battery units is
Therefore, the single crystalline silicon solar cell is scribed into independent small cell units, and the power loss caused by the resistance of the single crystalline silicon solar cell is reduced to the original power loss
Drawings
In order that the present invention may be more readily and clearly understood, the following detailed description of the present invention is given in conjunction with the accompanying drawings, in which
Fig. 1 is a schematic front view of embodiment 1 of the present invention;
fig. 2 is a cross-sectional view of embodiment 1 of the present invention;
FIG. 3 is a schematic structural diagram of a crystalline silicon wafer according to embodiment 1 of the present invention;
fig. 4 is a schematic back view of embodiment 1 of the present invention;
fig. 5 is a schematic circuit connection diagram of embodiment 1 of the present invention;
fig. 6 is a schematic front view of embodiment 2 of the present invention.
Detailed Description
(example 1)
Referring to fig. 1 to 5, the present invention relates to a P-type doped crystalline silicon wafer 1; the thickness of the crystal silicon wafer 1 is generally 160um-200um, and the P-type crystal silicon wafer is subjected to high-temperature diffusion to prepare a PN junction with the diffusion depth of generally 0.1-0.5 um; four front electric insulation regions 2 which are distributed in a cross shape are engraved on the front surface of the crystal silicon wafer 1, and the crystal silicon wafer 1 is divided into four small battery units 3 which are mutually electrically insulated by the four front electric insulation regions 2 and are respectively an area A, an area B, an area C and an area D; the front side electric insulation region 2 is a groove with the etching depth exceeding the PN junction but not penetrating through the crystal silicon wafer 1, and the depth of the groove can be selected from 0.5-1 um.
The front surface of each small cell 3 is provided with a confluence layer 4 for collecting electrons and a main grid electrode region 5 for receiving the electrons collected from the confluence layer 4; the bus layer 4 comprises a printed fine grid 41 and a fine main grid 42; the fine grid 41 is connected with the fine main grid 42, and the fine main grid 42 is connected with the main grid electrode area 5; the back of each small cell 3 is provided with a back electrode area 6, and a back electric insulation area 7 is arranged between the adjacent back electrode areas 6; the main grid electrode area 5 is provided with a plurality of through holes 8 which are distributed along the extension direction and penetrate through the crystal silicon wafer 1; one end of the through hole 8 positioned on the back surface of the crystal silicon wafer 1 is positioned on the back electrode area 6 of the other small cell 3; and the through hole 8 is filled with solidified conductive paste 9. The conductive paste 9 is silver paste.
The main gate electrode region 5 of the region A is arranged against the front side electric insulation region 2 between the region A and the region B; the main gate electrode region 5 of the region B is arranged against the front side electric insulation region 2 between the region B and the region C; the main gate electrode region 5 of region C is located against the front electrically insulating region 2 between region C and region D.
The negative electrode of the small cell 3 corresponding to the area a is electrically connected with the back electrode area 6 of the small cell 3 corresponding to the area B, i.e. the positive electrode of the small cell 3, the negative electrode of the small cell 3 corresponding to the area B is electrically connected with the back electrode area 6 of the small cell 3 corresponding to the area C, i.e. the positive electrode of the small cell 3, and the negative electrode of the small cell 3 corresponding to the area C is electrically connected with the back electrode area 6 of the small cell 3 corresponding to the area D, i.e. the positive electrode of the small cell 3.
And also has a front passivation layer and a back passivation layer; the front passivation layer covers the front of the crystalline silicon wafer 1 and is positioned below the confluence layer 4 and the main gate electrode area 5; the back passivation layer covers the back of the crystalline silicon wafer 1 and is positioned above the back electrode region 6.
The front passivation layer is a SiNx layer or a laminated passivation layer of SiO2 and SiNx; the back passivation layer is an aluminum back surface field, a SiNx layer, a double-layer passivation layer of the SiNx and the aluminum back surface field, a laminated passivation layer of Al2O3 and SiNx, a laminated passivation layer of SiO2 and SiNx, or a multi-layer passivation layer of SiO2, Al2O3 and SiNx.
The back side electrical insulation region 7 is a non-graphic printed region when the back electrode region 6 is printed.
(example 2)
See fig. 6, in the present invention, the front surface of the crystalline silicon wafer 1 is divided into four small battery units 3 by the three front electrical insulation regions 2 arranged in parallel at intervals. The four small battery cells 3 are connected in series in the series connection manner in embodiment 1.
Other technical features are the same as those of embodiment 1.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A single crystalline silicon solar cell for increasing the output voltage, having a crystalline silicon wafer (1); the method is characterized in that: at least one front electric insulation area (2) is engraved on the front surface of the crystalline silicon wafer (1), and the crystalline silicon wafer (1) is divided into a plurality of small battery units (3) which are mutually electrically insulated by the front electric insulation area (2); the front side electric insulation region (2) is a groove with the etching depth exceeding a PN junction but not penetrating through the crystal silicon wafer (1); the front surface of each small cell (3) is provided with a confluence layer (4) for collecting electrons and a main grid electrode area (5) for receiving the electrons collected from the confluence layer (4); back electrode regions (6) are arranged on the back of each small cell (3), and back electric insulation regions (7) are arranged between the adjacent back electrode regions (6); the main grid electrode area (5) is provided with at least one through hole (8) which penetrates through the crystal silicon wafer (1); one end of the through hole (8) positioned on the back surface of the crystal silicon wafer (1) is positioned on the back electrode area (6) of the other small cell (3); the through hole (8) is filled with solidified conductive slurry (9); the last small battery unit (3) is connected with the next small battery unit (3) in series through the conductive paste (9) solidified in the through hole (8); the small battery unit (3) which is not required to be connected with the next small battery unit (3) in series is not provided with a through hole (8).
2. A single crystalline silicon solar cell for increasing output voltage according to claim 1, characterized in that: the front surface of the crystal silicon wafer (1) is divided into four small battery units (3) through four front surface electric insulation regions (2), wherein the four small battery units are respectively an A region, a B region, a C region and a D region; the four front side electric insulation regions (2) are arranged in a cross shape; the main gate electrode area (5) of the area A is arranged against the front side electric insulation area (2) between the area A and the area B; the main gate electrode area (5) of the B area is arranged against the front side electric insulation area (2) between the B area and the C area; the main gate electrode region (5) of region C is located against the front electrically insulating region (2) between region C and region D.
3. A single crystalline silicon solar cell for increasing output voltage according to claim 1, characterized in that: the front surface of the crystal silicon wafer (1) is divided into a plurality of small battery units (3) through a plurality of front surface electric insulation regions (2) which are arranged in parallel at intervals.
4. A single crystalline silicon solar cell for increasing output voltage according to claim 3, characterized in that: the front surface of the crystal silicon wafer (1) is divided into four small battery units (3) through three front surface electric insulation regions (2) which are arranged in parallel at intervals.
5. A single crystalline silicon solar cell for increasing output voltage according to claim 1 or 2 or 3 or 4, characterized in that: a plurality of through holes (8) are distributed on each main gate electrode area (5) along the extending direction.
6. A single crystalline silicon solar cell for increasing output voltage according to claim 1, characterized in that: also has a front passivation layer and a back passivation layer; the front passivation layer covers the front of the crystalline silicon wafer (1) and is positioned below the confluence layer (4) and the main gate electrode area (5); the back passivation layer covers the back of the crystal silicon wafer (1) and is positioned above the back electrode area (6).
7. The single crystalline silicon solar cell for increasing output voltage of claim 6, wherein: the front passivation layer is a SiNx layer or a laminated passivation layer of SiO2 and SiNx; the back passivation layer is an aluminum back surface field, a SiNx layer, a double-layer passivation layer of the SiNx and the aluminum back surface field, a laminated passivation layer of Al2O3 and SiNx, a laminated passivation layer of SiO2 and SiNx, or a multi-layer passivation layer of SiO2, Al2O3 and SiNx.
8. A single crystalline silicon solar cell for increasing output voltage according to claim 1, characterized in that: the bus layer (4) comprises a printed fine grid (41) and a fine main grid (42); the thin grid (41) is connected with the thin main grid (42), and the thin main grid (42) is connected with the main grid electrode area (5).
9. A single crystalline silicon solar cell for increasing output voltage according to claim 1, characterized in that: the back side electric insulation area (7) is a non-pattern printing area when the back electrode area (6) is printed.
10. A single crystalline silicon solar cell for increasing output voltage according to claim 1, characterized in that: the crystal silicon wafer (1) is a P-type crystal silicon wafer or an N-type crystal silicon wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120577450.2U CN214378472U (en) | 2021-03-22 | 2021-03-22 | Single crystalline silicon solar cell for increasing output voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120577450.2U CN214378472U (en) | 2021-03-22 | 2021-03-22 | Single crystalline silicon solar cell for increasing output voltage |
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| Publication Number | Publication Date |
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| CN214378472U true CN214378472U (en) | 2021-10-08 |
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| CN202120577450.2U Active CN214378472U (en) | 2021-03-22 | 2021-03-22 | Single crystalline silicon solar cell for increasing output voltage |
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- 2021-03-22 CN CN202120577450.2U patent/CN214378472U/en active Active
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