CN214375724U

CN214375724U - Display panel and electronic device

Info

Publication number: CN214375724U
Application number: CN202120083073.7U
Authority: CN
Inventors: 胡杨; 郭远辉; 石侠; 高玉杰
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2021-01-13
Filing date: 2021-01-13
Publication date: 2021-10-08
Anticipated expiration: 2031-01-13

Abstract

The present disclosure relates to a display panel and an electronic apparatus. The display panel may include an array substrate and an opposite substrate provided to the cell: the array substrate comprises a scanning line, a data line, a first retaining wall and a second retaining wall; the first retaining wall and the second retaining wall are respectively positioned at two opposite sides of the scanning line, and the first retaining wall and the second retaining wall comprise a first barrier layer arranged at the same layer as the scanning line and a second barrier layer arranged at the same layer as the data line; the distance between the first barrier layer and the scanning line in the first direction is smaller than that between the second barrier layer and the scanning line in the first direction; the opposite base plate comprises a spacer, and the orthographic projection of the spacer on the first substrate is positioned in the orthographic projection of the scanning line on the first substrate and between the orthographic projections of the first retaining wall and the second retaining wall on the first substrate; the size of the spacer close to the surface of the first substrate in the first direction is larger than the distance between the first barrier layer and the scanning line in the first direction. The scheme can improve the product quality.

Description

Display panel and electronic device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and an electronic device.

Background

As liquid crystal panels are developed, high-resolution products are developed, but as the number of pixels increases, a series of problems are likely to occur, such as: when a certain pressure test or drop test is carried out on the liquid crystal panel, the problems of uneven brightness such as bright spots, snowflakes and the like are easy to occur; in addition, the electrode structure in the panel is easily affected by impurity particles (particles) in the manufacturing process, and the bad conditions such as disconnection and the like are easily formed, so that the pixel failure is caused, the product yield is reduced, and the product reliability and the product quality are affected.

SUMMERY OF THE UTILITY MODEL

An object of the present disclosure is to provide a display panel and an electronic device, thereby overcoming, at least to some extent, one or more of the problems due to the limitations and disadvantages of the related art.

A first aspect of the present disclosure provides a display panel including an array substrate and an opposite substrate provided to a cell:

the array substrate comprises a first substrate, and a scanning line, a data line, a first retaining wall and a second retaining wall which are formed on one side of the first substrate, which is close to the opposite substrate; the data lines extend in a first direction, the scan lines extend in a second direction, and the first direction intersects the second direction; the first retaining wall and the second retaining wall are respectively positioned at two opposite sides of the scanning line in the first direction, the first retaining wall and the second retaining wall respectively comprise a first blocking layer which is arranged on the same layer as the scanning line and is mutually spaced and a second blocking layer which is arranged on the same layer as the data line and is mutually spaced, and the orthographic projection of the second blocking layer on the first substrate is overlapped with the orthographic projection of the first blocking layer on the first substrate; the distance between the first barrier layer and the scanning line in the first direction is a first distance, the distance between the second barrier layer and the scanning line in the first direction is a second distance, and the second distance is larger than the first distance;

the opposite substrate comprises a second substrate and a spacer positioned on one side of the second substrate close to the array substrate, the surface of the spacer close to the first substrate is a top surface, and the orthographic projection of the top surface of the spacer on the first substrate is positioned in the orthographic projection of the scanning line on the first substrate and between the orthographic projections of the first retaining wall and the second retaining wall on the first substrate; and the top surface of the spacer has a dimension in the first direction greater than the first pitch.

In an exemplary embodiment of the present disclosure, a ratio between a dimension of the top surface of the spacer in the first direction and the first pitch is 2 or more.

In one exemplary embodiment of the present disclosure, a distance between the second barrier layer and the spacer in the first direction is a third distance, and a ratio between the third distance and a dimension of the top surface of the spacer in the first direction is equal to or greater than 0.5.

In an exemplary embodiment of the present disclosure, a ratio between the third pitch and a dimension of the top surface of the spacer in the first direction is 1 or more.

In an exemplary embodiment of the present disclosure, a ratio between the third pitch and a dimension of the data line in the second direction is 2 to 4.

In an exemplary embodiment of the present disclosure, an orthographic projection of the second barrier layer on the first substrate is located within an orthographic projection of the first barrier layer on the first substrate, and the first direction is perpendicular to the second direction.

In an exemplary embodiment of the present disclosure, the array substrate further includes a first common line formed on the first substrate and extending in the second direction, the first common line being disposed at the same layer as the scan line and spaced apart from each other;

the first blocking layer of the second retaining wall is a partial structure of the first common line.

In an exemplary embodiment of the present disclosure, the array substrate further includes a plurality of sub-pixel units arranged in an array on the first substrate along the second direction and the first direction;

each of the sub-pixel units includes a pixel electrode, a common electrode, and a transistor: the transistor comprises a grid electrode, a first electrode and a second electrode, wherein the grid electrode is connected with the scanning line, the first electrode is connected with the pixel electrode, and the second electrode is connected with the data line;

an orthographic projection of the common electrode on the first substrate overlaps with an orthographic projection of the pixel electrode on the first substrate, and the common electrode is connected with the first common line.

In an exemplary embodiment of the present disclosure, the pixel electrode is located on a side of the common electrode away from the first substrate, and the pixel electrode includes:

the first electrode part comprises a first connecting strip extending in the first direction and a plurality of first electrode strips arranged at intervals in the first direction, the first connecting strip is provided with a first side and a second side which are opposite in the second direction, the plurality of first electrode strips are positioned on the first side of the first connecting strip and connected with the first connecting strip, and the end parts, far away from the first connecting strip, of the adjacent first electrode strips are in an open shape;

a second electrode portion arranged at a distance from the first electrode portion in the first direction, the second electrode portion including a second connection bar extending in the first direction and a plurality of second electrode bars arranged at a distance in the first direction, the second connection bar being located at a position where the first side is away from the second side, the second connection bar having a third side and a fourth side opposite to each other in the second direction, the third side being located at a position where the fourth side is close to the first side; the plurality of second electrode strips are positioned on the third side of the second connecting strip and connected with the second connecting strip, and the ends, far away from the second connecting strip, of the adjacent second electrode strips are in an open shape;

a conductive connection part between the first electrode part and the second electrode part, both ends of the conductive connection part being connected to the first connection bar and the second connection bar, respectively; and the area of the conductive connecting part is larger than the area of the first electrode strip and the area of the second electrode strip.

In an exemplary embodiment of the present disclosure, the conductive connection portion includes a first conductive connection bar and a second conductive connection bar which are arranged at an interval in the second direction and both extend in the first direction, and at least two third conductive connection bars which are located between the first conductive connection bar and the second conductive connection bar and arranged at an interval in the first direction, and both ends of each of the third conductive connection bars are connected to the first conductive connection bar and the second conductive connection bar, respectively;

the first conductive connecting strip is connected with the first connecting strip, and the second conductive connecting strip is connected with the second connecting strip.

In an exemplary embodiment of the present disclosure, the first electrode bar, the second electrode bar and the third conductive connecting bar all extend in a third direction, and the first widths of the first electrode bar, the second electrode bar and the third conductive connecting bar are equal;

wherein the first width is a dimension in a fourth direction, the third direction is perpendicular to the fourth direction, and the third direction intersects the first direction and the second direction.

In an exemplary embodiment of the present disclosure, the array substrate further includes: and the second common line is arranged on the same layer as the data line and is spaced from the data line, the second common line extends in the first direction, and two ends of the second common line are respectively connected with the common electrodes of two adjacent sub-pixel units in the first direction through first via structures.

In an exemplary embodiment of the present disclosure, the first via structure includes a first via portion, a second via portion, and a via connection portion disposed at the same layer as the pixel electrode and spaced apart from each other, the via connection portion being connected to the second common line through the first via portion, and the via connection portion being connected to the common electrode through the second via portion.

A second aspect of the present disclosure provides an electronic device including the display panel of any one of the above.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic view showing a structure of an electrode structure in the related art;

fig. 2 shows a schematic structural diagram of an electrode structure according to an embodiment of the present disclosure;

FIG. 3 shows a schematic structural diagram of an electrode structure according to another embodiment of the present disclosure;

fig. 4 is a schematic partial structure diagram of a display panel according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 6 is an enlarged schematic view of the portion A shown in FIG. 5;

FIG. 7 shows a schematic cross-sectional view along the direction C-C in FIG. 6;

fig. 8 shows an enlarged structural schematic diagram of the first via structure in fig. 5.

Reference numbers in fig. 1:

10. a slit electrode; 11. a slit;

reference numerals in fig. 2 to 8:

20. a first electrode section; 201. a first connecting bar; 201a, a first side; 201b, a second side; 202. a first electrode strip; 21. a second electrode section; 211. a second connecting strip; 211a, a third side; 211b, fourth side; 212. a second electrode strip; 213. a signal connection portion; 22. a conductive connection portion; 221. a first conductive connecting strip; 222. a second conductive connecting strip; 223. a third conductive connecting strip;

3. an array substrate; 30. a first substrate; 301. a sub-pixel region; 302. a first wiring region; 303. a second wiring region; 31. scanning a line; 32. a first common line; 33. a data line; 34. a pixel electrode; 35. a common electrode; 36. a transistor; 360. an active layer; 361. a gate electrode; 362. a first pole; 363. a second pole; 37. a second common line; 38a, a first retaining wall; 38b, a second retaining wall; 381. a first barrier layer; 382. a second barrier layer;

4. an opposing substrate; 40. a shielding layer; 41. a second substrate; 42. a spacer;

5. liquid crystal molecules.

Detailed Description

The technical solution of the present disclosure is further specifically described below by way of examples and with reference to the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the general concepts of the disclosure and should not be taken as limiting the disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details.

The TFT-LCD (Thin Film Transistor-Liquid Crystal Display) technology is a technology which skillfully combines the microelectronic technology and the Liquid Crystal Display technology. The technology of micro-electronic fine processing on Si (silicon-based) is utilized, and then the micro-electronic fine processing is transplanted to large-area glass to process a TFT array so as to form an array substrate; then the array substrate and another substrate with a color film layer (i.e. a counter substrate) are aligned by using the mature LCD technology to form a liquid crystal box, and then the liquid crystal display panel is formed through the processes of post-processing such as polarizer pasting and the like.

It should be understood that the liquid crystal cell further includes a Spacer (PS), which mainly serves to support the liquid crystal cell, so that the cell thickness of each region of the liquid crystal display panel is consistent, and the brightness uniformity of the panel is ensured. However, for horizontal electric field deflection products such as ADS (Advanced Super Dimension Switching) or IPS (In-Plane Switching), when the panel is subjected to external stress, PS may move, and if the movement is large, PS may scratch an alignment film (i.e., PI film) on a slit electrode (electrode structure with slits), so that liquid crystal alignment In the area fails, light leakage occurs at L0, and an irregular bright spot is formed macroscopically, thereby affecting the product quality.

In the related art, as shown in fig. 1, a slit electrode 10 of a liquid crystal display panel is designed to have a slit 11 formed therein and the periphery of the slit 11 is closed, but the slit electrode 10 has poor luminous efficiency at the periphery thereof, so that poor display is likely to occur.

In order to solve the above technical problem, embodiments of the present disclosure provide an electrode structure, which can be used in a liquid crystal display panel and can be used as a pixel electrode or a common electrode of the liquid crystal display panel; for example, the electrode structure may be an ITO (indium tin oxide) electrode, which is transparent.

In detail, as shown in fig. 2, the electrode structure may include a first electrode portion 20, a conductive connection portion 22, and a second electrode portion 21 sequentially arranged in a first direction Y; wherein:

the first electrode portion 20 may include a first connecting bar 201 extending in the first direction Y and a plurality of first electrode bars 202 arranged at intervals in the first direction Y, the first connecting bar 201 has a first side 201a and a second side 201b opposite to each other in the second direction X, the plurality of first electrode bars 202 are located on the first side 201a of the first connecting bar 201 and connected to the first connecting bar 201, and ends of adjacent first electrode bars 202 far from the first connecting bar 201 are open, that is, there is no connection between ends of adjacent first electrode bars 202 far from the first connecting bar 201.

It should be noted that, the plurality of first electrode bars 202 are arranged at intervals in the first direction Y, that is, the first gap S1 is formed between the adjacent first electrode bars 202, and the first gap S1 is semi-open.

The second electrode portion 21 includes a second connecting bar 211 extending in the first direction Y and a plurality of second electrode bars 212 arranged at intervals in the first direction Y, the second connecting bar 211 is located at a position where the first side 201a is far away from the second side 201b, the second connecting bar 211 has a third side 211a and a fourth side 211b opposite to each other in the second direction X, the third side 211a is located at a position where the fourth side 211b is close to the first side 201a, and it should be noted that the second direction X is perpendicular to the first direction Y; the plurality of second electrode strips 212 are located on the third side 211a of the second connecting strip 211 and connected to the second connecting strip 211, and ends of adjacent second electrode strips 212 far away from the second connecting strip 211 are open, that is, ends of adjacent second electrode strips 212 far away from the second connecting strip 211 are not connected.

It should be noted that, the plurality of second electrode bars 212 are arranged at intervals in the first direction Y, that is, the second gap S2 is formed between the adjacent second electrode bars 212, and the second gap S2 is semi-open.

The conductive connection portion 22 is located between the first electrode portion 20 and the second electrode portion 21, and both ends of the conductive connection portion 22 are connected to the first connection bar 201 and the second connection bar 211, respectively.

In the embodiment of the present disclosure, by designing the first electrode portion 20 and the second electrode portion 21 of the electrode structure with the first slit S1 and the second slit S2 in a semi-open manner, respectively, liquid crystal molecules can be deflected at the openings of the first slit S1 and the second slit S2; therefore, compared to the closed electrode structure around the gap shown in fig. 1, the light efficiency around the electrode structure can be improved.

Further, as shown in fig. 2, one of the first slit S1 of the first electrode portion 20 and the second slit S2 of the second electrode portion 21 is open rightward and the other is open leftward; namely: the openings of the first slit S1 of the first electrode part 20 and the second slit S2 of the second electrode part 21 are opposite, so that the light efficiency of the electrode structure at two sides (i.e., the left side and the right side in fig. 2) in the second direction X can be balanced, and the light efficiency around the electrode structure is more balanced, thereby improving the display effect.

Optionally, orthographic projections of the first electrode portion 20, the second electrode portion 21 and the conductive connection portion 22 on the reference plane coincide with each other, where the coincidence mentioned herein refers to complete coincidence within an error allowable range, so that design difficulty of the electrode structure can be reduced, and arrangement of a plurality of electrode structures in the array substrate is facilitated, but not limited thereto, orthographic projections of the first electrode portion 20, the second electrode portion 21 and the conductive connection portion 22 on the reference plane may also be misaligned, depending on the specific situation.

It should be noted that the reference plane mentioned in the present disclosure is a plane perpendicular to the first direction Y.

Wherein the aforementioned first electrode strips 202 and second electrode strips 212 may be parallel to each other, i.e.: the extending directions of the first electrode bars 202 and the second electrode bars 212 are parallel to each other to equalize the light effects at the first electrode part 20 and the second electrode part 21. Specifically, the first electrode stripes 202 and the second electrode stripes 212 each extend in a third direction Q, and the third direction Q intersects with the first direction Y and the second direction X, that is, the third direction Q is not parallel or collinear with the first direction Y and the second direction X, so that the color shift can be reduced to improve the display effect.

For example, the acute angle included between the third direction Q and the second direction X may be 5 ° to 15 °, such as: 5 °, 7 °, 9 °, 11 °, 13 °, 15 °, and so on.

Alternatively, the first width of the first electrode stripes 202 may be equal to the first width of the second electrode stripes 212; in addition, the first width of the first slit S1 may be equal to the first width of the second slit S2, so that the light effects at the first electrode portion 20 and the second electrode portion 21 may be further equalized to improve the product display effect.

It should be noted that the first width mentioned in the present disclosure refers to a dimension in a fourth direction P, and the fourth direction P is perpendicular to the third direction Q.

In order to ensure good liquid crystal molecule deflection at the first electrode part 20 and the second electrode part 21, the light effect at the first electrode part 20 and the second electrode part 21 is improved; the first width of the first electrode bar 202, the first width of the first slit S1, the first width of the second electrode bar 212, and the first width of the second slit S2 are required to satisfy a certain requirement; namely: the ratio of the first width of the first slit S1 to the first width of the first electrode bar 202 may be 1 to 4, such as: 1. 1.5, 2, 2.5, 3, 3.5, 4, etc.

Specifically, the first width of the first electrode stripes 202 and the second electrode stripes 212 of the embodiments of the present disclosure may be 1.8 μm to 3 μm, such as: 1.8. mu.m, 2. mu.m, 2.2. mu.m, 2.4. mu.m, 2.6. mu.m, 2.8. mu.m, 3 μm, etc.; the first width of the first and second slits S1 and S2 may be 3 μm to 7 μm, such as: 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, and the like.

In addition, in order to further balance the light effects at the first electrode part 20 and the second electrode part 21, the display effect of the product is improved; the second width of the first connection bar 201 and the second width of the second connection bar 211 may be equal. The second widths of the first connecting bar 201 and the second connecting bar 211 may be equal to the first widths of the first electrode bar 202 and the second electrode bar 212, but are not limited thereto, and may also be slightly larger than the first widths of the first electrode bar 202 and the second electrode bar 212, so as to improve the light efficiency, and at the same time, improve the condition that the first widths of the first connecting bar 201 and the second connecting bar 211 are too small to cause easy disconnection, and improve the product yield.

It should be noted that the second width mentioned in the embodiments of the present disclosure is a dimension in the second direction X.

In order to avoid the conductive connection portion 22 from being broken due to the influence of particles of impurities during the manufacturing process, the area of the conductive connection portion 22 in the embodiment of the present disclosure is designed to be larger so as to avoid the pixel failure caused by the broken line, and specifically, the area of the conductive connection portion 22 in the embodiment of the present disclosure is larger than the area of the first electrode bar 202 and the area of the second electrode bar 212.

It should be understood that the conductive connection portion 22 may also extend in the third direction Q as a whole to reduce the difficulty of processing and designing. For example, when the orthographic projection of the conductive connection portion 22 on the reference plane coincides with the orthographic projection of the first electrode portion 20 and the second electrode portion 21 on the reference plane, in order to make the area of the conductive connection portion 22 larger than the areas of the first electrode bar 202 and the second electrode bar 212, the present embodiment may make the first width of the first electrode bar 202 and the first width of the second electrode bar 212 smaller than the first width of the conductive connection portion 22 as a whole.

In an embodiment of the present disclosure, as shown in fig. 3, the conductive connection portion 22 may include a first conductive connection bar 221, a second conductive connection bar 222, and at least two third conductive connection bars 223; the first conductive connecting strips 221 and the second conductive connecting strips 222 extend in the first direction Y, the first conductive connecting strips 221 and the second conductive connecting strips 222 are arranged at intervals in the second direction X, the first conductive connecting strips 221 are connected with the first connecting strips 201, and the second conductive connecting strips 222 are connected with the second connecting strips 211; at least two third conductive connecting bars 223 are arranged at intervals in the first direction Y and located between the first conductive connecting bar 221 and the second conductive connecting bar 222, and two ends of each third conductive connecting bar 223 (i.e., two ends in the extending direction thereof) are respectively connected with the first conductive connecting bar 221 and the second conductive connecting bar 222, that is, a third gap S3 is formed between adjacent third conductive connecting bars 223, and the periphery of the third gap S3 is closed.

In the embodiment of the present disclosure, by performing the slit design (i.e. the third slit S3) inside the conductive connection portion 22, on one hand, the light effect loss above the conductive connection portion 22 can be reduced, so that the overall light effect of the electrode structure can be improved, and on the other hand, the first electrode portion 20 and the second electrode portion 21 can be connected and conducted through at least two wires (i.e. the third conductive connection strip 223), so that even if one of the wires is disconnected due to the parametric, the other wires still connect and conduct the first electrode portion 20 and the second electrode portion 21, so that the occurrence rate of pixel failure can be greatly reduced, that is: the product yield is improved.

Alternatively, two third conductive connecting strips 223 are provided, so that the proportion of the conductive connecting portion 22 in the electrode structure can be reduced appropriately while ensuring the connection conduction between the first electrode portion 20 and the second electrode portion 21 is stable, that is: more design space is provided for the first electrode part 20 and the second electrode part 21, in other words, the area of the first electrode part 20 and the second electrode part 21 can be larger than that of the conductive connecting part 22, and since the gap between the first electrode part 20 and the second electrode part 21 is in a semi-open design and the gap between the conductive connecting part 22 is in a closed design, the light efficiency at the first electrode part 20 and the second electrode part 21 is better than that at the conductive connecting part 22; by making the areas of the first electrode portion 20 and the second electrode portion 21 larger than the area of the conductive connecting portion 22, the light efficiency of the entire electrode structure can be improved, and the product quality can be improved. In addition, the third slit S3 is provided, so that the situation that the particle falls on the conductive connection portion 22 in the manufacturing process can be alleviated, the situation that the resistance value of the conductive connection portion 22 is increased due to the particle can be alleviated, and the influence on the driving of the pixel can be alleviated.

It should be understood that the third conductive connecting bar 223 is not limited to two, but may be provided with three, four, etc., as the case may be.

In order to further reduce the occupation ratio of the conductive connection portion 22 in the electrode structure, the length of the first conductive connection bar 221 and the length of the second conductive connection bar 222 are both smaller than the length of the first connection bar 201 and smaller than the length of the second connection bar 211. It should be understood that the length referred to herein is the dimension in the first direction Y.

Alternatively, the second width of the first conductive connection bar 221 and the second width of the first connection bar 201 may be equal, and the second width of the second conductive connection bar 222 and the second width of the second connection bar 211 may be equal.

In an embodiment of the present disclosure, the third conductive connection bar 223 may also extend in the third direction Q. Wherein, the first width of the third conductive connection bar 223 may be equal to the first width of the first electrode bar 202; in addition, the third gap S3 between the adjacent third conductive connection bars 223 may be equal to the first gap S1 between the adjacent first electrode bars 202 and the second gap S2 between the adjacent second electrode bars 212, so that the light effects at the conductive connection portion 22 and the first and

second electrode portions

20 and 21 may be equalized, thereby improving the product display effect.

Further, the fourth gap S4 between the third conductive connecting bar 223 and the first electrode bar 202, the fifth gap S5 between the third conductive connecting bar 223 and the second electrode bar 212 are equal to the aforementioned first gap S1, second gap S2, and third gap S3, so as to equalize the light effects at the conductive connecting portion 22, the first electrode portion 20, the second electrode portion 21, and the three, thereby improving the display effect of the product.

In another embodiment of the present disclosure, as shown in fig. 2, the conductive connection portion 22 may be a conductive connection bar extending in the third direction Q, wherein a ratio of the first width of the conductive connection bar to the first width of the first electrode bar 202 may be 1.5 to 5.5, that is, the conductive connection portion 22 is widened compared to the first electrode bar 202, so as to improve a condition that the conductive connection portion 22 is easily broken, and ensure product quality.

For example, when the conductive connection portion 22 is only one conductive connection bar, the first width of the conductive connection bar may be 5 μm to 10 μm, such as: 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and the like.

In an embodiment of the present disclosure, as shown in fig. 2 and 3, the second electrode portion 21 may further include a signal connection portion 213, and the signal connection portion 213 may be located on a side of the plurality of second electrode bars 212 away from the conductive connection portion 22 and connected to the second connection bar 211. For example, when the electrode structure of the present disclosure is a common electrode, the signal connection portion 213 may be connected to a common line in the array substrate, that is, the signal connection portion 213 may be used for receiving a common signal; but not limited thereto, when the electrode structure of the present disclosure is a pixel electrode, the signal connection portion 213 may also be connected to a source/drain electrode of a transistor in the array substrate, for receiving a signal transmitted from the source/drain electrode, for example: a data signal.

It should be noted that the dotted lines in fig. 2 and 3 do not have practical meanings, and are merely used to distinguish the aforementioned structures to facilitate understanding of the positional relationship between the aforementioned structures.

Further, it should be understood that the shape of the signal connection portion 213 is not limited to that shown in fig. 2 and 3, and may be other shapes as the case may be. It should be further noted that, the electrode structure mentioned in the embodiments of the present disclosure is an integral structure as a whole.

The embodiment of the present disclosure also provides a display panel, which may be a liquid crystal display panel; as shown in fig. 4, the display panel may include an array substrate 3 and a counter substrate 4 provided to the cell, and may further include liquid crystal molecules 5 between the counter substrate 4 and the array substrate 3.

The display panel of the embodiment of the present disclosure will be described in detail with reference to fig. 2 to 8.

As shown in fig. 5 to 7, the array substrate 3 may include a first substrate 30, and a plurality of sub-pixel units, a plurality of rows of scan lines 31, a plurality of rows of first common lines 32, and a plurality of columns of data lines 33 formed on the first substrate 30, wherein:

as shown in fig. 5, the first substrate 30 may have a plurality of sub-pixel regions 301 arranged in an array along a row direction X and a column direction Y, a first wiring region 302 between two adjacent rows of the sub-pixel regions 301, and a second wiring region 303 between two adjacent columns, where there is an overlap between the first wiring region 302 and the second wiring region 303.

For example, as shown in fig. 7, the first substrate 30 may be a single-layer structure, and the first substrate 30 may be a glass substrate, but is not limited thereto, and the first substrate 30 may also be a multi-layer structure. And the material of the first substrate 30 is not limited to glass, but may be other materials, such as: polyimide (PI) and the like, as the case may be.

As shown in fig. 5, a plurality of sub-pixel units each including a pixel electrode 34 at least partially located in the sub-pixel region 301, a common electrode 35, and a transistor 36 at least partially located in the first wiring region 302 are formed on the first substrate 30. In addition, a storage capacitor (not shown) may be further included in the sub-pixel unit.

In an embodiment of the present disclosure, as shown in fig. 5 and fig. 6, the transistor 36 may include an active layer 360, a gate electrode 361, and a first pole 362 and a second pole 363 disposed in the same layer; an insulating layer may be disposed between the gate 361 and the active layer 360 to insulate the gate 361 and the active layer 360, and the insulating layer may be made of inorganic materials, such as silicon oxide, silicon nitride, and the like. It should be noted that the gate 361 can be disposed at the same layer as the scan line 31, and the gate 361 can be part of the aforementioned scan line 31.

The transistor 36 may be a top gate type or a bottom gate type. In the embodiment of the present disclosure, the transistor 36 is mainly used as a bottom gate type. When the transistor 36 is a bottom gate type, a gate 361 is formed on the first substrate 30, and the gate 361 may include a metal material or an alloy material, such as molybdenum, aluminum, and titanium, to ensure good conductivity; an insulating layer is formed on the first substrate 30 and covers the gate electrode 361, and the insulating layer can be made of inorganic materials, such as: inorganic materials such as silicon oxide and silicon nitride; the active layer 360 is formed on a side of the insulating layer facing away from the first substrate 30, the first pole 362 and the second pole 363 are respectively connected to two doped regions of the active layer 360, and the first pole 362 and the second pole 363 may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, titanium, and the like, for example, the multi-layer structure is a multi-metal layer stack, such as a titanium, aluminum, titanium three-layer metal stack (Al/Ti/Al), and the like.

It should be understood that the number of the transistors 36 in the sub-pixel unit may be plural, and the transistors 36 are also classified into N-type, P-type, and the like.

In the embodiment of the disclosure, as shown in fig. 5 and fig. 6, the pixel electrode 34 may be connected to the first electrode 362, wherein the first electrode 362 of the transistor 36 may be a drain electrode, and the second electrode 363 may be a source electrode, but is not limited thereto, and the first electrode 362 of the transistor 36 may also be a source electrode, and the second electrode 363 is a drain electrode, as the case may be; and an orthogonal projection of the common electrode 35 on the first substrate 30 may overlap an orthogonal projection of the pixel electrode 34 on the first substrate 30.

At least one of the pixel electrode 34 and the common electrode 35 is the electrode structure described in any of the foregoing embodiments, so that the light efficiency around the pixel can be improved, and the product quality can be improved. It should be noted that the row direction X mentioned in the present embodiment may be the aforementioned second direction X, and the column direction Y may be the aforementioned first direction Y.

In the embodiment of the present disclosure, as shown in fig. 7, the pixel electrode 34 may be located on a side of the common electrode 35 away from the first substrate 30, that is, the common electrode 35 may be fabricated on the first substrate 30 before the pixel electrode 34; for example, the common electrode 35 may be a plate-shaped electrode; namely: the common electrode 35 is a whole block without slits; the pixel electrode 34 may be the electrode structure described in any of the foregoing embodiments; all liquid crystal molecules between the electrodes and right above the electrodes are deflected by an electric field generated between the pixel electrode 34 and the common electrode 35, so that the working efficiency of the liquid crystal can be improved, and the light transmission efficiency is increased.

It should be understood that the positional relationship between the pixel electrode 34 and the common electrode 35 in the present disclosure is not limited to the aforementioned relationship, for example: the pixel electrode 34 can also be located on one side of the common electrode 35 close to the first substrate 30, and this common electrode 35 is the electrode structure described in any of the foregoing embodiments; and the pixel electrode 34 is a plate electrode.

In the embodiment of the present disclosure, in order to ensure the light transmittance of the array substrate, the pixel electrode 34 may be made of an ITO material, but is not limited thereto, and may also be made of a transparent material such as Indium Zinc Oxide (IZO) and zinc oxide (ZnO); that is, since the pixel electrode 34 is made of a material different from the gate electrode 361, the first electrode 362 and the second electrode 363 of the transistor 36, the pixel electrode 34 and the gate electrode 361, the first electrode 362 and the second electrode 363 of the transistor 36 can be formed by different patterning processes.

For example, as shown in fig. 7, the common electrode 35 may be located on a side of the first pole 362 and the second pole 363 of the transistor 36 close to the first substrate 30; the common electrode 35 may be formed on the first substrate 30 before the gate 361 of the transistor 36 is formed, that is, when the array substrate is manufactured, the common electrode 35 may be formed on the first substrate 30 by using a first patterning process, and then the gate 361 of the transistor 36 may be formed on the first substrate 30 by using another patterning process. Note that, although the common electrode 35 and the gate electrode 361 are both formed over the first substrate 30, the common electrode 35 and the gate electrode 361 are disconnected from each other (i.e., are not connected to each other); it should be understood that the common electrode 35 may also be formed on the first substrate 30 after the gate 361 of the transistor 36 is formed, and this common electrode 35 may also be located on the side of the gate 361 away from the first substrate 30, as the case may be.

Similarly, in order to ensure the light transmittance of the array substrate, the pixel electrode 34 may also be made of a transparent conductive material such as ITO; the pixel electrode 34 may be formed on a side of the first pole 362 and the second pole 363 of the transistor 36 away from the first substrate 30, it is understood that there is an insulating layer between the pixel electrode 34 and the first pole 362 and the second pole 363 of the transistor 36, and the pixel electrode 34 may be connected to the first pole 362 of the transistor through a second via structure H2; specifically, when the pixel electrode 34 is the electrode structure mentioned in the foregoing embodiment, the pixel electrode 34 can be connected to the first electrode 362 of the transistor through the second via structure H2 via the signal connection portion 213, and it should be understood that the signal connection portion 213 can be located in the first wiring region 302.

When the pixel electrodes 34 have the electrode structure mentioned in the foregoing embodiment, the slit opening directions of the first electrode portions 20 in two adjacent pixel electrodes 34 in the first direction Y and the second direction X are opposite, and the slit openings of the second electrode portions 21 are opposite. In addition, it should be noted that the overall shape of each electrode structure in the array substrate 3 may be slightly different, for example: partial electrode structures need to be designed to avoid other structures in the array substrate 3, but it should be understood that, although the overall shape of each electrode structure in the array substrate 3 may not be exactly the same, the overall design concept should be the same, that is: the first electrode portion 20 and the second electrode portion 21 are both half-open, and the first width of the whole conductive connection portion 22 is greater than the first widths of the first electrode strip 202 and the second electrode strip 212.

As shown in fig. 5, at least one scan line 31 may be located in a first wiring area 302, in other words, at least one scan line 31 may be disposed in each first wiring area 302, and it should be understood that the scan lines 31 may be considered as extending in the row direction X as a whole; the scan line 31 is connected to the gate 361 of the transistor 36 in the sub-pixel unit, the scan line 31 and the gate 361 of the transistor 36 may be disposed on the same layer and be an integral structure, and the scan line 31 is configured to provide a scan signal to the sub-pixel unit.

As shown in fig. 5, at least one row of the first common lines 32 may be disposed in a first wiring region 302, in other words, at least one row of the first common lines 32 may be disposed in each first wiring region 302, it should be understood that the first common lines 32 may be regarded as extending in the row direction X as a whole; wherein, the first common line 32 may be connected to a common electrode 35 configured to provide a common signal to the sub-pixel units.

For example, the first common line 32 may be disposed at the same layer as the scan line 31; here, the aforementioned common electrode 35 may be disposed on the first substrate 30 prior to the scan line 31, and thus, in order to connect the first common line 32 with the common electrode 35, the first common line 32 and the common electrode 35 may be overlapped together during the fabrication of the first common line 32.

In the embodiment of the present disclosure, as shown in fig. 5, a row of scan lines 31 and a row of first common lines 32 may be disposed in each first wiring region 302, and it should be understood that the scan lines 31 and the first common lines 32 are disconnected from each other, that is: an orthogonal projection of the scan line 31 on the first substrate 30 does not overlap an orthogonal projection of the first common line 32 on the first substrate 30. It should be noted that, in the first wiring area 302, not only one row of the scan lines 31 and one row of the first common lines 32 are disposed, but also two rows of the scan lines 31 may be disposed, or the first common lines 32 may not be disposed, and so on, as the case may be. The embodiment of the disclosure is mainly described in terms of a row of scan lines 31 and a row of first common lines 32 disposed in each first wiring region 302.

As shown in fig. 5, at least one column of data lines 33 may be disposed in one second wiring region 303, in other words, at least one column of data lines 33 is disposed in each second wiring region 303, it should be understood that the data lines 33 as a whole may be regarded as extending in the column direction Y, and an orthogonal projection of the data lines 33 on the first substrate 30 overlaps with an orthogonal projection of the scan lines 31 and the first common lines 32 on the first substrate 30. The data line 33 may be connected to the second electrode 363 of the transistor 36 in the sub-pixel unit, and configured to provide the data signal to the sub-pixel unit.

For example, the data line 33 of the embodiment of the disclosure may be disposed in the same layer as the first pole 362 and the second pole 363 of the transistor 36 in the sub-pixel unit, that is: the mask can be manufactured by adopting the same composition process so as to reduce the mask cost; but is not limited thereto and may be fabricated using different patterning processes, as the case may be.

As shown in fig. 5, a row of data lines 33 may be disposed in each second wiring region 303, and the data lines 33 may be connected to the second poles 363 of the sub-pixel units in the same row, that is, the data lines 33 may provide data signals for the sub-pixel units in the same row.

In the embodiment of the present disclosure, each row of the data lines 33 may be symmetrically disposed about a central axis thereof, and it should be noted that the central axis mentioned herein is a line passing through the center of the data line 33 and extending in the row direction Y.

Alternatively, in a column of sub-pixel units, the first electrodes 362 of the sub-pixel units and the data lines 33 connected with the sub-pixel units are equally spaced in the row direction X, so as to ensure that the coupling capacitance between the transistors 36 of the sub-pixel units in each column and the data lines 33 is nearly uniform, and ensure uniformity of light efficiency at the sub-pixel units in each column. It should be noted that, while the first poles 362 of the sub-pixel units in a column of sub-pixel units and the data lines 33 connected to the first poles 362 are equally spaced in the row direction X, the overlapping area of the first poles 362 and the gate electrodes 361 in the column needs to be consistent with that in other columns.

As shown in fig. 5, the array substrate may further include a second common line 37, and the second common line 37 may be disposed at the same layer as the data line 33 and spaced apart from each other. The second common line 37 extends in the first direction Y, and a middle portion of an orthographic projection of the second common line 37 on the first substrate 30 is located in the first wiring region 302, and two ends of the second common line are respectively located in the sub-pixel regions 301. In the embodiment of the present disclosure, both ends of the second common line 37 are connected to the common electrodes 35 of the neighboring two sub-pixels in the first direction Y through the first via structures H1, respectively.

Alternatively, as shown in fig. 8, the first via structure H1 includes a first via portion H11, a second via portion H12, and a via connection portion H13, the via connection portion H13 is disposed at the same layer as and spaced apart from the pixel electrode 34, the via connection portion H13 is connected to the second common line 37 through the first via portion H11, and the via connection portion H13 is connected to the common electrode 35 through the second via portion H12.

In the embodiment of the present disclosure, as shown in fig. 5 to 7, the opposite substrate 4 may further include a second substrate 41, a spacer 42 on a side of the second substrate 41 close to the array substrate 3, and a shielding layer 40 on a side of the spacer 42 close to the second substrate 41. The specific structure of the second substrate 41 can refer to the description of the first substrate 30, and is not repeated herein; the orthographic projection of the shielding layer 40 on the first substrate 30 can completely cover the first wiring region 302, the second wiring region 303 and at least part of the sub-pixel region 30; the spacers 42 can be provided in plural, and the arrangement of the spacers 42 can improve the uniformity of the overall thickness of the display panel, and can improve the tolerance of the display panel to the fluctuation of liquid crystal molecules, thereby improving the yield of the display panel.

For example, the spacers 42 may include a main spacer and an auxiliary spacer, and when the display panel is not subjected to an external pressure, one end of the main spacer, which is far away from the second substrate 41, is in contact with the array substrate 3, which mainly plays a role in supporting; when the display panel is not subjected to external pressure, the end of the auxiliary spacer, which is far away from the second substrate 41, is spaced from the array substrate 1 by a certain distance, that is, a step difference (height difference) exists between the main spacer and the auxiliary spacer, and the thickness of the display panel can be finely adjusted by adjusting the step difference between the main spacer and the auxiliary spacer.

Illustratively, the height of the main spacer is greater than that of the auxiliary spacer, when the display panel is subjected to external pressure, the main spacer is firstly subjected to all pressure and compressed, and when the main spacer is compressed until the section difference between the main spacer and the auxiliary spacer is reduced to 0, the main spacer and the auxiliary spacer are subjected to the external pressure together.

It should be noted that the main spacer and the auxiliary spacer may be arranged according to a certain period. The size and height of different types of spacers are required to be monitored in the process of manufacturing. Because the size of the isolation pad is smaller, the number of main isolation pads is generally smaller, and the size of the main isolation pad is independent, the equipment is difficult to accurately identify the position of the main isolation pad, and the isolation pad which is vacant at a certain position around the main isolation pad is usually designed (i.e. no isolation pad is arranged) so as to conveniently, quickly and accurately identify the position of the main isolation pad and monitor the main isolation pad, for example: during design, no spacer is arranged below the main spacer, during monitoring, the position where no spacer is arranged can be quickly determined, and then the above mentioned design rule can make sure that the spacer at the position above which no spacer is arranged is the main spacer.

It should be noted that the surface of the spacer 42 close to the first substrate 30 in the embodiment of the disclosure may be a top surface, and the surface far from the first substrate 30 is a bottom surface, wherein, as shown in fig. 5, the orthographic projection of the top surface of the spacer 42 on the first substrate 30 is located in the orthographic projection of the scan line 31 on the first substrate 30, that is, the outer contour of the orthographic projection of the top surface of the spacer 42 on the first substrate 30 is located inside the outer contour of the orthographic projection of the scan line 31 on the first substrate 30, so as to ensure the flatness where the spacer 42 is supported, so as to ensure that the spacer 42 is stably supported on the array substrate 3. Note that the orthographic projection of the spacer 42 of the embodiment of the present disclosure on the first substrate 30 does not overlap with the orthographic projection of the data line 33 and the transistor on the first substrate 30.

It should be understood that the orthographic projection of the top surface of the spacer 42 on the first substrate 30 of the embodiment of the disclosure may be located within the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30, that is, the whole of the spacer 42 may be similar to a cone shape, but is not limited thereto, and the orthographic projection of the top surface of the spacer 42 on the first substrate 30 of the embodiment of the disclosure may also be completely coincident with the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30, as the case may be.

In addition, it should be noted that the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30 may be located within the orthographic projection of the scan line 31 on the first substrate 30, but is not limited thereto, and the outline of the spacer 42 in the column direction Y may exceed the outline of the scan line 31 in the column direction Y.

In order to prevent the occurrence of erythema caused by scratching the alignment film after the spacer 42 is moved by an external force, a retaining wall may be disposed around the spacer 42. Specifically, since the orthographic projection of the spacer 42 on the first substrate 30 is located in the orthographic projection of the scanning line 31 on the first substrate 30, and the scanning line 31 is covered by the shielding layer 40, even if the spacer 42 moves in the row direction X, the spacer is still located in the range covered by the shielding layer 40, and the display effect is not substantially affected; therefore, retaining walls do not need to be arranged on two opposite sides of the spacer 42 in the row direction X, so that the design difficulty is reduced.

In addition, as shown in fig. 5, transistors are disposed on two opposite sides of the spacer 42 in the row direction X, and the overall height of the region where the transistors are located in the array substrate 3 is greater than the overall height of the region where the spacer 42 is located, that is, the transistors can be used as a retaining wall to block the sliding of the spacer 42 in the row direction X.

In order to prevent the spacers 42 from sliding excessively in the column direction Y under the action of external force, as shown in fig. 5 and 6, a first retaining wall 38a and a second retaining wall 38b may be disposed on the array substrate 3, the first retaining wall 38a and the second retaining wall 38b are respectively located at two opposite sides of the scan line 31 in the column direction Y, wherein an orthographic projection of the spacers 42 on the first substrate 30 may be located between orthographic projections of the first retaining wall 38a and the second retaining wall 38b on the first substrate 30; in other words, the first retaining wall 38a and the second retaining wall 38b may be provided on opposite sides of the spacer 42 in the row direction Y.

It should be noted that at least a portion of the first retaining wall 38a and the second retaining wall 38b may be located in the sub-pixel region 301; the first wall 38a and the second wall 38b can be covered by a covering layer 40.

Each of the first and second blocking walls 38a and 38b includes a first blocking layer 381 disposed in the same layer as the scan line 31 and spaced apart from each other, and a second blocking layer 382 disposed in the same layer as the data line 33 and spaced apart from each other, and an orthographic projection of the second blocking layer 382 on the first substrate 30 overlaps with an orthographic projection of the first blocking layer 381 on the first substrate; as shown in fig. 5 to 7, a distance between the first barrier layer 381 and the scan line 31 in the first direction Y is a first distance W1, a distance between the second barrier layer 382 and the scan line 31 in the first direction Y is a second distance W2, and the second distance W2 is greater than the first distance W1; that is, the first barrier layer 381 is protruded toward the direction of the spacer 42 compared with the second barrier layer 382, and the protruded portion can play a supporting role when the spacer is forced to move, so as to alleviate the situation that the spacer 42 falls into the gap between the scan line 31 and the first barrier layer 381 and cannot be restored to the original state; meanwhile, in the embodiment of the present disclosure, the distance between the second barrier layer 382 and the spacer 42 is larger than the distance between the first barrier layer 381 and the spacer 42, so that compared with a scheme in which the distance between the second barrier layer 382 and the spacer 42 is designed to be equal to the distance between the first barrier layer 381 and the spacer 42, when the external stress applied to the spacer 42 is the same, the tilting angle of the spacer 42 can be reduced, so that when the external stress applied to the spacer 42 is a force in the horizontal direction (e.g., the first direction Y), the resistance in the vertical direction (i.e., the thickness direction of the display panel) can be reduced, and at this time, the spacer 42 is more difficult to cross the retaining wall to scratch the alignment film at the transparent region (i.e., the region not covered by the shielding layer 40 in the sub-pixel region 301), that is: the risk of scratching the alignment film is reduced. In addition, the vertical deformation of the display panel is reduced, and T-DNU (Touch-Dark Non-uniformity, uneven Dark state of the Touch panel) is improved.

It should be noted that the surface of the spacer 42 close to the first substrate 30 in the embodiment of the disclosure may be a top surface, and the dimension W4 of the top surface of the spacer 42 in the first direction Y may be larger than the first distance W1, so as to alleviate the situation that the spacer 42 falls into the gap between the scan line 31 and the first barrier layer 381 during the moving process and cannot be recovered.

Optionally, the ratio between the dimension W4 of the top surface of the spacer 42 in the first direction Y and the first spacing W1 is greater than or equal to 2, so as to further alleviate the problem that the spacer 42 falls into the gap between the scan line 31 and the first barrier layer 381 during the movement and cannot be restored to the original state.

The distance between the second barrier layer 382 and the spacer 42 in the first direction Y is a third distance W3, and the ratio between the third distance W3 and the dimension of the top surface of the spacer 42 in the first direction Y is greater than or equal to 0.5, so that the risk that the spacer 42 crosses the retaining wall can be reduced, and the risk of scratching the alignment film at the light-transmitting area can be reduced; further, a ratio between the third pitch W3 and the dimension W4 of the top surface of the spacer 42 in the first direction Y may be 1 or more.

For example, the ratio between the third distance W3 and the size of the data line 33 in the second direction X is 2 to 4; among them, the size of the data line 33 in the second direction X may be 5 μm to 7 μm, such as: 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, etc., in which case the third pitch W3 may be 10 μm to 28 μm, such as: 10 μm, 13 μm, 17 μm, 21 μm, 25 μm, 28 μm, and the like.

It should be understood that the aforementioned orthographic projection of the second barrier layer 382 on the first substrate 30 is located in the orthographic projection of the first barrier layer 381 on the first substrate 30, so as to ensure that the film layer (i.e., the second barrier layer 382) mainly functioning as a barrier in the first retaining wall 38a and the second retaining wall 38b has a sufficient width in the first direction Y to better block the sliding of the spacer 42 in the first direction Y; that is, as shown in fig. 7, the longitudinal section of the first retaining wall 38a and the second retaining wall 38b of the embodiment of the present disclosure may look "L" as a whole, where the longitudinal section refers to a plane parallel to the thickness direction of the display panel and the first direction Y.

It should be noted that the aforementioned first blocking layer 381 of the second blocking wall 38b may be a partial structure of the first common line 32. It should be further noted that the first spacing W1 between the second blocking wall 38b and the scan line 31, the second spacing W2, the third spacing W3 between the second blocking wall 38b and the spacer 42, and the first spacing W1 between the first blocking wall 38a and the scan line 31, the second spacing W2, and the third spacing W3 between the first blocking wall 38a and the spacer 42 may be equal or unequal, as the case may be.

In the embodiment of the present disclosure, the aforementioned shielding layer 40 may cover part of the sub-pixel region 301, and specifically may cover part of the common electrode 35 and part of the pixel electrode 34, in addition to completely covering the first wiring region 302 and the second wiring region 303. Coupling electric fields exist in the areas, close to the scanning lines 31 and the data lines 33, of the edges of the pixel electrodes 34, and therefore, in the display process, the liquid crystal arrangement is disordered, a failure area is generated, and light leakage occurs at the edges of dark-state pixels, so that the failure area needs to be shielded by the shielding layer 40.

For example, there is a coupling electric field between the pixel electrode 34 and the scan line 31, that is, there is a failure region in a portion of the pixel electrode 34 close to the scan line 31, in order to shield the failure region, the shielding layer 40 can cover at least 5um of the edge of the pixel electrode 34 in the column direction Y, and it should be noted that, when the color film layer is located on the opposite substrate, the width needs to be increased more in consideration of the accuracy of the upper and lower substrates to the cell, but the width should not exceed 10 μm, so as to avoid affecting the pixel aperture ratio too much.

In addition, the data line 33 and the pixel electrode 34 also have a coupling electric field at their edges, that is, the portion of the pixel electrode 34 close to the data line 33 in the embodiment of the disclosure has a failure area; wherein, when the liquid crystal molecules 5 are negative liquid crystal molecules, the electric field does not cause the liquid crystal to rotate, the shielding layer 40 can cover the edge of the pixel electrode 34 by about 1 μm to shield the Shadow region near the data line 33; if the liquid crystal molecules 5 are positive liquid crystal molecules, the coupling electric field between the data line 33 and the pixel electrode 34 will not cause significant dark state light leakage, but will cause Crosstalk phenomenon to be aggravated, and at this time, the shielding layer 40 may cover at least 6um of the edge of the pixel electrode 34 to shield the coupling electric field area.

It should be noted that the color film layer used in the liquid crystal display panel may be located on the opposite substrate 4, or may be located on the array substrate 3, as the case may be.

Based on the above, the liquid crystal display panel of the embodiment of the present disclosure may be used in a display product with 4K resolution or 8K resolution.

Embodiments of the present disclosure also provide an electronic device including the display panel described in any of the above embodiments.

According to the embodiments of the present disclosure, the specific type of the electronic device is not particularly limited, and any electronic device commonly used in the art may be used, and specific examples include a mobile device such as a liquid crystal display, a mobile phone, a notebook computer, etc., a wearable device such as a watch, a VR device, etc., and those skilled in the art may select the electronic device according to the specific application of the display device, which is not described herein again.

It should be noted that the electronic device includes other necessary components and components besides the display panel, for example, the display may further include a backlight module, a housing, a main circuit board, a power line, and the like, which can be supplemented correspondingly according to the specific requirements of the electronic device, and will not be described herein again.

It is noted that references herein to "on … …", "formed on … …" and "disposed on … …" can mean that one layer is formed or disposed directly on another layer or that one layer is formed or disposed indirectly on another layer, i.e., there is another layer between the two layers.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another.

In the present disclosure, unless otherwise specified, the term "disposed on the same layer" is used to mean that two layers, components, members, elements or portions can be formed by the same patterning process, and the two layers, components, members, elements or portions are generally formed of the same material.

In the present disclosure, unless otherwise specified, the expression "patterning process" generally includes the steps of coating, exposing, developing, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel characterized by comprising an array substrate (3) and an opposed substrate (4) provided to a cell:

the array substrate (3) comprises a first substrate (30), and a scanning line (31), a data line (33), a first retaining wall (38a) and a second retaining wall (38b) which are formed on one side of the first substrate (30) close to the opposite substrate (4); the data lines (33) extend in a first direction (Y), the scan lines (31) extend in a second direction (X), and the first direction (Y) intersects the second direction (X); the first retaining wall (38a) and the second retaining wall (38b) are respectively located on two opposite sides of the scanning line (31) in the first direction (Y), the first retaining wall (38a) and the second retaining wall (38b) each include a first barrier layer (381) which is arranged in the same layer as the scanning line (31) and is spaced from each other and a second barrier layer (382) which is arranged in the same layer as the data line (33) and is spaced from each other, and an orthographic projection of the second barrier layer (382) on the first substrate (30) is overlapped with an orthographic projection of the first barrier layer (381) on the first substrate (30); a spacing between the first barrier layer (381) and the scan line (31) in the first direction (Y) is a first spacing (W1), a spacing between the second barrier layer (382) and the scan line (31) in the first direction (Y) is a second spacing (W2), and the second spacing (W2) is greater than the first spacing (W1);

the opposite substrate (4) comprises a second substrate (41) and a spacer (42) positioned on one side of the second substrate (41) close to the array substrate (3), the surface of the spacer (42) close to the first substrate (30) is a top surface, and the orthographic projection of the top surface of the spacer (42) on the first substrate (30) is positioned in the orthographic projection of the scanning line (31) on the first substrate (30) and between the orthographic projection of the first retaining wall (38a) and the orthographic projection of the second retaining wall (38b) on the first substrate (30); and a dimension (W4) of a top surface of the spacer (42) in the first direction (Y) is greater than the first pitch (W1).

2. The display panel according to claim 1, wherein a ratio between a dimension (W4) of a top surface of the spacer (42) in the first direction (Y) and the first pitch (W1) is 2 or more.

3. The display panel according to claim 2, wherein the second barrier layer (382) is spaced from the spacer (42) in the first direction (Y) by a third spacing (W3), and a ratio between the third spacing (W3) and a dimension (W4) of the top surface of the spacer (42) in the first direction (Y) is 0.5 or more.

4. The display panel according to claim 3, wherein a ratio between the third pitch (W3) and a dimension (W4) of the top surface of the spacer (42) in the first direction (Y) is 1 or more.

5. A display panel as claimed in claim 3 characterized in that the ratio between the third pitch (W3) and the dimension of the data line (33) in the second direction (X) is 2 to 4.

6. A display panel according to any of claims 1 to 5, characterized in that the orthographic projection of the second barrier layer (382) on the first substrate (30) is within the orthographic projection of the first barrier layer (381) on the first substrate (30), and the first direction (Y) is perpendicular to the second direction (X).

7. The display panel according to claim 6, wherein the array substrate (3) further comprises a first common line (32) formed on the first substrate (30) and extending in the second direction (X), the first common line (32) being disposed at the same layer as and spaced apart from the scan line (31);

wherein the first blocking layer (381) of the second retaining wall (38b) is a partial structure of the first common line (32).

8. The display panel according to claim 7, wherein the array substrate (3) further comprises a plurality of sub-pixel units arranged in an array on the first substrate (30) along the second direction (X) and the first direction (Y);

each of the sub-pixel units includes a pixel electrode (34), a common electrode (35), and a transistor (36): the transistor (36) includes a gate electrode (361), a first electrode (362), and a second electrode (363), the gate electrode (361) being connected to the scanning line (31), the first electrode (362) being connected to the pixel electrode (34), and the second electrode (363) being connected to the data line (33);

an orthographic projection of the common electrode (35) on the first substrate (30) overlaps with an orthographic projection of the pixel electrode (34) on the first substrate (30), and the common electrode (35) is connected with the first common line (32).

9. The display panel according to claim 8, wherein the pixel electrode (34) is located on a side of the common electrode (35) away from the first substrate (30), the pixel electrode (34) comprising:

a first electrode portion (20) including a first connecting strip (201) extending in the first direction (Y) and a plurality of first electrode strips (202) arranged at intervals in the first direction (Y), the first connecting strip (201) having a first side (201a) and a second side (201b) opposite to each other in the second direction (X), the plurality of first electrode strips (202) being located on the first side (201a) of the first connecting strip (201) and connected to the first connecting strip (201), and ends of adjacent first electrode strips (202) far from the first connecting strip (201) being open;

a second electrode portion (21) spaced apart from the first electrode portion (20) in the first direction (Y), the second electrode portion (21) including a second connection bar (211) extending in the first direction (Y) and a plurality of second electrode bars (212) spaced apart in the first direction (Y), the second connection bar (211) being located at a position on the first side (201a) away from the second side (201b), the second connection bar (211) having a third side (211a) and a fourth side (211b) opposite to each other in the second direction (X), the third side (211a) being located at a position on the fourth side (211b) close to the first side (201 a); the plurality of second electrode strips (212) are positioned on the third side (211a) of the second connecting strip (211) and connected with the second connecting strip (211), and the ends of the adjacent second electrode strips (212) far away from the second connecting strip (211) are in an open shape;

a conductive connection part (22) located between the first electrode part (20) and the second electrode part (21), both ends of the conductive connection part (22) being connected to the first connection bar (201) and the second connection bar (211), respectively; and the area of the conductive connection part (22) is larger than the area of the first electrode bar (202) and the area of the second electrode bar (212).

10. The display panel according to claim 9, wherein the conductive connection portion (22) comprises a first conductive connection bar (221) and a second conductive connection bar (222) arranged at intervals in the second direction (X) and each extending in the first direction (Y), and at least two third conductive connection bars (223) located between the first conductive connection bar (221) and the second conductive connection bar (222) and arranged at intervals in the first direction (Y), wherein two ends of each third conductive connection bar (223) are respectively connected with the first conductive connection bar (221) and the second conductive connection bar (222);

wherein the first conductive connecting strip (221) is connected with the first connecting strip (201), and the second conductive connecting strip (222) is connected with the second connecting strip (211).

11. The display panel according to claim 10, wherein the first electrode stripes (202), the second electrode stripes (212) and the third conductive connecting stripes (223) all extend in a third direction (Q), and the first widths of the first electrode stripes (202), the second electrode stripes (212) and the third conductive connecting stripes (223) are equal;

wherein the first width is a dimension in a fourth direction (P), the third direction (Q) is perpendicular to the fourth direction (P), and the third direction (Q) intersects the first direction (Y) and the second direction (X).

12. The display panel according to claim 9, wherein the array substrate (3) further comprises: and second common lines (37) disposed at the same layer as the data lines (33) and spaced apart from each other, the second common lines (37) extending in the first direction (Y), and both ends of the second common lines (37) being connected to the common electrodes (35) of two adjacent sub-pixel units in the first direction (Y) through first via structures (H1), respectively.

13. The display panel of claim 12, wherein the first via structure (H1) comprises a first via portion (H11), a second via portion (H12), and a via connection portion (H13), the via connection portion (H13) is disposed at the same layer as the pixel electrode (34) and spaced apart from the pixel electrode, the via connection portion (H13) is connected to the second common line (37) through the first via portion (H11), and the via connection portion (H13) is connected to the common electrode (35) through the second via portion (H12).

14. An electronic device characterized by comprising the display panel according to any one of claims 1 to 13.