CN214337888U - Double-charge-pump phase-locked loop - Google Patents
Double-charge-pump phase-locked loop Download PDFInfo
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- CN214337888U CN214337888U CN202120483566.XU CN202120483566U CN214337888U CN 214337888 U CN214337888 U CN 214337888U CN 202120483566 U CN202120483566 U CN 202120483566U CN 214337888 U CN214337888 U CN 214337888U
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Abstract
The utility model discloses a two charge pump phase-locked loops, include: a phase frequency detector; an integrating charge pump; a proportional charge pump; a PMOS tube; a frequency divider; a current controlled oscillator; the phase frequency detector comprises a phase frequency detector, a PMOS tube, a current control oscillator, a frequency divider, a proportional charge pump, a PMOS tube, a current control oscillator, a frequency divider and a phase frequency detector, wherein the output end of the phase frequency detector is connected with the integral charge pump and the proportional charge pump respectively, the integral charge pump is connected with the proportional charge pump in parallel, the integral charge pump is connected with the PMOS tube, the PMOS tube is connected with the current control oscillator, the current control oscillator is connected with one end of the frequency divider, and the other end of the frequency divider is connected with one input end of the phase frequency detector. The phase-locked loop can control the phase-locked loop to effectively control the zero frequency and adjust the zero frequency in a diversified manner through the connection structure of the current-controlled oscillator and the two charge pumps, and the flexibility of signal processing of the phase-locked loop is improved.
Description
Technical Field
The utility model relates to a circuit field, in particular to phase-locked loop of two charge pumps.
Background
At present, a common phase-locked loop is a single-charge-pump phase-locked loop, a low-pass filter is realized by a resistor capacitor, and a zero point or a pole of the phase-locked loop is determined by the resistor capacitor and is not easy to adjust, so that when the output frequency signal range is very wide, and the value of a feedback frequency divider is greatly changed, the stability and the equivalent effect of the loop are poor, and the condition that the final output signal quality is poor or even cannot be locked is caused.
SUMMERY OF THE UTILITY MODEL
The utility model discloses one of them utility model aims at providing a phase-locked loop of two charge pumps, the phase-locked loop can be through the connection structure control phase-locked loop of current-controlled oscillator and two charge pumps, and effective control zero frequency and pluralism adjust zero frequency, improve phase-locked loop signal processing's flexibility.
The utility model discloses one of them utility model aims at providing a phase-locked loop of double charge pump, the phase-locked loop of traditional single charge structure is compared to the phase-locked loop, the utility model discloses a voltage to the signal conversion of electric current is realized to the transconductance of PMOS pipe, realizes the stability of signal through a plurality of wave filters to can the stable control phase-locked loop's zero frequency.
In order to realize at least more than one utility model purpose, the utility model discloses further provide a two charge pump phase-locked loops, include:
a phase frequency detector;
an integrating charge pump;
a proportional charge pump;
a PMOS tube;
a frequency divider;
a current controlled oscillator;
the phase frequency detector comprises a phase frequency detector, a PMOS tube, a current control oscillator, a frequency divider, a proportional charge pump, a PMOS tube, a current control oscillator, a frequency divider and a phase frequency detector, wherein the output end of the phase frequency detector is connected with the integral charge pump and the proportional charge pump respectively, the integral charge pump is connected with the proportional charge pump in parallel, the integral charge pump is connected with the PMOS tube, the PMOS tube is connected with the current control oscillator, the current control oscillator is connected with one end of the frequency divider, and the other end of the frequency divider is connected with one input end of the phase frequency detector.
According to the utility model discloses one of them preferred embodiment, integrated charge pump one end is connected the PMOS pipe, the PMOS pipe includes grid, source electrode and drain electrode, wherein the one end of integrated charge pump is connected to the grid, first electric capacity is connected to the source electrode, the drain electrode is connected the current control oscillator.
According to another preferred embodiment of the present invention, one end of the first capacitor is connected to the gate, and the other end of the first capacitor is connected to the source.
According to another preferred embodiment of the present invention, the current controlled oscillator comprises a plurality of inverters, and the plurality of inverters are connected in series with each other.
According to another preferred embodiment of the present invention, the plurality of inverters each have an input and an output, the inverter inputs include a first inverter input and a second inverter input, the integrating charge pump and the proportional charge pump each have an output and an input, wherein the output of the proportional charge pump is connected to the first input of the plurality of inverters.
According to another preferred embodiment of the present invention, the first input ends of the plurality of phase inverters are connected to one end of the second capacitor for filtering at the input ends of the phase inverters.
According to another preferred embodiment of the present invention, the output terminals of the plurality of phase inverters are connected to the second input terminal of the phase inverter and are simultaneously connected to one end of the frequency divider.
According to another preferred embodiment of the present invention, the second capacitor is grounded.
According to another preferred embodiment of the present invention, the input terminal of the phase frequency detector is connected to the crystal resonator.
Drawings
Fig. 1 shows a schematic structural diagram of a dual charge pump phase-locked loop of the present invention.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents and other technical solutions without departing from the spirit and scope of the invention.
It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in a generic and descriptive sense only and not for purposes of limitation, as the terms are used in the description to indicate that the referenced device or element must have the specified orientation, be constructed and operated in the specified orientation, and not for the purpose of limitation.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
Referring to fig. 1, the present invention discloses a structure of a dual charge pump phase-locked loop, wherein the phase-locked loop employs an integrating charge pump and a proportional charge pump, and inputs the input voltage signals of the two charge pumps into a current control oscillator after converting the input voltage signals into current signals, so as to realize the multi-path signal control of the phase-locked loop, and improve the flexibility of signal control.
Specifically, referring to fig. 1, the phase-locked loop includes: a Phase Frequency Detector (PFD); an integral charge pump (integral charge pump); a proportional charge pump (proportional charge pump); a PMOS tube; frequency dividers (dividers); a Current Controlled Oscillator (CCO); one end of the phase frequency detector is connected with the input end of the integrated charge pump and the input end of the proportional charge pump respectively, the other end of the phase frequency detector is connected with a crystal resonator (Fref), the integrated charge pump and the proportional charge pump are connected in parallel, the output end of the integrated charge pump is connected with a PMOS (P-channel metal oxide semiconductor) tube, the PMOS tube comprises a grid electrode, a source electrode and a drain electrode, the output end of the integrated charge pump is connected with the grid electrode of the PMOS tube, the source electrode of the PMOS tube is connected with one end of a first capacitor C1, the drain electrode of the PMOS tube is connected with the current control oscillator, the output end of the integrated charge pump is connected with the other end of the first capacitor C1, and one end of the source electrodes of the first capacitor and the PMOS tube is connected with a power supply.
The output of proportion charge pump is connected the current control oscillator, the current control oscillator has a plurality of inverters, and every inverter has first input and second input, wherein the first input of every inverter with the drain electrode of PMOS pipe is connected, and the first input of every inverter with the output of proportion charge pump is connected, and every inverter still includes the output, the output of every inverter with the second input is connected, and the output of every inverter in the lump with the one end of frequency divider is connected, the other end of frequency divider is connected the input of phase frequency detector. The input end of each inverter is also connected with one end of a second capacitor C2, and the other end of the second capacitor C2 is grounded.
In order to better explain the technical effects of the utility model, the utility model discloses a provide a signal control method on the basis based on structure:
the output voltage signal A of the phase frequency detector is used for outputting current icp _ int through an integral charge pump, further inputting the current icp _ int to a first capacitor C1, and obtaining a small-signal voltage signal icp _ int (1/sc1), wherein 1/sc1 is an alternating current impedance parameter according to the attribute of the first capacitor C1, C1 is the size of the first capacitor, the voltage signal icp _ int (1/sc1) is input into a PMOS tube MP1, and is converted into current icp _ int (1/sc1) 1 through transconductance in the PMOS tube MP1, and gm1 is a transconductance parameter in the PMOS tube MP 1. An output voltage signal A of the phase frequency detector outputs current icp _ prop after passing through a proportional charge pump, and current icp _ int (1/sc1) gm1 after transconductance conversion in a PMOS tube MP1 and output current icp _ prop after passing through the proportional charge pump are input into a Current Control Oscillator (CCO) together for conversion so as to generate a final combined transfer function of the charge pump and the CCO: h ═ (icp _ int (1/sc1) × gm1+ icp _ prop) (kvco/s), where kvco/s is the switching parameter of the current controlled oscillator, the final joint transfer function H can be expressed in terms of: h ═ is (icp _ prop + icp _ int gm1 × 1/sc1) × (kvco/s), wherein zero point frequency w ═ is (icp _ int × gm1)/(c1 × icp _ prop), that is to say, through the utility model discloses a control to zero point frequency can effectively be realized to the structural setting, improves the flexibility of the control of phase-locked loop.
It is understood by those skilled in the art that the embodiments of the present invention as described above and shown in the drawings are given by way of example only and are not limiting of the present invention, the objects of which have been fully and effectively achieved, the functions and structural principles of which have been shown and described in the embodiments, and that the embodiments of the present invention may be modified or adapted without departing from said principles.
Claims (9)
1. A dual charge pump phase locked loop, comprising:
a phase frequency detector;
an integrating charge pump;
a proportional charge pump;
a PMOS tube;
a frequency divider;
a current controlled oscillator;
the phase frequency detector is characterized in that the output end of the phase frequency detector is connected with the integrating charge pump and the proportional charge pump respectively, the integrating charge pump is connected with the proportional charge pump in parallel, the integrating charge pump is connected with the PMOS pipe, the PMOS pipe is connected with the current control oscillator, the current control oscillator is connected with one end of the frequency divider, and the other end of the frequency divider is connected with the input end of the phase frequency detector.
2. The dual-charge-pump phase-locked loop of claim 1, wherein one end of the integrated charge pump is connected to the PMOS transistor, the PMOS transistor comprises a gate, a source and a drain, wherein the gate is connected to one end of the integrated charge pump, the source is connected to the first capacitor, and the drain is connected to the current-controlled oscillator.
3. A dual charge pump pll as claimed in claim 2, wherein one end of said first capacitor is connected to said gate and the other end of said first capacitor is connected to said source.
4. A dual charge pump phase locked loop as claimed in claim 2, wherein said current controlled oscillator comprises a plurality of inverters, said plurality of inverters being connected in series with each other.
5. A dual charge pump phase locked loop as claimed in claim 4, wherein said plurality of inverters each have an input and an output, said inverter inputs including an inverter first input and an inverter second input, said integrating charge pump and proportional charge pump each having an output and an input, and wherein said proportional charge pump has an output coupled to said plurality of inverter first inputs.
6. A dual charge pump PLL according to claim 5, wherein said plurality of inverter first inputs are connected together at one end of a second capacitor for filtering of the inverter inputs.
7. A dual charge pump phase locked loop as claimed in claim 5, wherein the outputs of said plurality of inverters are connected to the second input of said inverter and are simultaneously connected together to one terminal of said frequency divider.
8. A dual charge pump phase locked loop as claimed in claim 6, wherein said second capacitor is connected to ground.
9. A dual charge pump phase locked loop as claimed in claim 1, wherein the phase frequency detector input is connected to the crystal resonator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120483566.XU CN214337888U (en) | 2021-03-05 | 2021-03-05 | Double-charge-pump phase-locked loop |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120483566.XU CN214337888U (en) | 2021-03-05 | 2021-03-05 | Double-charge-pump phase-locked loop |
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| Publication Number | Publication Date |
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| CN214337888U true CN214337888U (en) | 2021-10-01 |
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| CN202120483566.XU Active CN214337888U (en) | 2021-03-05 | 2021-03-05 | Double-charge-pump phase-locked loop |
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2021
- 2021-03-05 CN CN202120483566.XU patent/CN214337888U/en active Active
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Address after: 311422 4th floor, building 9, Yinhu innovation center, 9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee after: Zhejiang Xinmai Microelectronics Co.,Ltd. Address before: 311400 4th floor, building 9, Yinhu innovation center, No.9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee before: Hangzhou xiongmai integrated circuit technology Co.,Ltd. |