CN214337887U

CN214337887U - Signal level conversion circuit

Info

Publication number: CN214337887U
Application number: CN202022938683.9U
Authority: CN
Inventors: 徐万芝; 何俐鹏; 王敏
Original assignee: Shenzhen Weimu Technology Co ltd
Current assignee: Hangzhou Vmhstar Technology Co ltd
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2021-10-01
Anticipated expiration: 2030-12-10

Abstract

The utility model discloses a signal level converting circuit, including triode Q1, first power and second power, triode Q1's base is connected to the feed end of second power through resistance R1, be connected with resistance R2 between triode Q1's base and the projecting pole, triode Q1's collecting electrode is connected to the feed end of first power through resistance R3, the supply voltage of first power is higher than the supply voltage of second power, triode Q1's collecting electrode is signal input part, triode Q1's transmission is signal output part. The design of the utility model is simple and practical, the chip scheme is not used, the cost is low, and the cost control of the product is facilitated; the devices required by level conversion are relatively few, and PCB layout and routing are facilitated; it is suitable for various communication application environments and has high frequency response speed.

Description

Signal level conversion circuit

Technical Field

The utility model relates to a circuit level transition technical field especially relates to a signal level transition circuit.

Background

At present, the application environment of a circuit board is more and more complex, the functional requirements are more and more, a plurality of level signals often exist in a system, and especially when the signal level of a single chip microcomputer is not matched with the signal level of a peripheral circuit, the level of the signal needs to be converted.

The traditional high level is simpler to convert into the low level, and the simplest mode is to construct a voltage division circuit and convert the high level into the low level through resistance voltage division; however, when the low level is converted into the high level, because the boost circuit is not convenient to construct, a power conversion chip is added in the circuit in the conventional mode, and internal conversion of the level signal is realized through chip processing.

Level signals are converted through the power conversion chip, stability is good, efficiency is high, cost is high, peripheral circuits needed by partial conversion chips are many, layout and wiring difficulty of a PCB is increased, and certain difficulty exists in design and cost management and control.

SUMMERY OF THE UTILITY MODEL

The utility model provides a signal level converting circuit is in order to solve above-mentioned technical problem.

In order to achieve the above purpose, the utility model discloses the technical scheme who adopts is:

the utility model provides a signal level converting circuit, includes triode Q1, first power and second power, triode Q1's base is connected to the feed end of second power through resistance R1, is connected with resistance R2 between triode Q1's base and the projecting pole, and triode Q1's collecting electrode is connected to the feed end of first power through resistance R3, the supply voltage of first power is higher than the supply voltage of second power, and triode Q1's collecting electrode is signal input part, and triode Q1's emitting electrode is signal output part.

Preferably, the power supply voltage of the first power supply is 5V, and the power supply voltage of the second power supply is 3.3V.

Preferably, a capacitor C1 is connected between the base and the collector of the transistor Q1.

Compared with the prior art, the design idea of the utility model is simple and practical, a chip scheme is not used, the cost is low, and the cost management and control of the product are facilitated; the devices required by level conversion are relatively few, and PCB layout and routing are facilitated; it is suitable for various communication application environments and has high frequency response speed.

Drawings

Fig. 1 is a circuit diagram of the signal level conversion circuit of the present invention.

Detailed Description

The present invention will be described in detail below with reference to specific embodiments shown in the drawings. However, these embodiments are not intended to limit the present invention, and structural, methodical, or functional changes that may be made by one of ordinary skill in the art based on these embodiments are all included in the scope of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

As shown in fig. 1, a signal level converting circuit includes a transistor Q1, a first power supply and a second power supply, a base of the transistor Q1 is connected to a power supply terminal of the second power supply through a resistor R1, a resistor R2 is connected between the base and an emitter of the transistor Q1, a collector of the transistor Q1 is connected to the power supply terminal of the first power supply through a resistor R3, a power supply voltage of the first power supply is higher than a power supply voltage of the second power supply, the collector of the transistor Q1 is a signal input terminal (DO), and the emitter of the transistor Q1 is a signal output terminal (MCU _ DO).

Here, the supply voltage of the first power supply may be selected to be 5V, and the supply voltage of the second power supply may be selected to be 3.3V, thereby being used for the conversion of the common levels of 3.3V and 5V.

In order to make the circuit more stable, a capacitor C1 may be connected between the base and the collector of the transistor Q1.

The utility model discloses a signal input part can connect outside IO data receiver, and single chip microcomputer IO mouth can be connected to signal output part. The signal input end (DO) is connected with a collector of a triode Q1 and is pulled up by a +5V0 power supply (the output voltage is 5V); the signal output end (MCU _ DO) is connected with the emitting electrode of the triode Q1, and the +3V3 power supply (the output voltage is 3.3V) is connected with the base electrode of the triode Q1 through resistance voltage division and serves as a switch control end.

When the signal of the signal output end (MCU _ DO) is at a high level, the base voltage of the triode Q1 is lower than the emitter voltage thereof, the triode Q1 is cut off, and the signal of the signal input end (DO) is pulled up to a high level by a +5V0 power supply; when the signal of the signal output end (MCU _ DO) is at a low level, the base voltage of the triode Q1 is higher than the emitter voltage thereof, the triode Q1 is conducted, the signal of the signal input end (DO) is consistent with the signal output end (MCU _ DO) and is at a low level, so that the level conversion from a 3.3V signal to a 5V signal is realized, and the high-low level time sequence is kept consistent.

Because the switching response frequency of triode is very high, the utility model discloses the switch tube that generally adopts is NPN type triode. Of course, a similar signal level conversion circuit formed by other switching tubes, such as MOS tubes, may also be built.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. The utility model provides a signal level switching circuit, characterized in that, includes triode Q1, first power and second power, triode Q1's base is connected to the feed end of second power through resistance R1, is connected with resistance R2 between triode Q1's base and the projecting pole, and triode Q1's collecting electrode is connected to the feed end of first power through resistance R3, the supply voltage of first power is higher than the supply voltage of second power, and triode Q1's collecting electrode is signal input part, and triode Q1's projecting pole is signal output part.

2. The signal level shifting circuit of claim 1, wherein the supply voltage of the first power supply is 5V and the supply voltage of the second power supply is 3.3V.

3. The signal level shifter circuit as claimed in claim 1, wherein a capacitor C1 is connected between the base and the collector of the transistor Q1.