CN214311720U - Media interface controller with enhanced drive capability - Google Patents
Media interface controller with enhanced drive capability Download PDFInfo
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- CN214311720U CN214311720U CN202022942233.7U CN202022942233U CN214311720U CN 214311720 U CN214311720 U CN 214311720U CN 202022942233 U CN202022942233 U CN 202022942233U CN 214311720 U CN214311720 U CN 214311720U
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Abstract
A media interface controller with enhanced drive capabilities is provided. The media interface controller comprises a plurality of channel circuits, wherein the channel circuits are used for coupling NVM channels; each channel circuit comprises a channel driver and a channel pin, wherein the channel driver is used for exchanging electric signals with the NVM channel through the channel pin; the media interface controller includes a first switch that couples the channel driver of the second channel circuit to the channel pin of the first channel circuit such that the channel driver of the first channel and the channel driver of the second channel cooperatively drive the channel pin of the first channel.
Description
Technical Field
The present application relates to chip technology, and in particular, to a memory control chip or media interface controller with enhanced drive capabilities.
Background
Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103, a control section 104, one or more NVM (Non-Volatile Memory) chips 105, and a DRAM (Dynamic Random Access Memory) 110.
NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.
The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in a variety of ways including software, hardware, firmware, or a combination thereof. The control unit 104 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. The data of FTL (flash Translation layer) table and/or the cached IO command can be stored in the DRAM.
Optionally, the storage device further comprises a firmware memory. The control unit 104 loads firmware from the firmware memory at runtime. Firmware memory is, for example, NOR flash, ROM, EEPROM, and may also be part of NVM chip 105.
The control component couples the plurality of NVM chips through a plurality of channels (NVM channels). The control component provides a pin for each channel to couple the signal lines of the channel. The pin count of the control component is significantly related to cost and cannot be changed after the control component is manufactured. The number of channels in turn limits the number of NVM chips that the controller can couple to, which in turn limits the storage capacity and data access bandwidth of the memory device. The channels are in parallel, and the control unit is able to access the NVM chip of one channel without being affected by the data transmission of the other channels.
As the number of channels increases, the number of NVM chips or DIEs (DIE) coupled on a channel increases, and the frequency of accessing NVM chips increases, the power consumed by multiple channels increases, which presents challenges to the power supply of control components and challenges to the driving capability of each channel. Reducing the frequency of signal transmission on a channel, reducing the number of channels or dies coupled to a channel, is a major means to overcome the driving capability challenge, but this in turn limits the performance of the control components and the capacity of the memory device.
SUMMERY OF THE UTILITY MODEL
It is desirable to solve the problem of insufficient driving capability of the control unit that accompanies an increase in the number of channels, an increase in the number of NVM chips or DIEs (DIE) coupled on a channel, and an increase in the frequency of accessing the NVM chips.
According to a first aspect of the present application, there is provided a first media interface controller according to the first aspect of the present application, comprising a plurality of channel circuits for coupling NVM channels; each channel circuit comprises a channel driver and a channel pin, wherein the channel driver is used for exchanging electric signals with the NVM channel through the channel pin; the media interface controller includes a first switch that couples the channel driver of the second channel circuit to the channel pin of the first channel circuit such that the channel driver of the first channel and the channel driver of the second channel cooperatively drive the channel pin of the first channel.
According to the first media interface controller of the first aspect of the present application, there is provided the second media interface controller of the first aspect of the present application, further comprising a second switch, where the first switch couples the channel driver of the fourth channel circuit to the channel pin of the third channel circuit, so that the channel driver of the third channel and the channel driver of the fourth channel drive the channel pin of the third channel together.
The third media interface controller according to the first aspect of the present application is provided according to the first or second media interface controller of the first aspect of the present application, further comprising a third switch coupling the channel driver of the fifth channel circuit to the channel pin of the first channel circuit, such that the channel driver of the first channel, the channel driver of the second channel and the driver of the fifth channel drive the channel pin of the first channel together.
According to one of the first to third media interface controllers of the first aspect of the present application, there is provided the fourth media interface controller of the first aspect of the present application, wherein the first switch further disconnects the coupling of the channel driver of the second channel circuit with the channel pin of the second channel circuit.
According to one of the first to fourth media interface controllers of the first aspect of the present application, there is provided the fifth media interface controller of the first aspect of the present application, wherein each channel further comprises a channel transmit/receive unit coupled with a corresponding channel driver; the media interface controller further comprises a first switch for the channel transmit/receive unit; the first switch for the channel transmit/receive unit couples the channel transmit/receive unit of the first channel to the channel driver of the second channel such that the signal output by the channel transmit/receive unit of the first channel is provided to both the channel driver of the first channel and the channel driver of the second channel.
According to a fifth media interface controller of the first aspect of the present application, there is provided the sixth media interface controller of the first aspect of the present application, wherein the first switch for the channel transmission/reception unit further disconnects the coupling of the channel transmission/reception unit of the second channel with the channel driver of the second channel.
According to the fifth or sixth media interface controller of the first aspect of the present application, there is provided the seventh media interface controller of the first aspect of the present application, further comprising a second switch for the channel transmission/reception unit; the second switch for the channel transmitting/receiving unit couples the channel transmitting/receiving unit of the third channel with the channel driver of the fourth channel, so that the signal output by the channel transmitting/receiving unit of the first channel is simultaneously provided to the channel driver of the third channel and the channel driver of the fourth channel.
According to one of the first to fourth media interface controllers of the first aspect of the present application, there is provided the eighth media interface controller of the first aspect of the present application, each of the channel circuits further comprising an n-to-1 switch for coupling an output of the channel transmitting/receiving unit of one of the n channel circuits to a channel driver of the channel circuit to which the n-to-1 switch belongs; the output of the n-to-1 switch of the first channel is coupled with the input of the channel driver of the first channel, and the input of the n-to-1 switch of the first channel is coupled with the channel transmitting/receiving unit of each channel; wherein the media interface controller comprises n channel circuits.
According to one of the first to fourth media interface controllers of the first aspect of the present application, there is provided the ninth media interface controller of the first aspect of the present application, each channel circuit further comprising a1 to n switch for coupling an output of the channel transmit/receive unit of the channel circuit to the channel driver of each of the n channel circuits; the 1-to-n switches of the first channel are used to simultaneously supply the output of the channel transmit/receive unit of the first channel to the channel driver of each of one or more of the n channel circuits.
According to one of the first to ninth media interface controllers of the first aspect of the present application, there is provided the tenth media interface controller of the first aspect of the present application, further comprising a spare channel circuit and a fifth switch; the spare channel circuit does not include a channel pin; the fifth switch couples the channel driver of the standby channel circuit to the channel pin of the first channel circuit, so that the channel driver of the first channel and the channel driver of the standby channel jointly drive the channel pin of the first channel.
According to one of the first to tenth media interface controllers of the first aspect of the present application, there is provided an eleventh media interface controller according to the first aspect of the present application, responsive to insufficient drive capability of an NVM channel to which the first channel circuit is coupled, closing the first switch such that the first switch couples the channel driver of the second channel circuit to the channel pin of the first channel circuit; in response to the first channel circuit having sufficient drive capability for the NVM channel to which it is coupled, the first switch is opened such that the channel driver of the second channel circuit is not coupled to the channel pin of the first channel circuit.
According to one of the first to eleventh media interface controllers according to the first aspect of the present application, there is provided the twelfth media interface controller according to the first aspect of the present application, further comprising a frequency allocation unit; the frequency allocation unit sets a signal transmission frequency of one or more of the plurality of channels.
According to a twelfth media interface controller of the first aspect of the present application, there is provided the thirteenth media interface controller of the first aspect of the present application, wherein the frequency allocation unit sets the signal transmission frequency of one or more of the plurality of channels so that the sum of the drive capabilities of the plurality of channels does not exceed the drive capability upper limit of the media interface controller.
According to a twelfth or thirteenth media interface controller of the first aspect of the present application, there is provided the fourteenth media interface controller of the first aspect of the present application, wherein the frequency allocation unit sets the signal transmission frequency of one or more of the plurality of channels according to the data transmission requirement of the one or more channels.
According to one of the twelfth to fourteenth media interface controllers of the first aspect of the present application, there is provided the fifteenth media interface controller of the first aspect of the present application, wherein the frequency allocation unit sets the signal transmission frequency of one or more of the plurality of channels by setting the frequency of the clock signal supplied to the channel circuit.
According to a second aspect of the present application, there is provided a first media interface controller according to the second aspect of the present application, comprising a plurality of channel circuits for coupling NVM channels; each channel circuit comprises a channel sending/receiving unit and a channel pin; the media interface controller also includes a channel driver pool having channel drivers, one or more channel drivers of the channel driver pool being coupled to the one or more channel circuits.
A first media interface controller according to a second aspect of the present application, there is provided a second media interface controller according to the second aspect of the present application, further comprising a first configurable interconnection unit; the first configurable interconnect unit couples one or more channel drivers of a channel driver pool to channel pins of one or more channel circuits.
According to a second media interface controller of the second aspect of the present application, there is provided a third media interface controller of the second aspect of the present application, the first configurable interconnection unit coupling a first plurality of channel drivers of the channel driver pool to channel pins of a first channel; and the first configurable interconnect unit couples a second plurality of channel drivers of the channel driver pool to channel pins of a second channel.
According to one of the first to third media interface controllers of the second aspect of the present application, there is provided a fourth media interface controller according to the second aspect of the present application, further comprising a second configurable interconnection unit; the second configurable interconnect unit couples the channel transmit/receive units of the one or more channel circuits to one or more channel drivers of the channel driver pool.
According to a fourth media interface controller of the second aspect of the present application, there is provided a fifth media interface controller of the second aspect of the present application, the second configurable interconnection unit coupling the channel transmit/receive unit of the first channel to the first plurality of channel drivers of the channel driver pool; and the two configurable interconnect units couple the channel transmit/receive unit of the first channel to the second plurality of channel drivers of the channel driver pool.
According to a fifth media interface controller of the second aspect of the present application, there is provided the sixth media interface controller of the second aspect of the present application, wherein the channel transmit/receive units of the first channel simultaneously provide the same signal to the first plurality of channel drivers through the second configurable interconnect, and the first plurality of channel drivers simultaneously drive the channel pins of the first channel through the first configurable interconnect.
According to a fifth media interface controller of the second aspect of the present application, there is provided the seventh media interface controller of the second aspect of the present application, wherein the channel transmit/receive units of the second channel simultaneously provide the same signal to the second plurality of channel drivers through the second configurable interconnect, and the second plurality of channel drivers simultaneously drive the channel pins of the second channel through the first configurable interconnect.
According to a third aspect of the present application, there is provided a first memory device according to the third aspect of the present application, comprising a control section and one or more NVM chips; the control component comprises a media interface controller according to any of the first or second aspects above, the media interface controller coupling the one or more NVM chips.
According to a fourth aspect of the present application, there is provided the first method for a media interface controller according to the fourth aspect of the present application, the media interface controller comprising N channel circuits for coupling NVM channels; the method comprises the following steps: enabling the N channel circuits to work simultaneously, and identifying whether each of the N channel circuits works normally; in response to that any one of the N channel circuits cannot work normally, implementing one or more times of detection, cutting off one of the N channel circuits each time of detection, and enabling the rest multiple channel circuits to work simultaneously, and if each of the rest M channel circuits in a certain detection works normally, identifying that at most M channel circuits in the N channel circuits of the media interface controller can work simultaneously; wherein M and N are positive integers; and ensuring that the number of the channel circuits which work simultaneously in the medium interface controller is not more than M.
According to a fifth aspect of the present application, there is provided the first method for a media interface controller according to the fifth aspect of the present application, the media interface controller comprising N channel circuits for coupling NVM channels; the method comprises the following steps: causing the N channel circuits to operate simultaneously at a first frequency and identifying whether each of the N channel circuits is operating normally; in response to any of the N channel circuits failing to operate properly, performing one or more probing operations, each probing operation causing one or more of the N channel circuits to operate simultaneously at a reduced frequency and causing the remaining plurality of channel circuits to operate simultaneously at the last probed operating frequency; if each of the N channel circuits works normally in a certain detection, recording the working frequency of each of the N channel circuits; and enabling the operating frequency of each channel circuit of the media interface controller which operates simultaneously to be not higher than the recorded operating frequency of the channel.
According to a sixth aspect of the present application, there is provided the first method for a media interface controller according to the sixth aspect of the present application, the media interface controller comprising N channel circuits for coupling NVM channels; the method comprises the following steps: identifying whether the channel circuit works normally; and in response to the first channel circuit not working normally, coupling the channel drivers of one or more other channel circuits to the channel pin of the first channel, and driving the channel pin of the first channel by the channel driver of the first channel and the channel drivers of the one or more other channel circuits at the same time.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a block diagram of a prior art memory device;
FIG. 2 illustrates a block diagram of a media interface controller coupling a plurality of channels;
FIG. 3 illustrates a block diagram of a media interface controller coupling multiple channels according to yet another example;
4A, 4B and 4C illustrate a media interface controller with enhanced drive capability according to an embodiment of the present application;
FIG. 5 illustrates a media interface controller with enhanced drive capability according to yet another embodiment of the present application; and
FIG. 6 illustrates a media interface controller with enhanced drive capability according to yet another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
FIG. 2 shows a block diagram of a media interface controller coupling multiple channels.
The control component of the storage device includes a media interface controller. The media interface controller couples a plurality of channels (channel 1, channel 2, channel 3, and channel 4). The NVM chip is coupled to the channel. By way of example, lane 1 is coupled to NVM chip A, lane 2 is coupled to NVM chip B, lane 3 is coupled to NVM chip C, and lane 4 is coupled to NVM chip D. In fig. 2, a1, a2, and A3 indicate the same NVM chip a in different probing processes. Similarly, B1, B2, and B3 indicate the same NVM chip B.
The media interface controller includes a set of pins coupled to the channels. In fig. 2, channel 1 pins (representing one set of pins) are used to couple channel 1, channel 2 pins (one set of pins) are used to couple channel 2, channel 3 pins (one set of pins) are used to couple channel 3, and channel 4 pins (one set of pins) are used to couple channel 4. The control unit further includes a plurality of channel drivers (channel 1 driver, channel 2 driver, channel 3 driver, and channel 4 driver) for exchanging electrical signals with the respective channels through corresponding channel pins.
To identify the driving capability of the media interface controller to determine the number of NVM chips it can couple to and/or the frequency of signal transmission, multiple probes are performed on the coupled NVM chips.
In the example of fig. 2, 3 probes are shown. In the first probe, 1 NVM chip (NVM chip A, NVM chip B, NVM chip C and NVM chip D) is coupled to each channel, and each NVM chip operates at a frequency of 666MT/s, for example. In the detection, whether the driving capability meets the requirement is identified through the normal operation of the media interface controller and each channel. For example, in the first detection, each channel cannot operate, indicating insufficient driving capability, and the second detection is performed. In the second probing, the load on the media interface controller is reduced relative to the first probing. Specifically, the NVM chips such as channel 3 and channel 4 are removed, or channel 3 and channel 4 are cut off, while the NVM chips on each of channel 1 and channel 2 are reserved, and the operating frequencies of the NVM chips A and B are 666 MT/s. For example, in the second detection, the channel 1 and/or the channel 2 still cannot work, which indicates that the driving capability is still insufficient, so that the third detection is performed. In the third probing, only channel 1 is turned on, and channel 1 is coupled with 1 NVM chip A, and the operating frequency is 666 MT/s. By way of example, in the third detection, channel 1 works normally. Thus, the current driving capability is only capable of operating in a single channel, single NVM chip, and 666MT/s configuration.
Through multiple detections, the driving capability of the media interface controller can be identified, and a configuration for enabling the media interface controller to work normally is found. But some channels are closed, limiting the performance and/or capacity of the control unit.
Optionally, the constraint of the driving capability is also satisfied by reducing the operating frequency.
FIG. 3 illustrates a block diagram of a media interface controller coupling multiple channels according to yet another example.
The media interface controller of FIG. 3 is coupled to the NVM chip in a manner similar to that of FIG. 2.
To identify the driving capability of the media interface controller, 1 NVM chip is coupled to each channel of the media interface controller at each of the multiple probes, but the operating frequency is changed.
In the first probe, each channel is operated at 666MT/s frequency. As an example, the first detection indicates insufficient driving capability. In the second probing, each channel was operated at 533 MT/s. As an example, the second detection indicates insufficient driving capability. In the third probe, each channel was operated at 400 MT/s. In the third detection, each channel worked properly. Therefore, the driving capability of the medium interface controller is identified, and the 4 channels can work at 400MT/s frequency when working concurrently. Due to the limited driving capability, if all 4 channels are used, only the operating frequency can be reduced.
The driving capability of the chip is composed of the driving capability of each pin. The pin driving capability is mainly related to the pin's ability to output current. While the chip technology constrains the output current capability of the pins.
Fig. 4A, 4B and 4C show a media interface controller with enhanced drive capability according to an embodiment of the present application.
Referring to fig. 4A, the media interface controller includes channel circuitry for coupling, for example, 4 channels. The channel circuit for coupling channels includes a channel transmit/receive unit, a channel driver, and a channel pin. In fig. 4A, numerals in the channel transmitting/receiving unit, the channel driver, and the channel pin as reference numerals represent the channel circuit to which they belong and also represent the channel to which they are coupled.
The channel transmission/reception unit (channel 1 transmission/reception unit, channel 2 transmission/reception unit, channel 3 transmission/reception unit, or channel 4 transmission/reception unit) is used to control a signal transmission and/or reception operation on the channel pin, and the channel driver (channel 1 driver, channel 2 driver, channel 3 driver, or channel 4 driver) is used to drive current generation (or reception) of a signal on the channel pin. Channel pins (channel 1 pin, channel 2 pin, channel 3 pin, or channel 4 pin) represent a set of pins for coupling channels.
By way of example, in FIG. 4A, channel 1 is coupled to NVM chip A1, channel 3 is coupled to NVM chip C1, and channel 2 and channel 4 are not coupled to NVM chips.
In order to enable the NVM chip a1 and the NVM chip C1 to operate at 666MT/s frequency simultaneously, for example, the media interface controller according to the embodiment of the present application further includes a switch 1 and a switch 2 to combine the currents generated by the two channel drivers, respectively, so as to increase the driving capability. Referring to fig. 4A, a channel 1 driver is used to drive the channel 1 pin, while a channel 2 driver is coupled to the channel 2 pin, the channel 2 driver also being coupled to the channel 1 pin through switch 1, such that when switch 1 is closed, the channel 2 driver is also used to drive the channel 1 pin. Thereby enhancing the driving capability of channel 1.
Similarly, a channel 3 driver is used to drive the channel 3 pin, while a channel 4 driver is coupled to the channel 4 pin, the channel 4 driver also being coupled to the channel 3 pin through the switch 2, so that when the switch 2 is closed, the channel 2 driver is also used to drive the channel 1 pin. Thereby enhancing the driving capability of channel 1.
According to the embodiment of FIG. 4A, the limited output currents of the channel drivers are applied to two channels (channel 1 and channel 3), while the other channels are turned off or inactive, so that the NVM chips coupled to the two channels (NVM chip A1 and NVM chip C1) can operate at higher frequencies. In the example of FIG. 4A, NVM chip A1 and NVM chip C1 operate at 666 MT/s.
Alternatively, according to the embodiment of fig. 4A, channel 2 and/or channel 4 are operated by opening switch 1 and/or switch 2. For example, lane 2 and/or lane 4 are coupled to NVM chips, or NVM2 and/or lane 4 are operating at a lower frequency (e.g., 400MT/s), while lane 1 and/or lane 3 may be shut down to reduce loading of the media interface controller.
Alternatively, the media interface controller includes other numbers (not limited to 4) of channel circuits, each for coupling channels. And the media interface controller includes other numbers (not limited to 2) of switches for coupling two or more channel drivers to the same channel pin. Optionally, the number of switches is larger than the number of channel drivers, so that one channel driver may be coupled to a different channel driver, respectively, at different times.
Optionally, switches 1 and 2 also couple the channel pins to the channel driver, and thus from the channel pins. For example, the channel 1 pin receives a signal from the channel coupled to the channel 1 driver, while switch 1 also couples the channel 1 pin to the channel 2 driver. The channel 3 pin receives a signal from the channel coupled to the channel 3 driver, while the switch 2 also couples the channel 3 pin to the channel 4 driver.
According to the embodiment of fig. 4A, when switch 1 is closed, the lane 1 driver and the lane 2 driver transmit the same signal to the lane 1 pin synchronously. When switch 2 is closed, the lane 3 driver transmits the same signal to the lane 3 pin in synchronization with the lane 4 driver. The channel 1 driver and the channel 2 driver transmit the same signal to the channel 1 pin synchronously by the channel 1 transmitting/receiving unit and the channel 2 transmitting/receiving unit respectively controlling the transmission and/or the reception of the same signal synchronously. The channel 3 driver and the channel 4 driver transmit the same signal to the channel 3 pin synchronously by the channel 3 transmit/receive unit controlling the transmission and/or reception of the same signal synchronously with the channel 4 transmit/receive unit, respectively.
To better synchronize the signals of multiple channels, in the embodiment illustrated in fig. 4B, the media interface controller further includes a switch 3 and a switch 4.
The input of switch 3 couples the outputs of the channel 1 transmit/receive unit and the channel 2 transmit/receive unit, and the output of switch 3 is coupled to the channel 2 driver. And the output of the channel 1 transmit/receive unit is also coupled to the channel 1 driver. When switch 1 is closed, switch 3 couples the output of the channel 1 transmit/receive unit to the channel 2 driver, and decouples the channel 2 transmit/receive unit from the channel 2 driver. Thus, when switch 1 is closed, the output of the lane 1 transmit/receive unit is simultaneously provided to the lane 1 driver and the lane 2 driver through switch 3, so that the lane 1 driver and the lane 2 driver transmit the same signals to the lane 1 pin synchronously (because the signals are from the same lane 1 transmit/receive unit).
Similarly, the input of switch 4 couples the outputs of channel 3 transmit/receive unit and channel 4 transmit/receive unit, and the output of switch 4 is coupled to the channel 4 driver. And the output of the channel 3 transmit/receive unit is also coupled to the channel 1 driver. When switch 1 is closed, switch 3 couples the output of the channel 1 transmit/receive unit to the channel 3 driver, while decoupling the channel 4 transmit/receive unit from the channel 4 driver. Thus, when switch 2 is closed, the output of the channel 3 transmit/receive unit is simultaneously provided to the channel 3 driver and the channel 4 driver through switch 4, so that the channel 3 driver and the channel 4 driver transmit the same signal to the channel 3 pin synchronously.
To distinguish from the switches 1 and 2, the switches 3 and 4 are also referred to as switches for channel transmission/reception units.
Alternatively, the media interface controller includes other numbers (not limited to 4) of channel circuits, each for coupling channels. And the media interface controller includes another number (not limited to 2) of switches for the channel transmit/receive units for coupling 1, 2, or more number of channel transmit/receive units each to the plurality of channel drivers. Alternatively, the number of switches for the channel transmission/reception units is greater than the number of channel transmission/reception units, so that one channel transmission/reception unit can be respectively coupled to different channel drivers at different times.
As yet another example, the channel 1 transmit/receive unit is coupled to the channel 1 driver, the channel 2 driver, and the channel 3 driver, and accordingly the channel 1 driver, the channel 2 driver, and the channel 3 driver are coupled to the channel 1 pin by a switch or switches, such that the channel 1 is operated by a single channel 1 transmit/receive unit with the driving capability provided by the 3 channel drivers. While operating 3 channel drivers simultaneously with a single channel 1 transmit/receive unit also facilitates having 3 channel drivers simultaneously provide the same signal to channel 1.
Alternatively, in order to enable a single channel transmit/receive unit to simultaneously operate a plurality of channel drivers, the single channel transmit/receive unit is coupled to each of the plurality of channel drivers through a plurality of switches. Still alternatively, the input terminal of each channel driver is coupled to a n-to-1 switch, the n-to-1 switch has n inputs, n is the same as the number of channel transmit/receive units, and the corresponding output of the n-to-1 switch is coupled to the input terminal of the channel driver. Still optionally, an output of each channel transmit/receive unit is coupled to a 1-to-n switch, an input of the 1-to-n switch is coupled to an output of a corresponding channel transmit/receive unit, and an output of the 1-to-n switch is coupled to each of the n channel drivers to provide the output of the channel transmit/receive unit to one or more of the n channel drivers. It will be appreciated that channel drivers are also coupled to channel pins by 1-to-n switches or n-to-1 switches to couple multiple channel drivers to a single channel pin.
In the embodiment of FIG. 4C, the number of channel circuits is greater than the number of channels to which the media interface controller is coupled, or greater than the number of channel pins. Such that one or more channel circuits (including, for example, a channel transmit/receive unit and a channel driver) become backup channel circuits. In the example of FIG. 4C, the backup channel circuit includes a channel 4 send/receive unit and a channel 4 driver. In response to identifying, for example, that the drive capability of channel 3 is insufficient, a channel 4 driver is coupled through switch 3 to the channel 3 pin such that the channel 3 driver and the channel 4 driver jointly drive the channel 3 pin to enhance the drive capability of the channel 3 pin.
FIG. 5 illustrates a media interface controller with enhanced drive capability according to yet another embodiment of the present application.
Referring to fig. 5, the media interface controller includes channel circuitry for coupling, for example, 4 channels. The channel circuit comprises a channel sending/receiving unit, a channel driver and a channel pin. Channel 1 pins are used to couple channel 1, channel 2 pins are used to couple channel 2, channel 3 pins are used to couple channel 3, and channel 4 pins are used to couple channel 4. For example, 4 channel transmit/receive units are coupled to a channel driver pool via a configurable interconnect unit 510, and the channel driver pool is coupled to, for example, 4 channel pins via a configurable interconnect unit 520.
The channel driver pool includes a plurality of drivers that, when coupled to the channel pins, each provide a limited driving capability on the corresponding channel for the coupled channel pins. The number of drives of the drive pool is not less than the number of channels. Two or more drivers of the channel driver pool can thus be coupled to the same channel to enhance the driving capability for that channel.
The output of one of the lane transmit/receive units is coupled to one or more drivers of the pool of drivers via a configurable interconnect 510 such that the lane transmit/receive unit can simultaneously operate the coupled one or more drivers with the same signal. For example, via configurable interconnect 510, a lane 1 transmit/receive unit is coupled to 3 drivers of the lane driver pool, a lane 2 transmit/receive unit is coupled to another 4 drivers of the lane driver pool, and a lane 3 transmit/receive unit is coupled to still another 1 driver of the lane driver pool.
One or more drivers of the channel driver pool are coupled to a single channel pin by the configurable interconnect unit 520 such that the one or more drivers simultaneously provide the same signal to the single channel pin. For example, through the configurable interconnect unit 520, the 3 drivers coupled to the lane 1 transmit/receive unit mentioned above are coupled to the lane 1 pin, the 4 drivers coupled to the lane 2 transmit/receive unit are coupled to the lane 2 pin, and the 1 driver coupled to the lane 3 transmit/receive unit is coupled to the lane 3 pin. Thus, through the combination of configurable interconnect 510 and configurable interconnect 520, a lane 1 transmit/receive unit can operate lane 1 with enhanced drive capability provided by 3 drivers, a lane 2 transmit/receive unit can operate lane 2 with enhanced drive capability provided by 4 drivers, and a lane 3 transmit/receive unit can operate lane 3 with 1 driver. Thus, the media interface controller, by configuring configurable interconnect 510 and configurable interconnect 520, drives the channels with different numbers of drivers, depending on the required drive capabilities of each channel.
It will be appreciated that configurable interconnect 510 causes the channel transmit/receive units to simultaneously apply the same control signals to the one or more drivers coupled thereto, while configurable interconnect 520 causes the one or more drivers to simultaneously apply the same signals to the channel pins to which they are coupled.
Due to the enhanced drive capability, the channels of the media interface controller can operate simultaneously at, for example, a higher frequency of 666 MT/s.
FIG. 6 illustrates a media interface controller with enhanced drive capability according to yet another embodiment of the present application.
According to the embodiment of the application, in addition to enhancing the driving capability of the media interface controller to the channels by combining a plurality of channel drivers, the driving capability is reasonably distributed among a plurality of channels, so that the total driving capability of the plurality of channels in the process of working simultaneously is prevented from exceeding the driving capability of the media interface controller, and the performance requirement of each channel is met as much as possible.
Referring to fig. 6, the media interface controller includes channel circuitry for coupling, for example, 4 channels. The channel circuit comprises a channel sending/receiving unit, a channel driver and a channel pin. The media interface controller also includes a frequency assignment unit that couples the respective channel circuits to set a signal transmission frequency of the respective channels. The frequency of the channel is positively correlated with the power consumption, and the higher the frequency is, the more power is consumed for signal transmission, and the higher the driving capability is required. To avoid that the total power consumption or driving capability requirement exceeds the driving capability of the media interface controller when multiple channels are simultaneously operating at higher frequencies, the frequency allocation unit sets an operating frequency of 666MT/s for channel circuit 1, 400MT/s for channel 2, 400MT/s for channel 3, and makes channel 4 temporarily inactive, for example.
Alternatively, the frequency allocation unit determines an upper limit of the combination of the operating frequencies of the respective channels in accordance with an upper limit of a driving capability of the media interface controller. For example, under the condition of the upper limit of the driving capability of the media interface controller, 1 channel works at 666MT/s and 2 channels work at 400MT/s when multiple channels are simultaneously made; or at most 3 channels at 533MT/s, or at most 4 channels at 400 MT/s. And the medium interface controller sets the working frequency of each channel through the frequency distribution unit according to the data access requirement of each channel. For example, channel 1 is set to a higher operating frequency, e.g., 666MT/s, by the frequency allocation unit in response to channel 1 being written sequentially with a large amount of data, and to a lower operating frequency, e.g., 400MT/s, in response to channel 2 being processing random read operations. Channel 3 is set to a higher operating frequency of, for example, 666MT/s by the frequency allocation unit temporarily reducing the operating frequency of channel 1 and/or channel 2, or shutting down these channels, while accessing the NVM chips of channel 3 in response to a high priority read request. For another example, if the memory device enters one or more low power consumption states, the upper limit of the driving capability of the media interface controller is correspondingly reduced, and the upper limit of the operating frequency combination of each channel determined by the frequency allocation unit is also correspondingly reduced. The frequency allocation unit sets the operating frequency of the channel by, for example, setting the frequency of the channel transmission/reception unit or the frequency of the clock supplied to the channel transmission/reception unit.
Although the present application has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A media interface controller with enhanced drive capability, characterized by: including a plurality of channel circuits for coupling to NVM channels;
each channel circuit comprises a channel driver and a channel pin, wherein the channel driver is used for exchanging electric signals with the NVM channel through the channel pin;
the media interface controller includes a first switch that couples the channel driver of the second channel circuit to the channel pin of the first channel circuit such that the channel driver of the first channel and the channel driver of the second channel cooperatively drive the channel pin of the first channel.
2. The media interface controller with enhanced drive capability of claim 1, wherein: the device also comprises a second switch which is connected with the first switch,
the first switch couples the channel driver of the fourth channel circuit with the channel pin of the third channel circuit, so that the channel driver of the third channel and the channel driver of the fourth channel jointly drive the channel pin of the third channel.
3. The media interface controller with enhanced drive capability of claim 1, wherein: and a third switch is also included, and the third switch,
the third switch couples the channel driver of the fifth channel circuit to the channel pin of the first channel circuit, such that the channel driver of the first channel, the channel driver of the second channel, and the driver of the fifth channel collectively drive the channel pin of the first channel.
4. A media interface controller with enhanced drive capabilities according to any one of claims 1-3, wherein each channel further comprises a channel transmit/receive unit coupled to a corresponding channel driver;
the media interface controller further comprises a first switch for the channel transmit/receive unit;
the first switch for the channel transmit/receive unit couples the channel transmit/receive unit of the first channel to the channel driver of the second channel such that the signal output by the channel transmit/receive unit of the first channel is provided to both the channel driver of the first channel and the channel driver of the second channel.
5. A media interface controller with enhanced drive capabilities according to any one of claims 1-3, wherein
Each channel circuit further includes an n-to-1 switch for coupling an output of the channel transmission/reception unit of one of the n channel circuits to a channel driver of the channel circuit to which the n-to-1 switch belongs;
the output of the n-to-1 switch of the first channel is coupled with the input of the channel driver of the first channel, and the input of the n-to-1 switch of the first channel is coupled with the channel transmitting/receiving unit of each channel; wherein the media interface controller comprises n channel circuits.
6. A media interface controller with enhanced drive capabilities according to any one of claims 1-3, wherein
Each channel circuit further includes a 1-to-n switch for coupling an output of the channel transmit/receive unit of the channel circuit to the channel driver of each of the n channel circuits;
the 1-to-n switches of the first channel are used to simultaneously supply the output of the channel transmit/receive unit of the first channel to the channel driver of each of one or more of the n channel circuits.
7. A media interface controller with enhanced drive capability according to one of claims 1-3, wherein: also includes a frequency allocation unit;
the frequency allocation unit sets a signal transmission frequency of one or more of the plurality of channels.
8. A media interface controller with enhanced drive capability, characterized by: including a plurality of channel circuits for coupling to NVM channels;
each channel circuit comprises a channel sending/receiving unit and a channel pin;
the media interface controller also includes a channel driver pool having channel drivers, one or more channel drivers of the channel driver pool being coupled to the one or more channel circuits.
9. The media interface controller with enhanced drive capability of claim 8, wherein: further comprising a first configurable interconnection unit;
the first configurable interconnect unit couples one or more channel drivers of a channel driver pool to channel pins of one or more channel circuits.
10. A media interface controller with enhanced drive capability according to claim 8 or 9, wherein: further comprising a second configurable interconnection unit;
the second configurable interconnect unit couples the channel transmit/receive units of the one or more channel circuits to one or more channel drivers of the channel driver pool.
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