CN109710186A - A kind of high-speed data processing and Transmission system based on eMMC array - Google Patents
A kind of high-speed data processing and Transmission system based on eMMC array Download PDFInfo
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- CN109710186A CN109710186A CN201811572294.XA CN201811572294A CN109710186A CN 109710186 A CN109710186 A CN 109710186A CN 201811572294 A CN201811572294 A CN 201811572294A CN 109710186 A CN109710186 A CN 109710186A
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Abstract
The invention discloses a kind of high-speed data processing and Transmission system based on eMMC array, which includes main control chip, for controlling the transmission of the data between modules；Optical fiber transmission module, including the road N optical fiber obtain high-speed parallel data for receiving optical signal and carrying out processing to optical signal, and the data are transmitted to DDR3 cache module；DDR3 cache module is cached for the high-speed parallel data to optical fiber transmission module；EMMC array memory module, for storing the data of DDR3 cache module；USB transmission module, for the data of eMMC array memory module to be transmitted in PC machine or other boards；Power module, for powering for the storage of entire data with Transmission system；Clock module, for providing work clock for optical fiber transmission module, DDR3 cache module and eMMC array memory module.Data storage of the invention and Transmission system have the characteristics that small in size, capacity greatly and with roomy, realize the real-time storage and transmission of data.
Description
Technical field
The invention belongs to the communications field, in particular to a kind of high-speed data processing and Transmission system based on eMMC array.
Background technique
Currently, data-storage system using more and more extensive, it has become in the industries such as scientific research, medical treatment, industry
Irreplaceable equipment.It needs us to develop the storage equipment of a set of big bandwidth large capacity of high speed for being suitble to need in this way, is used for
A large amount of high-speed data is stored, and there is high speed data transfer ability, can to export the data of storage system afterwards.?
In field of radar, the main medium of traditional data-storage system is NAND FLASH, is based on NAND FLASH chip in exploitation
Storage equipment when need to expend excessive energy and resource bad block management, wear leveling and the bit error rate the problem of.
EMMC (embedded Muti Media Card, built-in multimedia storage card) is a kind of NAND of management type
FLASH.Different from traditional NAND FLASH+ control module storage scheme, eMMC is sharp by storage medium and internal master control logic
With the BGA package of standard at a small in size, highly integrated micro chip.Chip interior master control logic is integrated with FLASH control
Device processed, including the functions such as error checking and correction mechanism, bad block management, power down protection and wear leveling.Externally using by
The unified eMMC consensus standard package interface formulated of MMC association.User is when developing eMMC chip, without the concern for being internally embedded
FLASH chip otherness and compatibility as brought by different vendor and model manufacture craft, only need to be according to standard agreement
Master control logic is designed on a hardware platform, the operations such as storage and the transmission to chip is completed, so that application side concentrates on production
Product research and development significantly shorten the research and development time and reduce research and development cost.EMMC chip is in memory capacity and storage speed at present
On all reached relatively high performance standard, it is excellent to have that interface is unified, memory capacity is big, transmission speed is fast and integrated level is high etc.
Gesture develops into the storage chip of current mainstream instead of traditional FLASH chip gradually, is the heat of current research
Point.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of high-speed data processing and Transmission system.
The technical solution for realizing the aim of the invention is as follows: a kind of high-speed data processing based on eMMC array and transmission are
System, including main control chip, power module, clock module and the optical fiber transmission module being sequentially connected, DDR3 cache module, eMMC
Array memory module, USB transmission module；
The main control chip, for controlling the transmission of the data between modules；
The optical fiber transmission module, including the road N optical fiber obtain high speed for receiving optical signal and carrying out processing to optical signal
Parallel data, and the data are transmitted to DDR3 cache module；
The DDR3 cache module, caches for the high-speed parallel data to optical fiber transmission module；
The eMMC array memory module, for storing the data of DDR3 cache module；
The USB transmission module, for the data of eMMC array memory module to be transmitted in PC machine or other boards；
The power module, for powering for the storage of entire data with Transmission system；
The clock module, for providing work for optical fiber transmission module, DDR3 cache module and eMMC array memory module
Make clock.
Compared with prior art, the present invention its remarkable advantage are as follows: 1) it is reluctant bad to solve traditional flash by the present invention
Block management and ECC check problem；2) carried out data transmission in the present invention by the way that several eMMC are constituted eMMC array parallel,
Read or write speed and memory capacity can be doubled and redoubled, and have very strong practicability；3) present invention is stored with eMMC array,
USB3.0 is high-speed transmission interface, has stronger versatility and portability.
The present invention is described in further detail with reference to the accompanying drawing.
Detailed description of the invention
Fig. 1 is that the present invention is based on the structural block diagrams of the high-speed data processing of eMMC array and Transmission system.
Fig. 2 is the structural block diagram of clock module in the present invention.
Fig. 3 is the structural block diagram of optical fiber transmission module in the present invention.
The structural block diagram of DDR3 cache module in Fig. 4 present invention.
Fig. 5 is the structural block diagram of eMMC array memory module in the present invention.
Fig. 6 is the structural block diagram of USB3.0 transmission module in the present invention.
Specific embodiment
In conjunction with Fig. 1, a kind of high-speed data processing and Transmission system based on eMMC array of the invention, including main control chip,
Power module, clock module and the optical fiber transmission module being sequentially connected, DDR3 cache module, eMMC array memory module, USB
Transmission module.Wherein,
Main control chip, for controlling the transmission of the data between modules；
Optical fiber transmission module, including the road N optical fiber obtain high-speed parallel for receiving optical signal and carrying out processing to optical signal
Data, and the data are transmitted to DDR3 cache module；
DDR3 cache module is cached for the high-speed parallel data to optical fiber transmission module；
EMMC array memory module, for storing the data of DDR3 cache module；
USB transmission module, for the data of eMMC array memory module to be transmitted in PC machine or other boards；
Power module, for powering for the storage of entire data with Transmission system；
Clock module, when for providing work for optical fiber transmission module, DDR3 cache module and eMMC array memory module
Clock.
Further, main control chip uses FPGA or ARM or CPLD.
Further, the model XC7VX690TFFG1761-2 of FPGA.
Further, in conjunction with Fig. 2, clock module includes:
Clock chip, for generating stable clock；
Clock chip configuration module, the running parameter for configurable clock generator chip；
Reseting module, for restoring clock chip to reset condition.
As a kind of specific example, the working method of clock module are as follows:
(1) system board provides global clock of the clock crystal oscillator as main control chip of a 25MHz；
(2) main control chip is by the clock buffer inside the clock access chip, to increase the driving capability of the clock；So
Afterwards by the clock as the driving clock in SPI (Serial Peripheral Interface) bus, for configuring SI5338
Clock chip.
(3) after clock chip SI5338 is configured running parameter, by externally input reference clock signal as input
Signal exports the clock signal of two different frequencies by the frequency multiplication and frequency divider of chip interior respectively, and is transferred to eMMC times
The Clock management module of column memory module provides work clock for system initialization and data transmission.
Further, in conjunction with Fig. 3, optical fiber transmission module includes:
Optical-fibre channel module, for converting high speed serialization electric signal for the optical signal received；
The high speed serialization electric signal that optical-fibre channel receives is gone here and there and is turned inside host by high speed serialization transceiver module
It changes and handles and be transferred to DDR3 cache module.
(1) the high speed serialization electric signal after host converts optical-fibre channel is converted to parallel data by SERDES.
(2) parallel data transmission after host converts high-speed serial channel is to DDR3 cache module.
Further, in conjunction with Fig. 4, as a kind of specific example, DDR3 cache module includes:
DDR3 module for reading and writing, match company, Sentos provides the soft core of DDR3MIG, after developer learns the user's manual of the soft core
Corresponding parameter is set according to design requirement and generates corresponding core module.Phase is write according to DDR3 user terminal bus read-write sequence
The verilog code answered realizes read-write logic function, eventually for data of the caching from optical fiber transmission module.
Ping-pong operation control module, the present invention in cache module use two groups of DDR3, controlled by ping-pong operation,
Alternately read-write transmission data.Data are cached to DDR3_A module by optical port data first under the control of input data selector
In.In second caching period, input data selector is switched over, and starts DDR3_B module for reading and writing, at the same time, exports number
The data of reading DDR3_A module for reading and writing are selected according to selector.In third caching period, input data selector switches again
By data buffer storage in DDR3_A module, while outlet selector switches over the data for reading DDR3_B module, and two groups of DDR3 are such as
This read-write alternate cycles carries out.
Further, in conjunction with Fig. 5, eMMC array memory module includes:
Clock management module provides work clock for the modules for eMMC controller, and at the beginning of switching system
Beginningization clock and data transfer clock；
System initialization module is completed equipment and is worked normally for carrying out electrification reset and parameter configuration for eMMC array
Preceding preparation；
Order transceiver module is used for initialization module and data transmission module, host and communication between devices order and response
Send and receive；
Data transmission module, for realizing the read-write of eMMC array memory module；
Transmit protective module, including CRC7 verification, CRC16 verification, the order sum number transmitted in guarded command bus
According to the data transmitted in bus.
As a kind of specific example, the concrete function that each module is realized is as follows:
(1) Clock management module: the 200MHz clock that input clock source uses clock chip to provide, it is included using vivado
Clocking Wizard IP kernel.When providing 200MHz in eMMC initial phase offer 250KHz clock, normal work
Clock.
(2) system initialization module: the main electrification reset for completing equipment, equipment identification, the distribution of equipment relative address with
And the relevant operations such as setting of operating mode and mode bus.According to eMMC5.0 agreement, initialization operation needs sequence is sent
CMD0,CMD1,CMD2,CMD3,CMD9,CMD7,CMD6.After operation more than completion, system initialization operation terminates simultaneously raw
At corresponding zone bit information, the relevant operations such as expression system can be written and read and wipe.If occurring mistake in above step
Resettable equipment carries out system initialization process again.After the completion of initialization, it can be checked by dedicated CMD13 order
Whether equipment has been in the correctness of data transmission state verifying initialization.
(3) order transceiver module: exchanging between FPGA and eMMC runs through order and response always, the function packet of the module
Host is included to send commands to eMMC equipment by CMD bus and receive the command response fed back from eMMC equipment.FPGA will
48bit order carries out parallel-serial conversion, and passing through command line is transferred to eMMC later.Command line be it is two-way, eMMC receives order
Respective response and feedback command response equally are made in command line afterwards, serioparallel exchange resolve command is carried out after being received by FPGA and is looked into
See whether operation is correct.
(4) data transmission module: the main read-write capability for completing data.After the completion of system initialization, eMMC is switched to
Data-transmission mode, expression can carry out data read-write operation.Data write phase is written as example with muti-piece, first transmission CMD23 life
Enable definition write data block number, then send the first address write of CMD25 command definition data, and then FPGA send 512B data and
Check code, eMMC, which receives after data feedback states check code and sends busy signal, enters programming phases, waits data write operation
It finishes；Data read phase sends the block number that CMD23 command definition muti-piece is read first, then sends CMD18 so that muti-piece is read as an example
Command definition reads data first address, and after waiting start bit to arrive, FPGA starts to receive data, waits the reading of USN3.0 transmission module
It takes.
(5) transmission protection is broadly divided into order transmission protection and data transmission protection, and eMMC system is by recycling lengthy and jumbled school
Code (CRC) is tested to carry out transmission protection.Wherein order transmission protection guarantees Host Command and equipment feedback by CRC7 check code
Transmission is correct on the command bus；Data transmission protection guarantees the process of data write-in and reading data by CRC16 check code
The correct transmission on the data bus of middle data block improves the reliability of system data storage and transmission.
Further, in conjunction with Fig. 6, USB3.0 transmission module includes:
FIFO consultative management module, for managing data, fifo buffer memory and the FIFO association in all channels PIPE
View layer sends and receives data, including data distribution, data transmission；
USB3.0 controller module, for handling the control of usb protocol request and FIFO functional parameter from host side
Order；
Core voltage regulator module is the power supply of USB3.0 transmission module for LDO adjuster adjustment voltage.
As a kind of specific example, USB3.0 transmission module working method is as follows:
(1) FIFO consultative management module is used to manage the data and fifo buffer memory in all channels PIPE, FIFO association
View layer sends and receives data.By FIFO consultative management part, FIFO memory can be to each channel distribution any size
Memory headroom, as long as distributing the memory headroom in all channels, size is no more than 16k byte in total.And fifo signal has a height
The ability of configuration, the resistance on line can be with multiple choices.
(2) USB3.0 protocol controller manages the data flow of equipment endpoint, provides that it is manipulated according to the agreement of USB3.0
From host side usb protocol request and FIFO functional parameter control command.
(3) LDO adjuster generates the voltage of 1V as internal core segment power supply, and outside cannot use the voltage.
The present invention solves the problems, such as the reluctant bad block management of traditional flash and ECC check, by by several
EMMC constitutes eMMC array parallel to carry out data transmission, and read or write speed and memory capacity can be doubled and redoubled, and has very strong practical
Property, and stored with eMMC array, USB3.0 is high-speed transmission interface, has stronger versatility and portability.The present invention
Data storage and Transmission system have the characteristics that small in size, capacity greatly and with roomy, realize the real-time storage and transmission of data.
Claims (10)
1. a kind of high-speed data processing and Transmission system based on eMMC array, which is characterized in that including main control chip, power supply mould
Block, clock module and the optical fiber transmission module being sequentially connected, DDR3 cache module, eMMC array memory module, USB transmission mould
Block；
The main control chip, for controlling the transmission of the data between modules；
The optical fiber transmission module, including the road N optical fiber obtain high-speed parallel for receiving optical signal and carrying out processing to optical signal
Data, and the data are transmitted to DDR3 cache module；
The DDR3 cache module, caches for the high-speed parallel data to optical fiber transmission module；
The eMMC array memory module, for storing the data of DDR3 cache module；
The USB transmission module, for the data of eMMC array memory module to be transmitted in PC machine or other boards；
The power module, for powering for the storage of entire data with Transmission system；
The clock module, when for providing work for optical fiber transmission module, DDR3 cache module and eMMC array memory module
Clock.
2. the high-speed data processing and Transmission system according to claim 1 based on eMMC array, which is characterized in that described
Main control chip uses FPGA or ARM or CPLD.
3. the high-speed data processing and Transmission system according to claim 2 based on eMMC array, which is characterized in that described
The model XC7VX690TFFG1761-2 of FPGA.
4. the high-speed data processing and Transmission system according to claim 1 based on eMMC array, which is characterized in that described
Optical fiber transmission module includes:
Optical-fibre channel module, for converting high speed serialization electric signal for the optical signal received；
High speed serialization transceiver module, for carrying out serioparallel exchange, the high speed serialization electric signal that optical-fibre channel module is exported is converted
For high-speed parallel data, and high-speed parallel data is transmitted to DDR3 cache module.
5. the high-speed data processing and Transmission system according to claim 1 based on eMMC array, which is characterized in that described
DDR3 cache module includes:
DDR3 module for reading and writing, including two groups of DDR3, cache, and will be high for the high-speed parallel data to optical fiber transmission module
Fast parallel data transmission is to eMMC array memory module；
Ping-pong operation control module is worked alternatively for controlling two groups of DDR3.
6. the high-speed data processing and Transmission system according to claim 1 based on eMMC array, which is characterized in that described
USB transmission module is USB3.0 transmission module.
7. the high-speed data processing and Transmission system according to claim 6 based on eMMC array, which is characterized in that described
USB3.0 transmission module includes:
FIFO consultative management module, for managing data, fifo buffer memory and the FIFO protocol layer in all channels PIPE
Send and receive data, including data distribution, data transmission；
USB3.0 controller module, for handling the control command of usb protocol request and FIFO functional parameter from host side；
Core voltage regulator module, for adjusting voltage as the power supply of USB3.0 transmission module.
8. the high-speed data processing and Transmission system according to claim 1 based on eMMC array, which is characterized in that described
EMMC array memory module includes eMMC controller and eMMC array, and wherein eMMC array is made of parallel several eMMC；
The eMMC controller includes:
Clock management module provides work clock for the modules for eMMC controller, and initializes for switching system
Clock and data transfer clock；
System initialization module, for carrying out electrification reset and parameter configuration for eMMC array；
Order transceiver module, for realizing sending and receiving for main control chip and the order of eMMC Inter-Array Communications and response；
Data transmission module, for realizing the read-write of eMMC array memory module；
Protective module is transmitted, including CRC7 verification, CRC16 verify, the order and data transmitted in guarded command bus are total
The data transmitted on line.
9. the high-speed data processing and Transmission system according to claim 1 based on eMMC array, which is characterized in that described
Clock module includes:
Clock chip, for generating stable clock；
Clock chip configuration module, the running parameter for configurable clock generator chip；
Reseting module, for restoring clock chip to reset condition.
10. the high-speed data processing and Transmission system according to claim 9 based on eMMC array, which is characterized in that institute
It states clock chip and specifically uses SI5338 chip.
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Application publication date: 20190503 |