CN214311487U - Short-circuit detection circuit and chip during power MOS (metal oxide semiconductor) starting - Google Patents
Short-circuit detection circuit and chip during power MOS (metal oxide semiconductor) starting Download PDFInfo
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Abstract
The embodiment of the utility model discloses a short circuit detection circuit and a chip when a power MOS is started, wherein the circuit comprises a power MOS, a sampling MOS and a current-limiting resistor; the grid of power MOS is connected with the grid of sampling MOS, sampling MOS connects current-limiting resistor, load resistance is connected to the output of power MOS, current-limiting resistor's voltage with load resistance's output end voltage is connected to the positive negative input of comparator, the output access control circuit of comparator, control circuit connects drive circuit, drive circuit connects the grid of power MOS. The utility model discloses not only reaction rate is fast, and trigger current is low, and the accuracy is high, and power loss is low moreover, and is with low costs, suitable popularization and application.
Description
Technical Field
The embodiment of the utility model provides a short-circuit detection circuit and chip when relating to the electronic circuit field especially relate to a power MOS opens.
Background
The power management chip is responsible for conversion, distribution, protection and the like of electric energy. These functions are realized without using a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), i.e., a power MOSFET (hereinafter, referred to as a power MOS). Under the action of the control circuit, the power MOS supplies electric energy to the load at the output end. For example: the chip provides safe and reliable electric energy for the output end through the power MOS. The chip is mainly used for mobile equipment. Mobile devices require frequent charging. When charging, the battery needs to be connected to the external environment, and the battery can be impacted by surge. Surge is a transient disturbance that causes transient voltages on the grid that exceed the nominal normal voltage range under certain specific conditions, and usually does not last too long, for example: millionths of a second, but possibly quite high in amplitude. In most cases, devices are easily damaged if the equipment or circuits connected to the grid are not protected from surges. Because the mobile device is battery powered, the voltage range for normal operation is within 5V. Therefore, chips used in mobile devices are usually designed by 5V semiconductor process, that is, about 5V is the highest voltage that these chips can bear. If this voltage is exceeded, the chip risks damage. When a surge occurs, the chip is impacted by far more than this safe voltage, usually more than 100V. In order to protect the internal system, a protection chip is added between the mobile device and the external interface, and the chip is connected with the external interface and the internal interface through a power MOS. When the external voltage is normal, the power MOS is conducted under the action of the control circuit, and the current is provided for the internal circuit to charge the battery or meet other electric energy requirements. When the surge occurs, the control circuit detects that the external voltage is abnormal, the power MOS is immediately turned off, and only the power MOS needs to bear high voltage after the power MOS is turned off. The channel between the inside and the outside does not exist, and the internal chip can not be influenced by the external high voltage any more, thereby achieving the purpose of protection. When the external voltage is detected to be recovered to normal, the power MOS is restarted, and the previous work is recovered.
In addition to protecting the circuits connected to the output terminals from high voltages, the chip also protects the circuits connected to the input terminals, usually the power supply. Because anomalies also occur at the output, for example: the output end is short-circuited. The reasons for short-circuiting the output terminals are many, for example: damage to the circuit to which the output is connected, or connection error of the output, etc. In the case of a short circuit at the output, if the power MOS is turned on, a large current is drawn from the power supply to which the input is connected, and the current that the power supply can supply is limited, exceeding which can result in the power supply being turned off or even damaged. In either case, all other circuits connected to the same power source are shut down, thereby shutting down the entire system.
In order to prevent an excessive current from flowing through the power MOS, the power MOS needs to detect the current passing through its channel in real time. Once an anomaly is detected, processing is done, for example: the power MOS is turned off and the system is alerted to the occurrence of an error. FIG. 1 is a diagram of a way of detecting power MOS current by a series resistor, in which the current flowing through a current sampling resistor is equal to the current flowing through a power MOS because of the series connection; through the resistor, the information of the current is converted into a voltage in proportion to the information of the current; the operational amplifier amplifies the voltage and the judgment or processing can be performed. For example: the sampling voltage can be compared with a reference voltage, if the sampling voltage exceeds the reference voltage, the current is over high, and a power MOS (metal oxide semiconductor) needs to be turned off; alternatively, the voltage may be converted to a digital signal by an analog-to-digital Converter (a/D Converter) and processed by the controller. However, the purpose of both the short-circuit detection and the current detection is to prevent current abnormality, but the requirements are not exactly the same. The accuracy of the current detection is required to be high because the detected information may also be used for loop control, for example: in the current mode DC/DC, the stability of the control loop can be ensured only if a certain relation is required to be kept between the current ramp and the slope compensation. While short circuit detection requires relatively little precision but a fast response, otherwise the current may already be too high, causing a hazard, by waiting until a short circuit condition is detected.
The above problems are urgently needed to be solved.
SUMMERY OF THE UTILITY MODEL
For solving the relevant technical problem, the embodiment of the utility model provides a short-circuit detection circuit and chip when opening power MOS solve the problem that above background art part mentioned.
In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a short circuit detection circuit when a power MOS is turned on, where the short circuit detection circuit includes a power MOS, a sampling MOS, and a current-limiting resistor; the grid of power MOS is connected with the grid of sampling MOS, sampling MOS connects current-limiting resistor, load resistance is connected to the output of power MOS, current-limiting resistor's voltage with load resistance's output end voltage is connected to the positive negative input of comparator, the output access control circuit of comparator, control circuit connects drive circuit, drive circuit connects the grid of power MOS.
Furthermore, the power MOS and the sampling MOS both adopt N-channel MOS tubes, the drain electrode of the power MOS is connected with the drain electrode of the sampling MOS, the source electrode of the power MOS is connected with the load resistor, the source electrode of the sampling MOS is connected with the current-limiting resistor, the voltage of the current-limiting resistor and the voltage of the output end of the load resistor are connected to the positive input and the negative input of the comparator, the output of the comparator is connected to the control circuit, and the control circuit adjusts the on-off state of the power MOS through the driving circuit.
Furthermore, the source electrode of the power MOS is connected with one end of the load resistor as the output end, the other end of the load resistor is grounded, the source electrode of the sampling MOS is connected with one end of the current-limiting resistor, the other end of the current-limiting resistor is grounded, the input end of the current-limiting resistor is connected with the power supply, and the power supply is connected with the drain electrode of the power MOS and the drain electrode of the sampling MOS.
Furthermore, the power MOS and the sampling MOS both adopt P-channel MOS tubes, the source electrode of the power MOS is connected with the source electrode of the sampling MOS, the drain electrode of the power MOS is connected with the load resistor, the drain electrode of the sampling MOS is connected with the current-limiting resistor, the voltage of the current-limiting resistor and the voltage of the output end of the load resistor are connected to the positive input and the negative input of the comparator, the output of the comparator is connected to the control circuit, and the control circuit adjusts the on-off state of the power MOS through the driving circuit.
Furthermore, the drain electrode of the power MOS is connected with one end of the load resistor as the output end, the other end of the load resistor is grounded, the drain electrode of the sampling MOS is connected with one end of the current-limiting resistor, the other end of the current-limiting resistor is grounded, the input end of the current-limiting resistor is connected with the power supply, and the power supply is connected with the source electrode of the power MOS and the source electrode of the sampling MOS.
Furthermore, the power MOS and the sampling MOS both adopt N-channel MOS tubes, the source electrode of the power MOS is connected with the source electrode of the sampling MOS, the drain electrode of the power MOS is connected with the load resistor, the drain electrode of the sampling MOS is connected with the current-limiting resistor, the voltage of the current-limiting resistor and the voltage of the output end of the load resistor are connected to the positive input and the negative input of the comparator, the output of the comparator is connected to the control circuit, and the control circuit adjusts the on-off state of the power MOS through the driving circuit.
Furthermore, the drain electrode of the power MOS is connected with one end of the load resistor as the output end, the other end of the load resistor is connected with the power supply, the drain electrode of the sampling MOS is connected with one end of the current-limiting resistor, the other end of the current-limiting resistor is connected with the power supply, the input end of the current-limiting resistor is connected with the ground, and the source electrode of the power MOS is connected with the source electrode of the sampling MOS and then is grounded.
In a second aspect, the embodiment of the present invention further provides a chip, which employs the short circuit detection circuit provided by the above embodiment when the power MOS is turned on.
The utility model discloses not only reaction rate is fast, and trigger current is low, and the accuracy is high, and power loss is low moreover, and is with low costs, suitable popularization and application.
Drawings
In order to more clearly illustrate and understand the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the background and embodiments of the present invention will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
FIG. 1 is a schematic diagram of series resistance sensing power MOS current;
fig. 2 is a schematic diagram of a short circuit detection circuit when a power MOS is turned on based on an N-channel MOS according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a short circuit detection circuit when a power MOS is turned on based on a P-channel MOS according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a short circuit detection circuit when the load resistor is connected between the power supply and the output end and the N-channel power MOS is turned on according to an embodiment of the present invention;
fig. 5A and 5B are diagrams of computer simulation results provided by the embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and technical effects achieved by the present invention more clear, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
Example one
The embodiment provides a short-circuit detection circuit when a power MOS is started, which comprises a power MOS, a sampling MOS and a current-limiting resistor; the grid of power MOS is connected with the grid of sampling MOS, sampling MOS connects current-limiting resistor, load resistance is connected to the output of power MOS, current-limiting resistor's voltage with load resistance's output end voltage is connected to the positive negative input of comparator, the output access control circuit of comparator, control circuit connects drive circuit, drive circuit connects the grid of power MOS. The power MOS and the sampling MOS adopt MOS tubes of the same type, namely the power MOS and the sampling MOS are both N-channel MOS tubes or both P-channel MOS tubes, and the power MOS and the sampling MOS preferably have the MOS tubes with the same electrical characteristics, and the difference between the power MOS and the sampling MOS is only the size.
For example, in this embodiment, as shown in fig. 2, when the power MOS and the sampling MOS both use N-channel MOS transistors, a drain of the power MOS is connected to a drain of the sampling MOS, a source of the power MOS is connected to the load resistor, a source of the sampling MOS is connected to the current limiting resistor, a voltage of the current limiting resistor and a voltage of an output end of the load resistor are connected to a positive input and a negative input of a comparator, an output of the comparator is connected to a control circuit, and the control circuit adjusts a switching state of the power MOS through a driving circuit. Specifically, in this embodiment, the source electrode of the power MOS is connected as the output terminal to one end of the load resistor, the other end of the load resistor is grounded, the source electrode of the sampling MOS is connected to one end of the current limiting resistor, the other end of the current limiting resistor is grounded, the input terminal is connected to the power supply, and the power supply is connected to the drain electrode of the power MOS and the drain electrode of the sampling MOS.
For example, in this embodiment, as shown in fig. 3, when the power MOS and the sampling MOS both use P-channel MOS transistors, a source of the power MOS is connected to a source of the sampling MOS, a drain of the power MOS is connected to the load resistor, a drain of the sampling MOS is connected to the current limiting resistor, a voltage of the current limiting resistor and a voltage of an output end of the load resistor are connected to a positive input and a negative input of a comparator, an output of the comparator is connected to a control circuit, and the control circuit adjusts a switching state of the power MOS through a driving circuit. Specifically, in this embodiment, the drain electrode of the power MOS is connected as the output terminal to one end of the load resistor, the other end of the load resistor is grounded, the drain electrode of the sampling MOS is connected to one end of the current limiting resistor, the other end of the current limiting resistor is grounded, the input terminal is connected to the power supply, and the power supply is connected to the source electrode of the power MOS and the source electrode of the sampling MOS.
It should be noted that, in the present embodiment, the input terminal is not limited to be connected to the power supply, and the load is connected to the output terminal and the ground; as shown in fig. 4, a source of the power MOS is connected to a source of the sampling MOS, a drain of the power MOS is connected to the load resistor, a drain of the sampling MOS is connected to the current-limiting resistor, a voltage of the current-limiting resistor and a voltage of an output end of the load resistor are connected to a positive input and a negative input of a comparator, an output of the comparator is connected to a control circuit, and the control circuit adjusts a switching state of the power MOS through a driving circuit. In this embodiment, the drain of the power MOS is connected to one end of the load resistor as the output end, the other end of the load resistor is connected to the power supply, the drain of the sampling MOS is connected to one end of the current limiting resistor, the other end of the current limiting resistor is connected to the power supply, the input end is connected to the ground, and the source of the power MOS is connected to the source of the sampling MOS and then connected to the ground.
The following short circuit detection circuit when turning on the power MOS shown in fig. 2 is used to briefly introduce the working principle of the present invention as follows:
since the sampling MOS does not need to flow a large current, the device area is usually much smaller than that of the power MOS, and the ratio of the two areas is:
area (power MOS)/Area (sampling MOS) K
Assuming that the source voltages of the power MOS and the sampling MOS are the same, the voltages of all the electrodes of both are the same. In this case, the current flowing also remains in the same proportion as the area:
IOUT(Power MOS)/ISMPL(sampling MOS) ═ K
To make the source voltages of the power MOS and the sampling MOS the same, a load resistance (R) is appliedOUT) And a current limiting resistor (R)LMT) A condition that the ratio of Area (power MOS) to Area (sampling MOS) is equivalent to the current limiting resistance (R) needs to be satisfiedLMT) And a load resistance (R)OUT) The ratio of the minimum allowable load resistance values. Equivalent R at short circuitOUTIs very small. This permissible minimum load resistance value ROUTReferred to as RSHORT. If R isLMTSatisfies the following conditions:
RLMT＝RSHORT*K
current-limiting resistorVoltage (V) onLMT) And the voltage (V) across the load resistorOUT) The following are satisfied:
RLMT*ISMPL＝RSHORT*IOUT
this means that, as long as according to RSHORTSelecting the corresponding RLMTIt is possible to make the source voltages of the power MOS and the sampling MOS the same. That is, RLMTRepresents the lowest allowable voltage, which can be used as a reference voltage for short circuit determination. If the load is within the normal range, i.e. ROUTGreater than RSHORT，RLMTAnd ROUTThe voltage of (a) satisfies:
RLMT*ISMPL<ROUT*IOUT
the comparator outputs a normal signal to the controller, and the power MOS can be normally started. Otherwise, when the load is abnormal, ROUTLess than RSHORT，RLMTAnd ROUTThe voltage of (a) satisfies:
RLMT*ISMPL>ROUT*IOUT
the comparator outputs an abnormal signal to the controller and turns off the power MOS.
The short-circuit detection circuit when opening power MOS that this embodiment provided not only reaction rate is fast, and trigger current is low, and the accuracy is high, and power loss is low moreover, and is with low costs, specifically as follows:
I. the reaction speed is high:
in a conventional circuit for detecting a power MOS current by a series resistor, an operational amplifier is required to have a very high bandwidth. The bandwidth of an operational amplifier is an important indicator of its ability to handle signal variations. For a short circuit that occurs suddenly, the current increases instantaneously, with a consequent increase in the sampled voltage. However, this voltage change has a certain delay. The wider the bandwidth of the operational amplifier, the smaller the delay, and the more timely the sampling voltage can track the change of the current. Therefore, the bandwidth directly determines whether the sampled voltage output by the amplifier can reflect the voltage on the current sampling resistor in time. The present invention does not have this limitation. In specific application, the judgment speed of the comparator is required to be as high as possible, so that the controller can send out an instruction as soon as possible according to a comparison result.
Low trigger current:
the trigger current is the current flowing through the power MOS when the comparator makes a short-circuit judgment. In a conventional circuit in which a series resistor detects a power MOS current, it is considered to be a short circuit only when the current of the power MOS reaches or exceeds a preset maximum current. Therefore, the trigger current is equal to the short-circuit current. And in the utility model, the source electrodes of the power MOS and the sampling MOS are compared from the beginning of the starting. At the start of the start, the current is 0A, and the two source voltages are equal and both are 0V. Then, the power MOS and the sampling MOS are gradually turned on, the current gradually rises, and the voltages of the two sources also rise. If the power MOS is started in a short-circuit state, ROUTLess than RSHORTThe source voltage of the sampling MOS is higher than that of the power MOS in the whole process. Therefore, the comparator can make a judgment at the initial stage of the starting without waiting for the current to exceed the preset short-circuit current. Usually the current at this time, i.e. the trigger current, is much smaller than the short circuit current. The low trigger current means that dangerous conditions such as conduction at excessive currents can be avoided and the presence of dangerous conditions can be detected, which undoubtedly increases the safety of the system.
Accuracy is comparable:
in a traditional circuit for detecting power MOS current by a series resistor, the detection accuracy mainly depends on the accuracy of a sampling resistance value, the offset voltage of an operational amplifier, the offset voltage of a comparator and the accuracy of a reference voltage. The absolute value of the sampling resistor is required to be consistent under the condition of large-scale mass production and not to change along with the working environment, such as: temperature or voltage. The offset voltage of the operational amplifier can change the amplification factor of the amplifier, thereby affecting the accuracy of the sampled voltage. Also, the offset voltage also varies with temperature. Therefore, the offset voltage is required to be much smaller than the voltage drop of the sampling resistor to ensure that the influence is negligible. The influence of the accuracy of the offset voltage and the reference voltage of the comparator is the same, which causes the trigger point of the comparator to shift, resulting in errors.
And the utility model discloses in rely on the matching of electrical characteristics between sampling MOS and the power MOS, the precision of current-limiting resistance value to and the offset voltage of comparator. Like the series-connected sampling resistors, the absolute values of the current-limiting resistors are also required to be consistent in large-scale mass production and not to change with the working environment. The sampling MOS uses the same MOSFET as the power MOS to ensure the same electrical characteristics, for example: a threshold voltage. The only difference is the size. The power MOS is equivalent to a number of small MOSFETs connected in parallel to enable it to pass a larger current. In the case of mass production of MOSFETs, different batches of products have different electrical characteristics. Integrating the sampling MOS with the power MOS ensures that they are produced simultaneously and that any change in electrical characteristics will have the same effect on them, for example: if the threshold voltage varies, the amount of variation is the same and a match between the two MOSFETs can still be maintained. The comparator is used as in the circuit with the series resistor, and the influence of the offset voltage is similar, which causes the trigger point of the comparator to shift and generate errors.
Small power loss:
in the traditional circuit for detecting power MOS current by series resistance, a sampling resistor (R) is added in the current pathSMPL). The loss generated in the sampling process is
P＝IOUT*IOUT*RSMPL
Since the loss is proportional to the square of the current, the loss is extremely severe at high currents. If the loss is to be reduced, the sampling resistance value needs to be reduced. But under the same current, the resistance value is reduced, and the voltage at the two ends of the resistance value is also reduced proportionally. Thus, the operational amplifier requires a lower offset voltage to keep the accuracy of the sampling voltage unaffected. This undoubtedly increases the design difficulty and cost of the operational amplifier. Therefore, the circuit with the series resistor has contradiction between power consumption and accuracy.
The device is not added on the path of the large current in the utility model. The current on the sampling MOS is much smaller than the current on the power MOS. Therefore, the power loss caused by the sampling MOS is very small, and there is little influence on the overall efficiency.
V, low cost:
the conventional circuit for detecting the power MOS current by the series resistor is very expensive if accurate and reliable current information is to be provided. The reason is that the series resistor needs to withstand the same large current as the MOSFET power tube, requiring a large area. While maintaining accuracy over a variety of temperatures and operating environments. The operational amplifier requires an ultra-low offset voltage (typically of the uV level) and is fast responding. Resistors and operational amplifiers that meet such requirements are very expensive. And the utility model discloses in, current-limiting resistor only requires the precision, and need not to bear the heavy current, and is relatively simple to the requirement of technology, for example: the Thin Film (Thin Film) resistance can meet the requirements. Furthermore, there is no operational amplifier. The whole is relatively easy to implement.
Through computer simulation, can show the utility model discloses an effect. In the simulation, the area ratio of the power MOS to the sampling MOS is 50: 1. allowable minimum load resistance RSHORT0.16 omega, corresponding to RLMTIs 8 omega. In the case of an input voltage of 4.2V, the maximum current is 26.25A. R is to beOUTSet to 0.1 Ω and 0.2 Ω, respectively, to simulate short circuit and normal start-up conditions. Simulation results show that short circuits can be detected in time. When the power MOS is turned off, the current just rises to 2.37A, which is far below the maximum allowable current, and is still within the safe range, as shown in fig. 5A, where Enable: enabling, namely starting signals; short: a short circuit detection output; VLMT: sampling a voltage; VOUT: outputting the voltage; IOUT: the output current, or just the load current. When the load is normal, the short-circuit protection cannot be triggered by mistake, the power MOS can be normally turned on, and current is output to the load, as shown in fig. 5B, the Enable: enabling, namely starting signals; short: a short circuit detection output; VLMT: sampling a voltage; VOUT: outputting the voltage; IOUT: the output current, or just the load current.
Example two
The present embodiment provides a chip, and the chip adopts the short circuit detection circuit when the power MOS is turned on provided in the second embodiment. It should be noted that the chip may be, but is not limited to, an overvoltage protection chip, and the scheme provided by this embodiment may be adopted for any chip that needs a short-circuit detection protection function.
The utility model discloses technical scheme just can judge the state of output load when the electric current is less, if the short circuit, turn-offs at once, and need not to wait to increase to the electric current and move again when very big, has increased the security level of system. The utility model discloses not only reaction rate is fast, and trigger current is low, and the accuracy is high, and power loss is low moreover, and is with low costs, suitable popularization and application.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (8)
1. A short circuit detection circuit when starting power MOS is characterized in that the circuit comprises a power MOS, a sampling MOS and a current-limiting resistor; the grid of power MOS is connected with the grid of sampling MOS, sampling MOS connects current-limiting resistor, load resistance is connected to the output of power MOS, current-limiting resistor's voltage with load resistance's output end voltage is connected to the positive negative input of comparator, the output access control circuit of comparator, control circuit connects drive circuit, drive circuit connects the grid of power MOS.
2. The short-circuit detection circuit when turning on the power MOS as claimed in claim 1, wherein the power MOS and the sampling MOS both employ N-channel MOS transistors, a drain of the power MOS is connected to a drain of the sampling MOS, a source of the power MOS is connected to the load resistor, a source of the sampling MOS is connected to the current limiting resistor, a voltage of the current limiting resistor and a voltage of an output end of the load resistor are connected to positive and negative inputs of a comparator, an output of the comparator is connected to a control circuit, and the control circuit adjusts a switching state of the power MOS through a driving circuit.
3. The short circuit detection circuit when turning on the power MOS as claimed in claim 2, wherein a source of the power MOS is connected as an output terminal to one end of the load resistor, the other end of the load resistor is grounded, a source of the sampling MOS is connected to one end of the current limiting resistor, the other end of the current limiting resistor is grounded, an input terminal is connected to a power supply, and the power supply is connected to a drain of the power MOS and a drain of the sampling MOS.
4. The short-circuit detection circuit when turning on the power MOS as claimed in claim 1, wherein the power MOS and the sampling MOS both employ P-channel MOS transistors, a source of the power MOS is connected to a source of the sampling MOS, a drain of the power MOS is connected to the load resistor, a drain of the sampling MOS is connected to the current limiting resistor, a voltage of the current limiting resistor and a voltage of an output end of the load resistor are connected to positive and negative inputs of a comparator, an output of the comparator is connected to a control circuit, and the control circuit adjusts a switching state of the power MOS through a driving circuit.
5. The short circuit detection circuit when turning on the power MOS as claimed in claim 4, wherein a drain of the power MOS is connected as an output terminal to one end of the load resistor, the other end of the load resistor is grounded, a drain of the sampling MOS is connected to one end of the current limiting resistor, the other end of the current limiting resistor is grounded, an input terminal is connected to a power supply, and the power supply is connected to a source of the power MOS and a source of the sampling MOS.
6. The short-circuit detection circuit when turning on the power MOS as claimed in claim 1, wherein the power MOS and the sampling MOS both employ N-channel MOS transistors, a source of the power MOS is connected to a source of the sampling MOS, a drain of the power MOS is connected to the load resistor, a drain of the sampling MOS is connected to the current limiting resistor, a voltage of the current limiting resistor and a voltage of an output end of the load resistor are connected to positive and negative inputs of a comparator, an output of the comparator is connected to a control circuit, and the control circuit adjusts a switching state of the power MOS through a driving circuit.
7. The short circuit detection circuit when turning on the power MOS as claimed in claim 6, wherein a drain of the power MOS is connected as an output terminal to one end of the load resistor, another end of the load resistor is connected to a power supply, a drain of the sampling MOS is connected to one end of the current limiting resistor, another end of the current limiting resistor is connected to the power supply, an input terminal is connected to ground, and a source of the power MOS is connected to the source of the sampling MOS and then connected to ground.
8. A chip characterized in that it employs the short-circuit detection circuit when turning on a power MOS of one of claims 1 to 7.
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Address after: Building 4 (8th and 9th floor), No. 5 Chuangzhi Road, Tianning District, Changzhou City, Jiangsu Province, 213000 Patentee after: Jiangsu Yingneng Microelectronics Co.,Ltd. Address before: 213022 building 8-5, Huashan Middle Road, Xinbei District, Changzhou City, Jiangsu Province Patentee before: JIANGSU APPLIED POWER MICROELECTRONICS Co.,Ltd. |
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