CN214279984U - 一种SiC基纳米尺度肖特基势垒场效应晶体管 - Google Patents

一种SiC基纳米尺度肖特基势垒场效应晶体管 Download PDF

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CN214279984U
CN214279984U CN202022397823.6U CN202022397823U CN214279984U CN 214279984 U CN214279984 U CN 214279984U CN 202022397823 U CN202022397823 U CN 202022397823U CN 214279984 U CN214279984 U CN 214279984U
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sic
schottky barrier
grid
field effect
electrode
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谢海情
蔡稀雅
范志强
刘刚
崔凯月
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Changsha University of Science and Technology
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

本发明公开了一种SiC基纳米尺度肖特基势垒场效应晶体管,其结构包括源、漏电极,栅电极,氧化层以及中间沟道散射区域。其中,源、漏电极采用二维金属相二硫化钼(MoS2)材料;栅极采用双栅结构,分为顶栅和背栅;顶栅和背栅与衬底沟道之间均包含一个氧化层。本发明采用二维SiC材料作为衬底,二维MoS2材料作为源、漏电极,与衬底材料形成肖特基势垒接触;双栅结构增强栅极对沟道的控制能力,有效解决沟道长度缩小至10nm以下时,短沟道效应和量子效应引起的器件性能缺陷。当沟道长度小于5.1nm时,器件关态电流小于0.1µA/µm,实现正常关断;开态电流不小于940µA/µm,满足国际半导体技术路线图(ITRS)的高性能要求。

Description

一种SiC基纳米尺度肖特基势垒场效应晶体管
技术领域
本发明涉及纳米尺度场效应晶体管技术领域,特别涉及一种SiC基纳米尺度肖特基势垒场效应晶体管。
背景技术
集成电路发展一直遵循摩尔定律。随着器件特征尺寸不断减小,传统硅基场效应晶体管作为集成电路的核心器件已经达到其物理极限。出现的短沟道效应、量子效应等,严重影响器件性能,导致器件无法正常工作。采用高K栅绝缘层、FinFET结构和纳米管等材料的场效应晶体管,工艺实现成本高。而以石墨烯、过渡金属硫化物、黑磷为代表的二维材料具有厚度很薄、表面光滑平整、弯曲性好等优点,已成为新一代电子器件的理想沟道材料。但当沟道长度尺寸减小至5.1nm时,大部分基于上述二维材料的场效应晶体管无法满足国际半导体技术路线图(International Technology Roadmap for Semiconductors,ITRS)的高性能要求。
发明内容
针对上述问题,本发明的目的在于采用宽禁带的二维SiC材料作为场效应晶体管的沟道材料,以解决沟道长度减小到5.1nm及以下时,场效应晶体管的性能缺陷,达到ITRS的高性能要求。
为了解决上述技术问题,本发明采用的技术方案为:一种SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:包括源、漏电极,栅电极,氧化层以及中间沟道散射区域。其中,源、漏电极为金属相单层MoS2材料,栅极采用双栅结构,分为顶栅和背栅两部分,顶栅和背栅与中间沟道散射区域之间均包含一个氧化层;
优选地,所述栅极和沟道长度为5.1nm、4.1nm和3.1nm。
优选地,所述氧化层厚度为0.41nm。
优选地,所述中间沟道散射区域的材料为二维SiC材料。
优选地,所述源、漏电极采用二维金属相MoS2材料。
优选地,所述源、漏电极与衬底二维SiC材料形成肖特基势垒接触。
本发明的SiC基纳米尺度肖特基势垒场效应晶体管具有下述优点:
1)宽禁带二维材料SiC具有熔点高、耐击值高、导热性能好、抗氧化能力强等优良特性,可以满足现代半导体器件发展的新要求。
2)器件的栅极长度减小为5.1nm、4.1nm和3.1nm时,开态电流不小于940μA/μm,满足ITRS的高性能要求。
3)源、漏电极为二维金属相MoS2材料,可极大减小器件尺寸,从而大幅度提升芯片的集成度。
附图说明
图1为本发明实施例的剖视结构示意图。
图2为本发明实施例的俯视结构示意图。
具体实施方式
如图1和图2所示,本实施例的SiC基纳米尺度肖特基势垒场效应晶体管包括源、漏电极,栅极,氧化层以及中间沟道散射区域。所述源、漏电极为二维金属相MoS2材料,所述栅极采用双栅结构,增强栅极对沟道的控制能力,分为顶栅和背栅两部分,所述顶栅和背栅与中间沟道散射区域之间均包含一个氧化层,所述中间沟道散射区域的材料采用的是宽禁带的二维SiC材料,SiC六边形晶格的布拉菲晶格矢量的大小为3.071Å,Si-C键长为1.773Å,所述源极和漏极之间的偏压为V DS,栅极电压为V GS, Z方向为电子输运方向。
本实施例中,栅极和沟道的长度为5.1nm、4.1nm和3.1nm。
本实施例中,氧化层厚度为0.41nm。
本实施例中,中间沟道散射区域的材料为二维SiC材料。
本实施例中,采用二维金属相MoS2材料作为源、漏电极。
本实施例中,源、漏电极与衬底二维SiC材料形成肖特基势垒接触。
以上所述仅是本发明的优选实施方式,本发明的保护范围并不仅局限于上述实施例,凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理前提下的若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (6)

1.一种SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:包括源、漏电极,栅电极,氧化层以及中间沟道散射区域;其中,源、漏电极为金属相单层MoS2材料,栅极采用双栅结构,分为顶栅和背栅两部分,顶栅和背栅与中间沟道散射区域之间均包含一个氧化层。
2.根据权利要求1所述的SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:所述栅极和沟道长度为5.1 nm、4.1nm和3.1nm。
3.根据权利要求1所述的SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:所述氧化层厚度为0.41 nm。
4.根据权利要求1所述的SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:所述中间沟道散射区域的材料为二维SiC材料。
5.根据权利要求1所述的SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:所述源、漏电极采用二维金属相MoS2材料。
6.根据权利要求5所述的SiC基纳米尺度肖特基势垒场效应晶体管,其特征在于:所述源、漏电极与衬底二维SiC材料形成肖特基势垒接触。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4199115A1 (en) * 2021-12-17 2023-06-21 IMEC vzw Transistor with low parasitic capacitance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4199115A1 (en) * 2021-12-17 2023-06-21 IMEC vzw Transistor with low parasitic capacitance

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