CN214226479U

CN214226479U - GIP circuit for optimizing display effect

Info

Publication number: CN214226479U
Application number: CN202120069380.XU
Authority: CN
Inventors: 谢建峰
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2021-01-12
Filing date: 2021-01-12
Publication date: 2021-09-17
Anticipated expiration: 2031-01-12

Abstract

The utility model discloses a GIP circuit of optimizing display effect, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10, transistor T11, transistor T12, transistor T13, transistor T14 and electric capacity; a control end of the transistor T1 is connected with the gate line G (n-4), an input end of the transistor T2 is connected with the voltage signal VGH, a control end of the transistor T3 is connected with the clock signal CK (n), an input end of the transistor T4 is connected with the clock signal CKn, an output end of the transistor T6 is connected with the voltage signal VGL, the transistor T7 is connected with the voltage signal VGL, the transistor T8 is connected with the gate line G (n +4), and the transistor T9 is connected with the clock signal CK (n + 4); according to the technical scheme, leakage currents of the transistor T5, the transistor T8 and the transistor T12 are suppressed, so that no leakage current exists at a Q point, and the output waveform of the gate line G (n) is not distorted.

Description

GIP circuit for optimizing display effect

Technical Field

The utility model relates to a display screen technical field especially relates to a GIP circuit of optimizing display effect.

Background

In recent years, the display panel has been diversified, and the display panel is developed toward light weight, thinness, low power consumption and low cost due to diversified applications and customer demands of the product.

In order to reduce the manufacturing cost of the display Panel and achieve the purpose of narrow bezel, a Gate In Panel (GIP) technology is usually adopted in the manufacturing process, and a Gate circuit (i.e., GIP circuit) is directly integrated on the flat Panel display Panel. The output waveform of the GIP circuit is susceptible to leakage of the transistor, resulting in a situation where the output waveform of the GIP circuit is distorted. The distorted output waveform may cause problems in turning on and off transistors in a display area within the display panel, thereby causing display anomalies in the display panel.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide a GIP circuit with an optimized display effect, which solves the problem that the output waveform of the GIP circuit is susceptible to the leakage of the transistor.

To achieve the above object, the present embodiment provides a GIP circuit that optimizes display effects, including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, and a capacitor;

a control terminal of the transistor T1 is connected to the gate line G (n-4), an input terminal of the transistor T1 is connected to the voltage signal VGH, and an output terminal of the transistor T1 is connected to a control terminal of the transistor T2, a control terminal of the transistor T4, an input terminal of the transistor T5 and a control terminal of the transistor T6;

the input end of the transistor T2 is connected with a voltage signal VGH, the output end of the transistor T2 is connected with a line connecting the input end of the transistor T10 and the output end of the transistor T5, and the output end of the transistor T2 is also connected with a line connecting the output end of the transistor T8 and the input end of the transistor T11;

the control end of the transistor T3 is connected with a clock signal CK (n), the input end of the transistor T3 is connected with a voltage signal VGH, and the output end of the transistor T3 is connected with the control end of the transistor T5, the input end of the transistor T6, the control end of the transistor T7 and the control end of the transistor T10;

the input end of the transistor T4 is connected to the clock signal CKn, and the output end of the transistor T4 is connected to the input end of the transistor T7 and the gate line G (n);

the first plate of the capacitor is connected with the control end of the transistor T4, and the second plate of the capacitor is connected with a line between the output end of the transistor T4 and the input end of the transistor T7;

the output end of the transistor T6 is connected with a voltage signal VGL, and the output end of the transistor T7 is connected with the voltage signal VGL;

the control terminal of the transistor T8 is connected to the gate line G (n +4), and the input terminal of the transistor T8 is connected to the line connecting the control terminal of the transistor T4 and the input terminal of the transistor T5;

the control end of the transistor T9 is connected with the clock signal CK (n +4), the input end of the transistor T9 is connected with the control end of the transistor T10, and the output end of the transistor T9 is connected with the voltage signal VGL;

the output end of the transistor T10 is connected with a voltage signal VGL;

the control end of the transistor T11 is connected to the gate line G (n +4), and the output end of the transistor T11 is connected to the voltage signal VGL;

the control end of the transistor T12 is connected with a clear signal CLR, the input end of the transistor T12 is connected to a line connecting the input end of the transistor T8 and the control end of the transistor T4, and the output end of the transistor T12 is connected with the input end of the transistor T13;

the control end of the transistor T13 is connected with a clear signal CLR, and the output end of the transistor T13 is connected with a voltage signal VGL;

the control end of the transistor T14 is connected with a clear signal CLR, the input end of the transistor T14 is connected with a gate line G (n), and the output end of the transistor T14 is connected with a voltage signal VGL.

Further, the GIP circuit is connected to the pixels on the display screen through the gate lines g (n).

Furthermore, the GIP circuits are plural, the pixels are plural, plural pixel arrays are arranged on the display screen, and each pixel is connected with the gate line g (n) of one circuit.

Further, the display screen is a display screen of an LCD.

Further, an input terminal of the transistor T1, an input terminal of the transistor T2, an input terminal of the transistor T3, an input terminal of the transistor T4, an input terminal of the transistor T5, an input terminal of the transistor T6, an input terminal of the transistor T7, an input terminal of the transistor T8, an input terminal of the transistor T9, an input terminal of the transistor T10, an input terminal of the transistor T11, an input terminal of the transistor T12, an input terminal of the transistor T13, and an input terminal of the transistor T14 are all drains.

Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the transistor T11, the transistor T12, the transistor T13, and the transistor T14 are all thin film transistors.

Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the transistor T11, the transistor T12, the transistor T13, and the transistor T14 are all depletion transistors.

Different from the prior art, the technical scheme inhibits the leakage current of the transistor T5, the transistor T8 and the transistor T12, so that a leakage-free path exists at a Q point, the voltage at the Q point cannot be attenuated, and the output waveform of the gate line G (n) cannot be distorted. The application provides a realize high definition's display screen's solution, can improve the display quality of display screen, promotes the impression of display screen, and then improves the competitiveness of display screen.

Drawings

Fig. 1 is a schematic structural diagram of a GIP circuit according to the present embodiment;

fig. 2 is a timing diagram of the GIP circuit according to the present embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 2, the GIP circuit for optimizing display effect of the present embodiment includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14, and a capacitor. The transistor is used as a switch for controlling the connection or disconnection of the line. The capacitor is composed of two conductors which are close to each other, a layer of non-conductive insulating medium is sandwiched between the two conductors, and the capacitor is used for storing electric charges. The control terminal of the transistor T1 is connected to the gate line G (n-4), the input terminal of the transistor T1 is connected to the voltage signal VGH, and the output terminal of the transistor T1 is connected to the control terminal of the transistor T2, the control terminal of the transistor T4, the input terminal of the transistor T5 and the control terminal of the transistor T6. The input end of the transistor T2 is connected to the voltage signal VGH, the output end of the transistor T2 is connected to a line connecting the input end of the transistor T10 and the output end of the transistor T5, and the output end of the transistor T2 is also connected to a line connecting the output end of the transistor T8 and the input end of the transistor T11. The control terminal of the transistor T3 is connected to the clock signal ck (n), the input terminal of the transistor T3 is connected to the voltage signal VGH, and the output terminal of the transistor T3 is connected to the control terminal of the transistor T5, the input terminal of the transistor T6, the control terminal of the transistor T7, and the control terminal of the transistor T10. The input terminal of the transistor T4 is connected to the clock signal CKn, and the output terminal of the transistor T4 is connected to the input terminal of the transistor T7 and the gate line g (n). The first plate of the capacitor is connected to the control terminal of the transistor T4 and the second plate of the capacitor is connected to the line between the output terminal of the transistor T4 and the input terminal of the transistor T7. The output end of the transistor T6 is connected to the voltage signal VGL, and the output end of the transistor T7 is connected to the voltage signal VGL. The control terminal of the transistor T8 is connected to the gate line G (n +4), and the input terminal of the transistor T8 is connected to a line connecting the control terminal of the transistor T4 and the input terminal of the transistor T5. The control terminal of the transistor T9 is connected to the clock signal CK (n +4), the input terminal of the transistor T9 is connected to the control terminal of the transistor T10, and the output terminal of the transistor T9 is connected to the voltage signal VGL. The output end of the transistor T10 is connected to the voltage signal VGL. The control terminal of the transistor T11 is connected to the gate line G (n +4), and the output terminal of the transistor T11 is connected to the voltage signal VGL. The control end of the transistor T12 is connected with a clear signal CLR, the input end of the transistor T12 is connected to a line connecting the input end of the transistor T8 and the control end of the transistor T4, and the output end of the transistor T12 is connected with the input end of the transistor T13. The control end of the transistor T13 is connected with a clear signal CLR, and the output end of the transistor T13 is connected with a voltage signal VGL. The control end of the transistor T14 is connected with a clear signal CLR, the input end of the transistor T14 is connected with a gate line G (n), and the output end of the transistor T14 is connected with a voltage signal VGL.

A point Q is provided at the intersection of the control terminal of the transistor T2, the input terminal of the transistor T5, and the control terminal of the transistor T4, and a point P is provided at the intersection of the output terminal of the transistor T3, the input terminal of the transistor T6, the control terminal of the transistor T5, and the control terminal of the transistor T7. The voltage at the point Q is pulled up by the transistors T1 and T4, and the voltage at the point Q is pulled down by the transistors T5, T10, T8, T11, T12, and T13. The transistor T5, the transistor T8, and the transistor T12 have leakage currents, which affect the output of the gate line g (n).

According to the technical scheme, the Qb point is arranged on a circuit from the output end of the transistor T2, and the voltage of the Qb node is introduced to inhibit the leakage current of the transistor T5, the transistor T8 and the transistor T12, so that the Q point has no leakage path, the voltage of the Q point is not attenuated, and the output waveform of the gate line G (n) is not distorted. The application provides a realize high definition's display screen's solution, can improve the display quality of display screen, promotes the impression of display screen, and then improves the competitiveness of display screen.

In the present embodiment, the GIP circuit of the present application is applied to pixels of a display panel, each pixel generally consists of three primary colors of red, blue, green (RGB), and each color on each pixel is called a "sub-pixel". The circuit is connected with pixels on the display screen through the gate lines G (n). The pixel array is arranged on the display screen. The circuit is multiple, and each pixel is connected with the gate line G (n) of one circuit. The GIP circuit is connected to the driving ic through the gate line G (n-4) and the gate line G (n + 4). The driving ic is a main part of the display panel imaging system, and integrates components such as a resistor, a regulator, a comparator, a power transistor and the like, and the driving ic mainly provides a compensation current for the pixels.

In this embodiment, the Display screen is an LCD Display screen, the LCD is a short for Liquid Crystal Display, and the chinese language is a Liquid Crystal Display. LCD display screens have the advantages of small size, low power consumption and high brightness.

In some embodiments, the display panel is an OLED display panel, the OLED is an Organic Light-Emitting Diode, and the chinese language is an Organic electroluminescent display or an Organic Light-Emitting semiconductor. The OLED display screen has the characteristics of lightness, thinness, quick response, high definition, good flexibility, high luminous efficiency and the like.

In this embodiment, a Transistor is used as a variable current switch capable of controlling an output current based on an input voltage, and the Transistor that can be used in this application is a Thin Film Transistor (TFT), a MOS Transistor (i.e., a metal-oxide-semiconductor field effect Transistor, MOSFET for short), a junction field effect Transistor, or the like. Preferably, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the transistor T11, the transistor T12, the transistor T13, and the transistor T14 are all thin film transistors.

In this embodiment, the input terminal of the transistor T1, the input terminal of the transistor T2, the input terminal of the transistor T3, the input terminal of the transistor T4, the input terminal of the transistor T5, the input terminal of the transistor T6, the input terminal of the transistor T7, the input terminal of the transistor T8, the input terminal of the transistor T9, the input terminal of the transistor T10, the input terminal of the transistor T11, the input terminal of the transistor T12, the input terminal of the transistor T13, and the input terminal of the transistor T14 are all drains. In this case, the output terminals of the 14 transistors are sources, and the control terminals of the 14 transistors are gates.

In some embodiments, an input terminal of the transistor T1, an input terminal of the transistor T2, an input terminal of the transistor T3, an input terminal of the transistor T4, an input terminal of the transistor T5, an input terminal of the transistor T6, an input terminal of the transistor T7, an input terminal of the transistor T8, an input terminal of the transistor T9, an input terminal of the transistor T10, an input terminal of the transistor T11, an input terminal of the transistor T12, an input terminal of the transistor T13, and an input terminal of the transistor T14 are all sources. In this case, the output terminals of the 14 transistors are drains, and the control terminals of the 14 transistors are gates.

The transistor of the GIP circuit may become a depletion transistor under the influence of process factors, because the depletion transistor is susceptible to leakage, and further causes an abnormality in the output waveform of the GIP circuit. In a preferred embodiment, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, the transistor T10, the transistor T11, the transistor T12, the transistor T13, and the transistor T14 are all depletion transistors.

The present embodiment further provides a GIP circuit driving method for optimizing a display effect, which is applied to the GIP circuit for optimizing a display effect according to any one of the above embodiments, and the GIP circuit driving method for optimizing a display effect includes the following steps:

at stage t1, the voltage signal VGH is written to high level, the voltage signal VGL is written to low level, the clock signal CK (n) is written to low level, the clock signal CK (n +4) is written to high level, the gate line G (n-4) is written to high level, the gate line G (n) is written to low level, and the gate line G (n +4) is written to low level.

At stage t2, the voltage signal VGH is written with a high voltage level, the voltage signal VGL is written with a low voltage level, the clock signal CK (n) is written with a high voltage level, the clock signal CK (n +4) is written with a low voltage level, the gate line G (n-4) is written with a low voltage level, the gate line G (n) is written with a high voltage level, and the gate line G (n +4) is written with a low voltage level.

At stage t3, the voltage signal VGH is written to high level, the voltage signal VGL is written to low level, the clock signal CK (n) is written to low level, the clock signal CK (n +4) is written to high level, the gate line G (n-4) is written to low level, the gate line G (n) is written to low level, and the gate line G (n +4) is written to high level.

At stage t4, voltage signal VGH is written to high level, voltage signal VGL is written to low level, clock signal CK (n) is written to high level, clock signal CK (n +4) is written to low level, gate line G (n-4) is written to low level, gate line G (n) is written to low level, and gate line G (n +4) is written to low level.

The t1 phase, t2 phase, t3 phase and t4 phase are arranged in sequence from first to second, and there is an interval between two adjacent phases, and the timing chart of these four phases is shown in fig. 2.

It should be noted that the voltage signal VGH is a dc high voltage, and the voltage signal VGH can be set to 15V (volts). The voltage signal VGL is a dc low voltage, and we can set the voltage signal VGL to-10V (volts). The high potential of the clock signal CKn and the clock signal CK (n +4) is VGH potential, and the low potential of the clock signal CKn and the clock signal CK (n +4) is VGL potential.

Vg (n) in fig. 2 indicates the potential of the gate line g (n), and the other gate lines also indicate the same.

Specifically, referring to fig. 1 and 2, the driving process of the GIP circuit is described herein:

during the period T1, the gate line G (n-4) is high, T1 is turned on, and the point Q starts to charge. Due to the action of the transistor T2 and the transistor T6, the potential at the point Qb is H (H represents VGH potential) and the potential at the point P is L (L represents VGL potential). At this time, the gate-source voltage Vgs of the transistor T5, the transistor T8, and the transistor T12 is VGL at the point P minus VGH at the point Qb, that is, the gate-source voltage Vgs of the transistor T5, the transistor T8, and the transistor T12 is P (VGL) -Qb (VGH), and the potential of the gate-source voltage Vgs is much smaller than 0 potential, so that the leakage current at the point Q is suppressed.

At the interval between the period T1 and the period T2, the gate line G (n-4) is at a low potential, the transistor T1 is in an off state, the Q point is kept in a floating state, the transistor T4 is turned on, and the gate line G (n) is also at a low potential because the Ckn is kept at a low potential.

During the period T2, the potential of the clock signal Ckn changes from low to high, and due to the capacitor C1, the potential at the point Q becomes higher due to the capacitive coupling effect, the transistor T4 is better opened, and the output waveform of the gate line g (n) is better transmitted. Since the voltage at the point Q becomes higher, the transistor T2 is also turned on better, and the potential at the point Qb is also increased. It is noted that, when the transistor T3 is turned on, the point P should be high, but since the point Q is high and the transistor T6 is turned on, the point P is still low.

At the interval between the T2 stage and the T3 stage, the potential of the clock signal Ckn changes from high to low, and at this time, due to the existence of the capacitor, the potential of the Q point changes back to the original H level due to the capacitive coupling effect, and the transistor T4 is still in an on state. At the same time, since the Q point returns to the original H level, the level of Qb also drops to the original level.

At the stage T3, when the gate line G (n +4) is at a high level, the transistor T8 and the transistor T11 are turned on, and the voltage at the point Q is discharged through this path. Since the clock signal Ckn +4 is high, the transistor T9 is turned on, and the point P is still maintained at VGL level, and the transistor T5, the transistor T10 and the transistor T7 controlled by the point P are all in the off state.

At the stage T4, when the clock signal Ckn changes from low to high, the transistor T3 is turned on, the point P changes to high due to the turning on of the transistor T3, the transistor T5, the transistor T10 and the transistor T7 are turned on, and discharge the point Q and the point g (n) of the gate line g (n), respectively, so that the output waveform of the gate line g (n) is not distorted.

The driving method maintains the voltage level of the Q point by improving the leakage path of the Q point pull-down transistor, so that the voltage of the Q point is not attenuated, the output waveform of the GIP circuit can be improved, the material cost of the GIP circuit is saved, and the display quality of the display screen is improved.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A GIP circuit for optimizing display effect is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a transistor T10, a transistor T11, a transistor T12, a transistor T13, a transistor T14 and a capacitor;

the output end of the transistor T10 is connected with a voltage signal VGL;

2. The GIP circuit for optimizing display effects of claim 1, wherein said GIP circuit is connected to pixels on a display screen via said gate lines G (n).

3. The GIP circuit for optimizing display effects of claim 2, wherein said GIP circuit comprises a plurality of GIP circuits, said plurality of pixels are arranged in an array on a display screen, each pixel is connected to a gate line G (n) of said circuit.

4. The GIP circuit for optimizing display effect of claim 2, wherein said display screen is a display screen of LCD.

5. The GIP circuit for optimizing display effects of claim 1, wherein said input terminal of said transistor T1, said input terminal of said transistor T2, said input terminal of said transistor T3, said input terminal of said transistor T4, said input terminal of said transistor T5, said input terminal of said transistor T6, said input terminal of said transistor T7, said input terminal of said transistor T8, said input terminal of said transistor T9, said input terminal of said transistor T10, said input terminal of said transistor T11, said input terminal of said transistor T12, said input terminal of said transistor T13 and said input terminal of said transistor T14 are all drains.

6. The GIP circuit for optimizing display effects of claim 1, wherein said transistor T1, said transistor T2, said transistor T3, said transistor T4, said transistor T5, said transistor T6, said transistor T7, said transistor T8, said transistor T9, said transistor T10, said transistor T11, said transistor T12, said transistor T13 and said transistor T14 are all thin film transistors.

7. The GIP circuit for optimizing display effects of claim 1, wherein said transistor T1, said transistor T2, said transistor T3, said transistor T4, said transistor T5, said transistor T6, said transistor T7, said transistor T8, said transistor T9, said transistor T10, said transistor T11, said transistor T12, said transistor T13 and said transistor T14 are all depletion transistors.