CN214225796U - Time synchronization circuit - Google Patents
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Abstract
The utility model discloses a time synchronization circuit, wherein, above-mentioned time synchronization circuit includes: a processor; a main controller; a baseboard management controller BMC chip; a logic switch; a logic clock chip; the processor is connected with the main controller, the baseboard management controller BMC chip and the logic switch respectively, and is used for receiving a first time synchronization request sent by the main controller and a second time synchronization request sent by the baseboard management controller BMC chip, and controlling the logic switch to be closed under the condition that a preset condition is met, so that the main controller and the baseboard management controller BMC chip access the clock chip connected with the logic switch in sequence.
Description
Technical Field
The utility model relates to the field of communications, particularly, relate to a time synchronization circuit.
Background
In the related art, in order to achieve time synchronization of a main controller and a Baseboard Management Controller (BMC) chip, the main controller or the BMC chip is generally adopted to be communicated with a system clock to obtain system hardware time, the main controller and the BMC are respectively connected with the system clock through a switching control module, the time of the two clocks is respectively read through hardware logic switching when the computer is started and powered on, and the time synchronization is achieved through the technical scheme that the clock of the main controller is synchronized to the BMC through hardware switching, but after the power-on time synchronization process is completed, the time of the main controller or the BMC is changed, and no way is provided for ensuring the time synchronization of the main controller and the BMC; or the main controller and the BMC are respectively provided with clock chips, the main controller software sends a request to synchronize time with the BMC, and the BMC synchronizes the time corresponding to the BMC to be the time of the main control system after receiving the request, but the scheme has time difference, and the BMC cannot actively initiate time synchronization.
Aiming at the problems that in the related art, errors exist in the time of a main controller and a Baseboard Management Controller (BMC) chip, the time is asynchronous and the like, an effective solution is not provided.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a time synchronization circuit to at least, solve the correlation technique, there is the error in the time of main control unit and base plate management controller BMC chip, the asynchronous scheduling problem of time.
According to the utility model discloses an embodiment provides a time synchronization circuit, include: a processor; a main controller; a baseboard management controller BMC chip; a logic switch; a logic clock chip; the processor is respectively connected with the main controller, the baseboard management controller BMC chip and the logic switch, and is used for receiving a first time synchronization request sent by the main controller and a second time synchronization request sent by the baseboard management controller BMC chip, and controlling the logic switch to be closed under the condition that a preset condition is met, so that the main controller and the baseboard management controller BMC chip sequentially access a clock chip connected with the logic switch.
In one exemplary embodiment, the master controller includes: first general input-output port and the general input-output port of second, just the treater with main control unit passes through respectively first general input-output port and the general input-output port of second are connected, wherein, first general input-output port be used for with main control unit's first time synchronization request send to the treater, the general input-output port of second is used for receiving the treater send with the first state response message that first time synchronization request corresponds.
In an exemplary embodiment, the BMC chip includes: the system comprises a third universal input/output port and a fourth universal input/output port, wherein the processor and the BMC chip of the substrate management controller are respectively connected through the third universal input/output port and the fourth universal input/output port, the third universal input/output port is used for sending a second time synchronization request of the BMC chip of the substrate management controller to the processor, and the fourth universal input/output port is used for receiving second state response information which is sent by the processor and corresponds to the second time synchronization request.
In an exemplary embodiment, the processor is further configured to control the main controller or the BMC chip to wait for a preset time when detecting that the clock chip is in a non-idle state, and detect the current state of the clock chip again after the preset time is reached.
In an exemplary embodiment, the processor is further configured to determine priorities of the master controller and the BMC chip if the first time synchronization request and the second time synchronization request are received simultaneously, respond to the first time synchronization request if the priority of the master controller is higher, and respond to the second time synchronization request if the priority of the BMC chip is higher.
In an exemplary embodiment, the processor is further configured to, when it is detected that the first time synchronization request or the second time synchronization request falls from a high level and first status response information corresponding to the first time synchronization request or second status response information corresponding to the second time synchronization request is a low level, not respond to the first time synchronization request or the second time synchronization request.
In an exemplary embodiment, the processor is further configured to, when it is detected that the first time synchronization request or the second time synchronization request falls from a high level, and first status response information corresponding to the first time synchronization request or second status response information corresponding to the second time synchronization request is a high level, not respond to the first time synchronization request or the second time synchronization request.
In one exemplary embodiment, the master controller includes: a first I2C bus controller slice for accessing the clock chip with the master controller and the logic switch in the pass-through.
In an exemplary embodiment, the BMC chip includes: and the second I2C bus controller chip is used for accessing the clock chip under the condition that the baseboard management controller BMC chip and the logic switch are in a passage.
In an exemplary embodiment, the clock chips are mounted separately on a separate I2C bus.
Through the utility model discloses a time synchronization circuit, processor; a main controller; a baseboard management controller BMC chip; a logic switch; a logic clock chip; wherein, the processor is respectively connected with the main controller, the baseboard management controller BMC chip and the logic switch, and is configured to receive a first time synchronization request sent by the main controller and a second time synchronization request sent by the baseboard management controller BMC chip, and control the logic switch to be turned on when a preset condition is met, so as to enable the main controller and the baseboard management controller BMC chip to sequentially access the clock chip connected with the logic switch, that is, to control the logic switch to be turned on through the processor, so as to enable the main controller and the baseboard management controller BMC chip to sequentially access the clock chip connected with the logic switch, thereby ensuring time synchronization between the main controller and the baseboard management controller BMC chip, and by adopting the above technical scheme, an error exists between the main controller and the baseboard management controller BMC chip in the related technology is solved, time asynchronization and the like.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:
fig. 1 is a block diagram of a time synchronization circuit according to an embodiment of the present invention;
fig. 2 is a diagram of hardware architecture in a time synchronization circuit according to an alternative embodiment of the present invention;
fig. 3 is a flow diagram of an access in a time synchronization circuit according to an alternative embodiment of the present invention;
fig. 4 is a flow diagram of a logic process of a processor in a time synchronization circuit in accordance with an alternative embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In the present embodiment, a time synchronization circuit is provided, and fig. 1 is a structural diagram of the time synchronization circuit according to the embodiment of the present invention, which is specifically described as follows:
a processor 10; a main controller 20; a BMC chip 30; a logic switch 40; a logic clock chip 50; the processor 10 is connected to the main controller 20, the BMC chip 30 and the logic switch 40, and configured to receive a first time synchronization request sent by the main controller 20 and a second time synchronization request sent by the BMC chip 30, and control the logic switch 40 to be closed when a preset condition is met, so that the main controller 20 and the BMC chip 30 sequentially access the clock chip 50 connected to the logic switch 40.
Through the utility model discloses a time synchronization circuit, processor; a main controller; a baseboard management controller BMC chip; a logic switch; a logic clock chip; wherein, the processor is respectively connected with the main controller, the baseboard management controller BMC chip and the logic switch, and is configured to receive a first time synchronization request sent by the main controller and a second time synchronization request sent by the baseboard management controller BMC chip, and control the logic switch to be turned on when a preset condition is met, so as to enable the main controller and the baseboard management controller BMC chip to sequentially access the clock chip connected with the logic switch, that is, to control the logic switch to be turned on through the processor, so as to enable the main controller and the baseboard management controller BMC chip to sequentially access the clock chip connected with the logic switch, thereby ensuring time synchronization between the main controller and the baseboard management controller BMC chip, and by adopting the above technical scheme, an error exists between the main controller and the baseboard management controller BMC chip in the related technology is solved, time asynchronization and the like.
It should be noted that, the processor in the above circuit preferably selects the CPLD chip, or may be other processors that can control the logic switch to be closed or vacant, and the present invention is not limited thereto.
In an alternative embodiment, the master controller comprises: first general input-output port and the general input-output port of second, just the treater with main control unit passes through respectively first general input-output port and the general input-output port of second are connected, wherein, first general input-output port be used for with main control unit's first time synchronization request send to the treater, the general input-output port of second is used for receiving the treater send with the first state response message that first time synchronization request corresponds.
That is, the processor is connected to two general purpose input output pins (GPIOs) of the host controller. One universal input/output port sends a first time synchronization request to the processor, and the other universal input/output port receives first status response information given by the processor, wherein the universal input/output port sending the first time synchronization request to the processor is a first universal input/output port, and the universal input/output port receiving the first status response information corresponding to the first time synchronization request sent by the processor is a second universal input/output port.
In an optional embodiment, the BMC chip includes: the system comprises a third universal input/output port and a fourth universal input/output port, wherein the processor and the BMC chip of the substrate management controller are respectively connected through the third universal input/output port and the fourth universal input/output port, the third universal input/output port is used for sending a second time synchronization request of the BMC chip of the substrate management controller to the processor, and the fourth universal input/output port is used for receiving second state response information which is sent by the processor and corresponds to the second time synchronization request.
In short, the processor is connected with two general input/output port pins (GPIO) of the BMC chip of the BMC, one general input/output port sends a second time synchronization request to the processor, and the other general input/output port receives second status response information given by the processor, where the general input/output port sending the second time synchronization request to the processor is a third general input/output port, and the general input/output port receiving the second status response information corresponding to the second time synchronization request sent by the processor is a fourth general input/output port.
In an exemplary embodiment, the clock chips are mounted separately on a separate I2C bus.
In order to better understand the structure of the time synchronization circuit, the following describes a hardware structure diagram of the time synchronization circuit with reference to an alternative embodiment, but the hardware structure diagram is not limited to the technical solution of the embodiment of the present invention.
In this alternative embodiment, a hardware structure of a time synchronization circuit is provided, and fig. 2 is a hardware structure diagram of the time synchronization circuit according to the alternative embodiment of the present invention, where the hardware structure diagram is specifically described as follows:
in this alternative embodiment, the hardware structure of the time synchronization circuit includes: the system comprises a CPLD (complex programmable logic device) chip (equivalent to the processor in the embodiment), a server master control system (equivalent to the master controller in the embodiment), a baseboard management controller BMC chip, a logic switch and an RTC clock chip, wherein one clock chip is used, and the master controller and the baseboard management controller BMC chip share the clock chip in a time-sharing manner, so that the time synchronization of the master controller and the baseboard management controller BMC chip is ensured, in addition, the master controller and the baseboard management controller BMC chip are controlled to access the clock chip by using one CPLD (complex programmable logic device) chip, and the RTC clock chip is mounted on a single I2C bus in order to avoid influencing other devices.
And the CPLD (complex programmable logic device) chip is respectively connected with two GPIO (general purpose input/output) pins of the server main control system and the baseboard management controller BMC chip. One of the GPIOs (general purpose input output ports) serves as an access Request signal (corresponding to the first time synchronization Request and the second time synchronization Request in the above-described embodiment) (Request), and the other GPIO (general purpose input output port) receives a response signal (corresponding to the first status response information and the second status response information in the above-described embodiment) (Ack) transmitted by the CPLD. The CPLD sends a signal to the logic switch for controlling the switching of the I2C bus. When the server main control system and the baseboard management controller BMC chip do not send out the access request, the request signal line is in low level, and the response signal is in low level.
In an exemplary embodiment, the processor is further configured to control the main controller or the BMC chip to wait for a preset time when detecting that the clock chip is in a non-idle state, and detect the current state of the clock chip again after the preset time is reached.
That is to say, at main control unit or baseboard management controller BMC chip is behind the transmission time synchronization request, whether the detection clock chip is in non-idle state, is in under the condition of non-idle state at the clock chip, main control unit or baseboard management controller BMC chip waits for the preset time, and the preset time can be 5ms, 10ms etc. the utility model discloses do not limit to this, wait for after the preset time, whether the detection clock chip is in non-idle state once more.
Further, after the master controller or the BMC chip sends the time synchronization request, it may wait for a second preset time, and then detect whether the clock chip is in a non-idle state, and when the clock chip is in the non-idle state, the master controller or the BMC chip may also select whether to continue to wait for the request clock chip, and after selecting to continue to wait for the request clock chip, the master controller or the BMC chip waits for the preset time, and the preset time may be 5ms, 10ms, etc., the utility model discloses not limit this, after waiting for the preset time, it is in the non-idle state again to detect whether the clock chip is, if the master controller or the BMC chip selects not to continue to wait, the request is ended.
In an exemplary embodiment, the processor is further configured to determine priorities of the master controller and the BMC chip if the first time synchronization request and the second time synchronization request are received simultaneously, respond to the first time synchronization request if the priority of the master controller is higher, and respond to the second time synchronization request if the priority of the BMC chip is higher.
That is, the master controller and the BMC chip have priorities, and in a case where the master controller and the BMC chip simultaneously send the first time synchronization request and the second time synchronization request to the processor, in a case where the priority of the master controller is higher, the processor responds to the first time synchronization request, and in a case where the priority of the BMC chip is higher, the processor responds to the second time synchronization request. It should be noted that, the processor may set the priority of the main controller and the BMC chip of the baseboard management controller, and the processor determines whether to respond to the first time synchronization request or the second time synchronization request according to the priority.
In an exemplary embodiment, the processor is further configured to, when it is detected that the first time synchronization request or the second time synchronization request falls from a high level and first status response information corresponding to the first time synchronization request or second status response information corresponding to the second time synchronization request is a low level, not respond to the first time synchronization request or the second time synchronization request.
In an exemplary embodiment, the processor is further configured to, when it is detected that the first time synchronization request or the second time synchronization request falls from a high level, and first status response information corresponding to the first time synchronization request or second status response information corresponding to the second time synchronization request is a high level, not respond to the first time synchronization request or the second time synchronization request.
In short, when the processor detects that the first time synchronization request or the second time synchronization request falls from a high level, it may be understood that the first time synchronization request or the second time synchronization request changes from a high level to a low level, and does not respond to the first time synchronization request or the second time synchronization request, specifically, when the processor detects that the first time synchronization request or the second time synchronization request falls from a high level, and the first status response information corresponding to the first time synchronization request or the second status response information corresponding to the second time synchronization request is a low level, it indicates that the BMC main controller and the BMC chip actively cancel the time synchronization request, and the processor does not respond to the first time synchronization request or the second time synchronization request; and the processor indicates that the access of the main controller and the Baseboard Management Controller (BMC) chip to the time chip is finished and the processor changes the response information to the low level to indicate that the next time synchronization request can be processed when the processor detects that the first time synchronization request or the second time synchronization request starts to fall from the high level and the first state response information corresponding to the first time synchronization request or the second state response information corresponding to the second time synchronization request is the high level.
In one exemplary embodiment, the master controller includes: a first I2C bus controller slice for accessing the clock chip with the master controller and the logic switch in the pass-through.
That is, with the master controller and the logic switch in path, the master controller accesses the clock chip through the first I2C bus controller slice.
In an exemplary embodiment, the BMC chip includes: and the second I2C bus controller chip is used for accessing the clock chip under the condition that the baseboard management controller BMC chip and the logic switch are in a passage.
That is, when the BMC chip and the logic switch are connected, the BMC chip accesses the clock chip through the second I2C bus controller chip.
For better understanding of the time synchronization circuit, the structure of the time synchronization circuit is described below with reference to an alternative embodiment, but the invention is not limited to the technical solution of the embodiment of the invention.
Fig. 3 is a flowchart of access in a time synchronization circuit according to an alternative embodiment of the present invention, and as shown in fig. 3, the access in the time synchronization circuit can be implemented by the following steps:
step S301: when a server main control system (equivalent to the main controller in the above embodiment) or a BMC chip (equivalent to the BMC chip in the above embodiment) needs to access a clock chip;
step S302: a request signal (equivalent to the first time synchronization request or the second time synchronization request in the above embodiment) of the server master control system or the BMC chip is pulled high, which may be understood as that the request signal is changed into a high-level request signal, and the request signal is sent to the CPLD;
step S303: counting 5ms, detecting the state of the response signal (corresponding to the first status response message or the second status response message in the above embodiment);
the states of the response signal include: low level and high level.
Step S304: judging whether the response signal is pulled up, wherein the answer signal is understood to be a high-level answer signal, if the answer signal is pulled up, executing step S306, and if the answer signal is not pulled up, executing step S305;
step S305: judging whether to continue waiting for access, executing step S303 under the condition of continuing waiting for access, and executing step S308 under the condition of not continuing waiting for access;
step S306: the control logic switch is closed to complete corresponding I2C bus switching, then the corresponding response signal is pulled high to indicate that the corresponding server main control system or BMC is authorized to access, and the clock chip is read and written;
step S307: the server master control system or the BMC pulls down the request signal and releases the request signal;
step S308: waiting for the CPLD to pull down the response signal, and pulling down the request signal of the server main control system or the BMC to indicate that the server main control system or the BMC finishes the reading and writing of the clock chip;
step S309: and (6) ending.
Fig. 4 is a flowchart of logic processing of a processor in a time synchronization circuit according to an alternative embodiment of the present invention, and as shown in fig. 4, the process of logic processing of a processor in a time synchronization circuit is as follows:
step S401: starting;
step S402: reading the state of the response signal (corresponding to the first state response information or the second state response information in the above-described embodiment);
step S403: detecting whether a response signal is pulled high; if the answer signal is pulled high, it indicates that there is read-write access in progress, execute step S405; otherwise, go to step S404;
step S404: delaying for 5ms, and executing step S408;
step S405: detecting whether the corresponding request signal is pulled high; if the request signal (corresponding to the first time synchronization request or the second time synchronization request in the above embodiment) is at a high level, indicating that the corresponding access is in progress, step S406 is executed; if the request signal is low, go to step S407;
step S406: after waiting for 5ms, executing step S405;
step S407: after reading and writing, switching the logic switch to the vacant position;
step S408: recovering the state of the response signal, namely pulling down the corresponding response signal, and enabling the clock chip to be in an idle state when the clock chip is accessed, wherein if the response signal is not pulled up, the clock chip is not accessed;
step S409: when the clock chip access is in an idle state, reading the access request signal state;
step S410: judging whether a signal of a server main control system or a BMC access request is pulled up or not, sending an access request, if the signal of the equipment access request is pulled up, executing a step S412, otherwise, executing a step S411;
step S411: delaying for 5ms, and executing the step S409;
step S412: judging whether the server main control system and the BMC send request signals at the same time, if so, executing the step S413, otherwise, executing the step S414;
step S413: the CPLD carries out arbitration, sets the priority of the master control system and responds to the request signal of the server master control system;
step S414: responding to the corresponding request signal, switching the CPLD to switch and switching the I2C signal to the corresponding server master control system;
step S415: raising the response signal of the server main control system;
step S416: the server main control system starts reading and writing and waits for 5 ms;
step S417: judging whether to quit, if so, executing step S418, and if not, executing step S402;
step S418: and (6) ending.
It should be noted that, the CPLD switches on and off, switches the I2C signal to the corresponding requester, and then pulls up the corresponding reply status signal to inform the requester that authorization has been granted. Waiting for detecting the state of the request signal, when detecting that the request signal starts to drop from a high level, if the corresponding response signal is a low level, indicating that the request is the active withdrawal of the request party, and not processing. If the request signal falls, the corresponding reply signal is a high level signal, indicating that the access of the requester is finished, and the CPLD should be responsible for restoring the reply signal to low, indicating that the bus is empty, so that the next request can be processed. And the logic switch controls the server main control system or the BMC to access the clock chip under the condition of receiving the control signal of the CPLD. When the bus control signal is sent to the BMC, the I2C bus controller chip of the BMC accesses the clock chip, and when the bus control signal is sent to the server main control system, the I2C bus controller of the server main control system accesses the clock chip.
Through the scheme, only one clock chip hung on the I2C bus is used by the server main control system and the BMC, hardware resources are saved, the time consistency of the acquisition of the server main control system and the BMC is ensured, the time-sharing clock chip is realized through the switching of the CPLD, when the server main control system or the BMC needs to access the clock chip, an access request is firstly sent to the CPLD, the arbitration is carried out, a signal is sent to the logic switch, the I2C bus main controller is switched, and the clock chip can be accessed after the server main control system or the BMC acquires the response of the access authority. If the request signal needs to be actively released after the access of the server master control system or the BMC is finished, after one time of the server master control system and the BMC is reset, the clock synchronization is guaranteed without mutual communication through software.
Through the utility model discloses a time synchronization circuit, processor; a main controller; a baseboard management controller BMC chip; a logic switch; a logic clock chip; wherein, the processor is respectively connected with the main controller, the baseboard management controller BMC chip and the logic switch, and is configured to receive a first time synchronization request sent by the main controller and a second time synchronization request sent by the baseboard management controller BMC chip, and control the logic switch to be turned on when a preset condition is met, so as to enable the main controller and the baseboard management controller BMC chip to sequentially access the clock chip connected with the logic switch, that is, to control the logic switch to be turned on through the processor, so as to enable the main controller and the baseboard management controller BMC chip to sequentially access the clock chip connected with the logic switch, thereby ensuring time synchronization between the main controller and the baseboard management controller BMC chip, and by adopting the above technical scheme, an error exists between the main controller and the baseboard management controller BMC chip in the related technology is solved, time asynchronization and the like.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A time synchronization circuit, comprising:
a processor; a main controller; a baseboard management controller BMC chip; a logic switch; a logic clock chip; wherein,
the processor is respectively connected with the main controller, the baseboard management controller BMC chip and the logic switch and used for receiving a first time synchronization request sent by the main controller and a second time synchronization request sent by the baseboard management controller BMC chip and controlling the logic switch to be closed under the condition that preset conditions are met so as to realize that the main controller and the baseboard management controller BMC chip sequentially access clock chips connected with the logic switch.
2. The time synchronization circuit of claim 1, wherein the master controller comprises: first general input-output port and the general input-output port of second, just the treater with main control unit passes through respectively first general input-output port and the general input-output port of second are connected, wherein, first general input-output port be used for with main control unit's first time synchronization request send to the treater, the general input-output port of second is used for receiving the treater send with the first state response message that first time synchronization request corresponds.
3. The time synchronization circuit of claim 1, wherein the Baseboard Management Controller (BMC) chip comprises: the system comprises a third universal input/output port and a fourth universal input/output port, wherein the processor and the BMC chip of the substrate management controller are respectively connected through the third universal input/output port and the fourth universal input/output port, the third universal input/output port is used for sending a second time synchronization request of the BMC chip of the substrate management controller to the processor, and the fourth universal input/output port is used for receiving second state response information which is sent by the processor and corresponds to the second time synchronization request.
4. The time synchronization circuit of claim 1, wherein the processor is further configured to control the main controller or the BMC chip to wait for a preset time when the clock chip is detected to be in a non-idle state, and detect the current state of the clock chip again after the preset time is reached.
5. The time synchronization circuit of claim 1, wherein the processor is further configured to determine a priority of the master controller and the BMC chip if the first time synchronization request and the second time synchronization request are received simultaneously, respond to the first time synchronization request if the priority of the master controller is higher, and respond to the second time synchronization request if the priority of the BMC chip is higher.
6. The time synchronization circuit of claim 1, wherein the processor is further configured to not respond to the first time synchronization request or the second time synchronization request when it is detected that the first time synchronization request or the second time synchronization request falls from a high level and first status response information corresponding to the first time synchronization request or second status response information corresponding to the second time synchronization request is a low level.
7. The time synchronization circuit of claim 1, wherein the processor is further configured to not respond to the first time synchronization request or the second time synchronization request when it is detected that the first time synchronization request or the second time synchronization request falls from a high level and first status response information corresponding to the first time synchronization request or second status response information corresponding to the second time synchronization request is a high level.
8. The time synchronization circuit of claim 1, wherein the master controller comprises: a first I2C bus controller slice for accessing the clock chip with the master controller and the logic switch in the pass-through.
9. The time synchronization circuit of claim 1, wherein the Baseboard Management Controller (BMC) chip comprises: and the second I2C bus controller chip is used for accessing the clock chip under the condition that the baseboard management controller BMC chip and the logic switch are in a passage.
10. The time synchronizing circuit according to any one of claims 1 to 9, wherein the clock chips are mounted separately on a separate I2C bus.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114115446A (en) * | 2021-11-30 | 2022-03-01 | 杭州迪普信息技术有限公司 | Method for sharing real-time clock and data processing equipment |
| CN116827475A (en) * | 2023-08-28 | 2023-09-29 | 成都秦川物联网科技股份有限公司 | Flowmeter clock synchronization method, device, equipment and medium based on Internet of things |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114115446A (en) * | 2021-11-30 | 2022-03-01 | 杭州迪普信息技术有限公司 | Method for sharing real-time clock and data processing equipment |
| CN116827475A (en) * | 2023-08-28 | 2023-09-29 | 成都秦川物联网科技股份有限公司 | Flowmeter clock synchronization method, device, equipment and medium based on Internet of things |
| CN116827475B (en) * | 2023-08-28 | 2023-11-17 | 成都秦川物联网科技股份有限公司 | Flowmeter clock synchronization method, device, equipment and medium based on Internet of things |
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