CN214203219U - Embedded FPGA storage circuit - Google Patents
Embedded FPGA storage circuit Download PDFInfo
- Publication number
- CN214203219U CN214203219U CN202120022164.XU CN202120022164U CN214203219U CN 214203219 U CN214203219 U CN 214203219U CN 202120022164 U CN202120022164 U CN 202120022164U CN 214203219 U CN214203219 U CN 214203219U
- Authority
- CN
- China
- Prior art keywords
- word line
- control end
- pmos
- memory
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses an embedded FPGA storage circuit and control method thereof, include: the CMOS memory comprises a CMOS memory topology array, a bit line array and a word line array, wherein the CMOS memory topology array comprises M rows by N columns of memories, the bit line array comprises N bit line units, and the word line array comprises M word line units; each word line unit controls a row of memories, and each bit line unit controls a column of memories; each memory comprises a transmission gate and a storage unit which are connected; the word line P control end of each word line unit is connected with the PMOS control end of the transmission gate of each memory in the row; the word line N control end of each word line unit is connected with the NMOS control end of the transmission gate of each memory in the row; the local line control end of each word line unit is connected with the storage unit control end of each memory in the row; and the bit line control end of each bit line unit is connected with the read-write control end of the transmission gate of each memory in the column.
Description
Technical Field
The utility model relates to a memory field indicates an embedded FPGA storage circuit especially.
Background
At present, more and more modules are integrated on a chip, the types of the modules are different, and the modules can be analog or digital, and the power of the modules is different. An FPGA (Field Programmable Gate Array) is also added to the integrated ranks. The FPGA has a programmable function, and can greatly improve the performance of the chip. However, it needs large area of memory and logic unit, and has very high requirements on cost, power consumption, speed and stability in design.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides an embedded FPGA storage circuit and control method thereof reduces FPGA in memory and the logical unit's consumption, improves FPGA in memory and logical unit's stability.
In order to achieve the purpose of the utility model, the utility model provides an embedded FPGA storage circuit, include: the CMOS memory comprises a CMOS memory topology array, a bit line array and a word line array, wherein the CMOS memory topology array comprises M rows by N columns of memories, the bit line array comprises N bit line units, and the word line array comprises M word line units; each word line unit controls a row of memories, and each bit line unit controls a column of memories;
each memory comprises a transmission gate and a storage unit which are connected;
the word line P control end of each word line unit is connected with the PMOS control end of the transmission gate of each memory in the row; the word line N control end of each word line unit is connected with the NMOS control end of the transmission gate of each memory in the row; the local line control end of each word line unit is connected with the storage unit control end of each memory in the row;
and the bit line control end of each bit line unit is connected with the read-write control end of the transmission gate of each memory in the column.
Preferably, the word line unit includes: a NAND gate, a NOR gate and an AND gate; two input ends of the NAND gate are respectively connected with the word line control end and the word selection end; the output end of the NAND gate is used as a word line N control end; the output end of the NAND gate is used as a word line P control end through the output of the NOT gate; two input ends of the AND gate are respectively connected with a word selection end and a local control end; the initial control end and the output end of the AND gate are used as the input ends of the NOR gate; and the output end of the NOR gate is used as a local line control end.
Preferably, the transmission gate comprises a first NMOS and a first PMOS, and a source of the first NMOS is connected to a source of the first PMOS to serve as a write data control terminal; one of the grid of the first NMOS and the grid of the first PMOS is connected with a first level, the other one is connected with a second level, and the drain of the first NMOS and the drain of the first PMOS are used as read data control ends; the grid electrode of the first PMOS is connected with the word line P control end of the corresponding word line unit; and the grid electrode of the first NMOS is connected with the word line N control end of the word line unit.
Preferably, the storage unit includes: the source electrode of the second PMOS and the source electrode of the third PMOS are respectively connected with the local line control end of the corresponding word line unit, the drain electrode of the second PMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS are connected with the write data control end of the corresponding transmission gate, and the grid electrode of the second PMOS, the grid electrode of the second NMOS and the drain electrode of the third PMOS are connected with the drain electrode of the third NMOS to serve as the output end of the memory; and the source electrode of the second NMOS and the source electrode of the third NMOS are grounded.
Preferably, the bit line unit comprises a fourth PMOS, a gate of the fourth PMOS is connected to the bit charging control terminal, and a source of the fourth PMOS serves as a read data control terminal; and the drain electrode of the fourth PMOS is connected with a power supply.
The utility model also provides a control method of embedded FPGA storage circuit, include:
when a write control signal for any row of memories is received, the word line unit of the corresponding row controls the transmission gate of the corresponding row of memories to be conducted, and the data stored in each bit line unit is transmitted to the corresponding memory unit through the transmission gate;
when a read control signal for any row of memories is received, the word line unit of the corresponding row controls the transmission gate of the corresponding row of memories to be turned on, and the data stored in the corresponding memory unit is transmitted to the corresponding bit line unit through the transmission gate.
Preferably, the output end of the memory transmits the output data to the FPGA.
Preferably, when a write control signal for any one row of the memories is received, the bit charging control terminal of the bit line unit is charged through the local line control terminal of the word line unit.
Preferably, when the word line N control terminal of the bit line unit is at a high level, the transmission gate is turned on, and when the word line N control terminal of the bit line unit is at a low level, the transmission gate is turned off.
Compared with the prior art, the utility model provides a storage circuit, low-power consumption, stability is high.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments of the present invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and not to limit the embodiments of the invention.
Fig. 1 is a schematic diagram of an embedded FPGA storage circuit according to an embodiment of the present invention;
fig. 2 is a logic diagram of a word line unit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a bit line cell logic according to an embodiment of the present invention;
FIG. 4 is a logic diagram of a memory cell according to an embodiment of the present invention
Fig. 5 is a timing diagram of write data 1 according to an embodiment of the present invention;
fig. 6 is a timing diagram of write data 0 according to an embodiment of the present invention;
fig. 7 is a timing diagram of read data 1 according to an embodiment of the present invention;
FIG. 8 is a timing diagram of read data 0 according to an embodiment of the present invention;
fig. 9 is a timing diagram of initial operation of an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
As shown in fig. 1, an embodiment of the present invention provides an embedded FPGA storage circuit, including: the CMOS memory comprises a CMOS memory topology array, a bit line array and a word line array, wherein the CMOS memory topology array comprises M rows by N columns of memories, the bit line array comprises N bit line units, and the word line array comprises M word line units; each word line unit controls a row of memories, and each bit line unit controls a column of memories;
each memory comprises a transmission gate and a storage unit which are connected;
the word line P control end of each word line unit is connected with the PMOS control end of the transmission gate of each memory in the row; the word line N control end of each word line unit is connected with the NMOS control end of the transmission gate of each memory in the row; the local line control end of each word line unit is connected with the storage unit control end of each memory in the row;
and the bit line control end of each bit line unit is connected with the read-write control end of the transmission gate of each memory in the column.
As shown in fig. 1, the embodiment of the present invention adopts the topology of M × N CMOS memory. There are M x N memory cells and M x N transmission gates in this topology. Each memory cell may store a 0 or a 1, Q being its output. The output terminal can be used to control the subsequent stage logic circuit. Each memory cell performs read and write operations through the pass gate, the bit line cell and the word line cell. The read and write operations of the memory are always operated on a word-by-word basis. Of the N words, only one word can be read or written at a time. But the output Q of the memory cell is always an active output, driving the subsequent logic circuit all the time. This is also the most important difference between the memory circuit of the embodiment of the present invention and the conventional memory structure.
As shown in fig. 2, in the embodiment of the present invention, the word line unit includes: a NAND gate, a NOR gate and an AND gate; two input ends of the NAND gate are respectively connected with the word line control end and the word selection end; the output end of the NAND gate is used as a word line N control end; the output end of the NAND gate is used as a word line P control end through the output of the NOT gate; two input ends of the AND gate are respectively connected with a word selection end and a local control end; the initial control end and the output end of the AND gate are used as the input ends of the NOR gate; and the output end of the NOR gate is used as a local line control end.
As shown in fig. 3, in the embodiment of the present invention, the transmission gate includes a first NMOS (101) and a first PMOS (201), and a source of the first NMOS (101) is connected to a source of the first PMOS (201) to serve as a write data control terminal; one of the grid of the first NMOS (101) and the grid of the first PMOS (201) is connected with a first level, the other one is connected with a second level, and the drain of the first NMOS (101) and the drain of the first PMOS (201) are used as read data control terminals; the grid electrode of the first PMOS (201) is connected with the control end of the word line P of the corresponding word line unit; the grid electrode of the first NMOS (101) is connected with the word line N control end of the word line unit.
In an embodiment of the present invention, one of the first NMOS gate and the first PMOS gate is a positive logic, and the other is a negative logic, and one is connected to a high and the other is connected to a low.
As shown in fig. 4, in the embodiment of the present invention, the storage unit includes: a second PMOS (202), a third PMOS (203), a second NMOS (102) and a third NMOS (103), wherein the source of the second PMOS (202) and the source of the third PMOS (203) are respectively connected with the local line control end of the corresponding word line unit, the drain of the second PMOS (202), the drain of the second NMOS (102), the gate of the third PMOS (203) and the gate of the third NMOS (103) are connected with the write data control end of the corresponding transmission gate, and the gate of the second PMOS (202), the gate of the second NMOS (102), the drain of the third PMOS (203) and the drain of the third NMOS (103) are connected as the output end of the memory; the source of the second NMOS (102) and the source of the third NMOS are grounded.
In the embodiment of the utility model provides an in, the memory cell is four pipe storage structures. It has a stable binary state. In the storage of the embedded FPGA, the storage unit can be directly used for outputting and driving a post-stage logic circuit. Since the memory cell has stability, it is necessary to control its writing and reading by the bit line array and the word line array. The embodiment of the present invention adopts the topology of the memory cells, and the corresponding local lines, bit line arrays and word line arrays for reading and writing operations, and the related initialization operations. All read and write operations of the embodiments of the present invention are performed through the bit line array and the word line array. Generally, address decoding is used to generate a word selection signal, and once a word line unit is selected, all memory cells corresponding to the word line unit perform the same operation. Read and write signals are read from or written to the memory cells through the bit line cells.
As shown in fig. 3, in the embodiment of the present invention, the bit line unit includes a fourth PMOS (204), a gate of the fourth PMOS (204) is connected to a bit charging control terminal, and a source of the fourth PMOS (204) is used as a read data control terminal; the drain of the fourth PMOS (204) is connected with a power supply.
The embodiment of the utility model provides a still provide a control method of embedded FPGA storage circuit, include:
when a write control signal for any row of memories is received, the word line unit of the corresponding row controls the transmission gate of the corresponding row of memories to be conducted, and the data stored in each bit line unit is transmitted to the corresponding memory unit through the transmission gate;
when a read control signal for any row of memories is received, the word line unit of the corresponding row controls the transmission gate of the corresponding row of memories to be turned on, and the data stored in the corresponding memory unit is transmitted to the corresponding bit line unit through the transmission gate.
In the embodiment of the utility model provides an in, the output of memory is with data transmission to FPGA of output.
The embodiment of the utility model provides an in, when receiving the write control signal to arbitrary line memory, charge for the position towards the electric control end of bit line unit through the local line control end of word line unit.
In the embodiment of the utility model provides an in, when the word line N control end of bit line unit is the high level, the transmission gate switches on, when the word line N control end of bit line unit is low high level, the transmission gate disconnection.
Example one
As shown in fig. 5, the present embodiment illustrates the procedure of the write 1 operation:
assuming that the data in the memory cell before writing 1 is 0, a write 1 operation is performed to this memory cell. The timing diagram is shown in fig. 5. For wordline writing, wordline control must be high (1), write control N must be high (1), and write control P must be low (0) so that the write data can be passed to the memory cell. However, the memory cell is a stable four-transistor memory structure, and this embodiment can ensure that the data signal transmitted from the outside to the memory cell is not strong enough to invert the internal memory cell, and this step must be assisted by local control plus timing. The method comprises the following specific steps: 1. the local control is high (1) which effectively acts to turn off the local line. When the local line is switched off, the memory cell becomes weak and the data signal passed from the outside to the memory cell is strong enough. 2. The local control is low (0), and after the local line is powered on, the internal memory cell will reverse to the same state as the external data. 3. And finishing the writing operation after the local line is stable.
Example two
As shown in fig. 6, the present embodiment illustrates the procedure of the write 0 operation:
assuming that the data in the memory cell before writing 0 is 1, a write 0 operation is performed to this memory cell. The timing diagram is shown in fig. 6. For wordline selection, wordline control must be high (1), write control N must be high (1), and write control P must be low (0) so that write data can be passed to the memory cell. However, the memory cell is a stable four-transistor memory structure, and this embodiment can ensure that the data signal transmitted from the outside to the memory cell is not strong enough to invert the internal memory cell, and this step must be assisted by local control plus timing. The method comprises the following specific steps: 1. the local control is high (1) which effectively acts to turn off the local line. When the local line is switched off, the memory cell becomes weak and the data signal passed from the outside to the memory cell is strong enough. 2. The local control is low (0), and after the local line is powered on, the internal memory cell will reverse to the same state as the external data. 3. And finishing the writing operation after the local line is stable.
EXAMPLE III
As shown in fig. 7, the present embodiment illustrates the procedure of the read 1 operation:
assuming that the data in the memory cell is 1, a read 1 operation is performed. The timing diagram is shown in fig. 7. For word line selection, word line control must be high (1), write control N must be high (0), and write control P must be low (1), so that write data cannot pass internally. In order to detect the data of the internal memory cell, the bit line must be charged. The bit line after charging is high level (1), but the memory cell is a stable four-tube memory structure, and the embodiment can ensure that the data signal transmitted to the memory cell from the outside is not strong enough to invert the internal memory cell. This property can then be used to detect the data signal of the memory cell. The method comprises the following specific steps: 1. the charging control is high (1), which actually acts to charge the bit line. 2. After the charging control is low (0), the bit line charging is completed, and the bit line level is high (1). The internal memory cells are de-inverted by a very stable four-pipe memory structure and by ensuring that the data signals passed to the memory cells from the outside are not strong enough. However, after the charging is completed, the data signal of the memory cell affects the bit line level. Due to the read-1 operation, the data of the memory cell is also 1, and the bit line level remains 1. 3. After the bit line is stabilized, the read operation can be completed.
Example four
As shown in fig. 8, the present embodiment illustrates the procedure of the read 0 operation:
assuming that the data in the memory cell is 0, a read 0 operation is performed. The timing diagram is shown in fig. 8. For word line selection, word line control must be high (1), write control N must be low (0), and write control P must be high (1), so that write data cannot pass internally. In order to detect the data of the internal memory cell, the bit line must be charged. The bit line after charging is high level (1), but the memory cell is a stable four-tube memory structure, and the embodiment can ensure that the data signal transmitted to the memory cell from the outside is not strong enough to invert the internal memory cell. This property can then be used to detect the data signal of the memory cell. The method comprises the following specific steps: 1. the charging control is high (1), which actually acts to charge the bit line. 2. After the charging control is low (0), the bit line charging is completed, and the bit line level is high (1). The stable four-tube memory structure and design ensure that the data signal transmitted to the memory cell from the outside is not strong enough to invert the internal memory cell. However, after the charging is completed, the data signal of the memory cell affects the bit line level. Since the data of the memory cell is also 0 due to the read-while-0 operation, the bit line level is gradually discharged to 0. 3. After the bit line is stabilized, the read operation can be completed.
EXAMPLE five
As shown in fig. 9, the present embodiment illustrates a procedure of an initial operation:
the storage unit of the embedded FPGA directly controls the logic unit of the back end, and the four-tube storage structure determines that the logic of the embedded FPGA is not determined after the embedded FPGA is initially powered on. I.e., its initial value may be high (1) or low (0). And thus the logic cells at the back end are also indeterminate. This may cause functional limitations and may more likely cause large start-up currents, cause start-up failures or damage to the chip. Initial operations must be performed. Initial control is directly linked logically to a system reset. Once the initial control is high (1), all word lines are selected, the word line control is high, the write control N must be high (1), the write control P must be low (0), the write data is low (0), (an initial value may be set in this embodiment), and the bit precharge control is low (0). All memory cells are actually forced to write a 0. The timing diagram is shown in fig. 9.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (4)
1. An embedded FPGA memory circuit, comprising: the CMOS memory comprises a CMOS memory topology array, a bit line array and a word line array, wherein the CMOS memory topology array comprises M rows by N columns of memories, the bit line array comprises N bit line units, and the word line array comprises M word line units; each word line unit controls a row of memories, and each bit line unit controls a column of memories;
each memory comprises a transmission gate and a storage unit which are connected;
the word line P control end of each word line unit is connected with the PMOS control end of the transmission gate of each memory in the row; the word line N control end of each word line unit is connected with the NMOS control end of the transmission gate of each memory in the row; the local line control end of each word line unit is connected with the storage unit control end of each memory in the row;
the bit line control end of each bit line unit is connected with the read-write control end of the transmission gate of each memory in the column;
the word line unit includes: a NAND gate, a NOR gate and an AND gate;
two input ends of the NAND gate are respectively connected with the word line control end and the word selection end;
the output end of the NAND gate is used as a word line N control end;
the output end of the NAND gate is used as a word line P control end through the output of the NOT gate;
two input ends of the AND gate are respectively connected with a word selection end and a local control end;
the initial control end and the output end of the AND gate are used as the input ends of the NOR gate; and
and the output end of the NOR gate is used as a local line control end.
2. The embedded FPGA memory circuit of claim 1, wherein the transmission gate comprises a first NMOS and a first PMOS, and a source of the first NMOS is connected to a source of the first PMOS to serve as a write data control terminal; one of the grid of the first NMOS and the grid of the first PMOS is connected with a first level, the other one is connected with a second level, and the drain of the first NMOS and the drain of the first PMOS are used as read data control ends; the grid electrode of the first PMOS is connected with the word line P control end of the corresponding word line unit; and the grid electrode of the first NMOS is connected with the word line N control end of the word line unit.
3. The embedded FPGA memory circuit of claim 2, wherein said memory cell comprises: the source electrode of the second PMOS and the source electrode of the third PMOS are respectively connected with the local line control end of the corresponding word line unit, the drain electrode of the second PMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS are connected with the write data control end of the corresponding transmission gate, and the grid electrode of the second PMOS, the grid electrode of the second NMOS and the drain electrode of the third PMOS are connected with the drain electrode of the third NMOS to serve as the output end of the memory; and the source electrode of the second NMOS and the source electrode of the third NMOS are grounded.
4. The embedded FPGA memory circuit of claim 1, wherein the bit line unit comprises a fourth PMOS, a gate of the fourth PMOS is connected with a bit charging control terminal, and a source of the fourth PMOS is used as a read data control terminal; and the drain electrode of the fourth PMOS is connected with a power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120022164.XU CN214203219U (en) | 2021-01-06 | 2021-01-06 | Embedded FPGA storage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120022164.XU CN214203219U (en) | 2021-01-06 | 2021-01-06 | Embedded FPGA storage circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214203219U true CN214203219U (en) | 2021-09-14 |
Family
ID=77635373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120022164.XU Active CN214203219U (en) | 2021-01-06 | 2021-01-06 | Embedded FPGA storage circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214203219U (en) |
-
2021
- 2021-01-06 CN CN202120022164.XU patent/CN214203219U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101529521B (en) | Two-port SRAM having improved write operation | |
| CN202275603U (en) | Device and chip for memory writing operation | |
| TWI410971B (en) | Static random access memory | |
| US20200035303A1 (en) | Non-volatile static random access memory architecture having single non-volatile bit per volatile memory bit | |
| US6924999B2 (en) | Ferroelectric memory | |
| CN115938413A (en) | Adaptive sense amplifier circuit and module applied to low-voltage SRAM | |
| CN114596907A (en) | Memristor array system for training | |
| CN105097017A (en) | SRAM (static random access memory) storage unit, SRAM memory and control method therefor | |
| CN108962311B (en) | SRAM control circuit and method for sequentially entering and exiting low-power-consumption state | |
| US8213219B2 (en) | Transistor-based memory cell and related operating methods | |
| CN101847432A (en) | Power supply structure of memory | |
| CN214203219U (en) | Embedded FPGA storage circuit | |
| CN115662483B (en) | SRAM memory cell array, read-write method, controller and system | |
| US11817149B2 (en) | Non volatile static random access memory device and corresponding control method | |
| US20020136077A1 (en) | Semiconductor memory with refresh and method for operating the semiconductor memory | |
| CN112687310A (en) | Embedded FPGA storage circuit and control method thereof | |
| US8787086B1 (en) | Inhibiting address transitions in unselected memory banks of solid state memory circuits | |
| CN110070904B (en) | Memory, chip and circuit control method | |
| KR20080047157A (en) | Power supply circuit for sense amplifier of semiconductor memory device | |
| CN110299177B (en) | Charge compensation circuit for reducing read operation voltage jitter and memory structure | |
| CN113284530B (en) | Magnetic random access memory and read-write method thereof | |
| US8411516B2 (en) | Memory cell having reduced circuit area | |
| US11328758B2 (en) | Magnetic memory, and programming control method, reading method, and magnetic storage device of the magnetic memory | |
| CN116206642B (en) | Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell | |
| CN110993001B (en) | Double-end self-checking writing circuit and data writing method of STT-MRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |