CN115938413A - An adaptive sensitive amplifier circuit and module applied to low-voltage SRAM - Google Patents

Abstract

The invention relates to the technical field of integrated circuits, in particular to a self-adaptive sense amplifier circuit applied to a low-voltage SRAM (static random access memory) and a sense amplifier module adopting the circuit layout. The invention adjusts the connection relation between the bit line BL/BLB and the two input ends of the sensitive amplifying module through the change-over switch module to realize the positive connection or the negative connection of the bit line BL/BLB and the sensitive amplifying module, so that the sensitive amplifying module can quickly and continuously read two opposite signals for a subsequent error detection circuit to judge whether the read data is correct or not; compared with the traditional error detection circuit, the invention improves the error detection delay and greatly advances the error detection time. According to the invention, after the error detection circuit module judges that the data read by the sensitive amplification module is correct, the enable signal EN acting on the word line Buffer WL _ Buffer is immediately reduced to a low level through the word line control module, so that the word line WL is closed, the discharge of the bit line BL/BLB is stopped, namely, the discharge time of the bit line BL/BLB is reduced, and the reading power consumption of the SRAM is obviously reduced.

Description

An adaptive sensitive amplifier circuit and module applied to low-voltage SRAM

technical field

The invention relates to the technical field of integrated circuits, and more specifically, relates to an adaptive sense amplifier circuit applied to a low-voltage SRAM, and a sense amplifier module adopting the circuit layout.

Background technique

With the popularity and portable applications of mobile phones, laptops and other equipment, as well as the rapid development of artificial intelligence (AI), new energy, unmanned driving technology, quantum science and technology and other technological fields, Static Random Access Memory (SRAM for short) ) The characteristics of high speed and low power consumption play an increasingly important role in circuit design, and the demand for higher density, lower power consumption, and faster speed of SRAM memory chips is becoming increasingly urgent, which requires continuous reduction of device feature size. The supply voltage continues to drop. However, shrinking dimensions and local process fluctuations lead to more serious mismatch problems between paired transistors. Referring to Figure 1, as the operating voltage VDD decreases from 1.2v, the discharge capacity of the memory cell will become weaker and weaker, that is, the discharge speed of the SRAM under low voltage will be tailed, and the delay required for the SRAM read operation will become larger and larger, resulting in The design margin required for the read operation delay of the SRAM is getting larger and larger, especially the overly pessimistic design margin at low voltage will greatly increase the read power consumption of the storage array.

Sensitive amplifier (Sense Amplifier, abbreviated as SA), as the core circuit of SRAM, largely determines whether the information in the memory cell can be read out quickly and correctly, and its main function is to connect the weak bit line connected to the memory cell The signal difference is amplified for correct readout. The performance indicators of the sense amplifier mainly include offset voltage, reading speed, yield rate, power consumption, etc., and the most important parameter is the offset voltage. The existence of the offset voltage may cause the sense amplifier to wrongly amplify the information in the storage unit, seriously affecting the working performance of the SRAM. In order to ensure that the read data is correct, the design margin of the bit line swing has to be increased to overcome the influence of the offset voltage. However, in order to meet the design margin set for the slow discharge time of very few memory cells, the read operation of most memory cells will cause unnecessary power consumption due to the long turn-on time of the word line, see Figure 2 and Figure 3 .

Contents of the invention

Based on this, it is necessary to provide an adaptive sense amplifier circuit and module applied to low-voltage SRAM to solve the problem of waste of power consumption in the read operation of the existing SRAM at low voltage.

The present invention adopts following technical scheme to realize:

In the first aspect, the present invention provides an adaptive sense amplifier circuit applied to low-voltage SRAM, which is used for adaptively controlling the discharge time of the bit line BL/BLB of the memory array, and adaptively outputting correct data.

The adaptive sensitive amplifier circuit includes a sensitive amplifier module, a switch module, an error detection circuit module and a word line control module.

The sensitive amplification module is used to read the data on the bit line BL/BLB. The switch module is connected between the sensitive amplifier module and the memory array, and is used for switching the positive/reverse connection between the bit line BL/BLB of the memory array and the sense amplifier when the sensitive amplifier module reads data twice adjacently. The error detection circuit module is connected to the output terminal of the sensitive amplifier module, and is used for error detection and comparison between the even-numbered read data of the sensitive amplifier module and the previous odd-number read data until the output result signal FLAG is "1", and the The correct read data is output to an external combinational logic circuit. The word line control module is connected to the output terminal of the error detection circuit module, and is used to adjust the enable signal EN acting on the word line buffer WL_Buffer according to the result signal FLAG, and then control the closing time of the memory array word line WL, and realize the self-adaptive control bit Line BL/BLB discharge time.

The implementation of the adaptive sense amplifier circuit applied to low-voltage SRAM is according to the method or process of the embodiments of the present disclosure.

In the second aspect, the present invention discloses a sense amplifier module, which adopts the adaptive sense amplifier circuit layout applied to low-voltage SRAM as disclosed in the first aspect.

Compared with the prior art, the present invention has the following beneficial effects:

1. The present invention adjusts the connection relationship between the bit line BL/BLB and the two input terminals of the sensitive amplifier module by switching the switch module, so as to realize the direct connection or reverse connection of the two, so that the sensitive amplifier module can read two opposite signals rapidly and continuously, so that It is used for the subsequent error detection circuit to judge whether the read data is correct; compared with the traditional error detection circuit, the present invention improves the error detection delay and greatly advances the error detection time.

2. In the present invention, after the error detection circuit module judges that the data read by the sensitive amplifier module is correct, the correct data will be adaptively output to the external combinational logic circuit, and the word line buffer WL_Buffer will be activated immediately through the word line control module. The enable signal EN drops to a low level, thereby turning off the word line WL, and stopping the discharge of the bit line BL/BLB, which reduces the discharge time of the bit line BL/BLB, and significantly reduces the read power consumption of the SRAM.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings on the premise of not paying creative efforts.

Fig. 1 is the simulation result figure of the 60mV time-delay situation of bit line discharge under VDD=1.2v and VDD=0.5v for existing SRAM storage unit in the background technology;

Fig. 2 is a schematic diagram of the existing problems in the read operation of the existing SRAM storage unit in the background technology;

FIG. 3 is a schematic diagram of the trend of the energy consumption and delay of the read operation of the existing SRAM storage unit in the background technology as the power supply voltage changes;

FIG. 4 is a structural diagram of an adaptive sense amplifier circuit applied to a low-voltage SRAM used in conjunction with a memory array provided in Embodiment 1 of the present invention;

Fig. 5 is a structural diagram of the diverter switch module in Fig. 4;

Fig. 6 is a schematic diagram of the working state of the diverter switch module in Fig. 5;

Fig. 7 is a structural diagram of the sensitive amplification module in Fig. 4;

Fig. 8 is a structural diagram of the error detection circuit module in Fig. 4;

Fig. 9 is a structural diagram of the word line control module in Fig. 4;

Fig. 10 is a schematic diagram of the timing sequence of the read operation in which the sense amplifier circuit of Fig. 4 judges that the read data is correct after the first error detection;

Fig. 11 is a schematic diagram of the timing sequence of the read operation in which the read data is judged to be correct after the nth error detection of the sense amplifier circuit of Fig. 4;

FIG. 12 is a schematic diagram of a comparison of dynamic power consumption between the sense amplifier circuit of FIG. 4 and the traditional scheme when reading operations at different voltages;

FIG. 13 is a schematic diagram of the comparison of the turn-on time of the word line when the sense amplifier circuit of FIG. 4 and the traditional scheme are read at different voltages;

FIG. 14 is a simulation result diagram of the sense amplifier circuit of FIG. 4 and the discharge condition of the existing SRAM memory cell in the background technology under VDD=0.6v.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that when a component is said to be "mounted on" another component, it can be directly on the other component or there can also be an intervening component. When a component is said to be "set on" another component, it may be set directly on the other component or there may be an intervening component at the same time. When a component is said to be "fixed" to another component, it may be directly fixed to the other component or there may be an intervening component at the same time.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "or/and" includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to FIG. 4 , it is a structural diagram of an adaptive sense amplifier circuit applied to a low-voltage SRAM disclosed in this embodiment and used together with a memory array.

As shown in FIG. 4 , an adaptive sense amplifier circuit applied to a low-voltage SRAM is used to adaptively control the discharge time of the bit line BL/BLB of the memory array.

For the storage array, it includes N columns and M rows of storage cells (BITCELL). Memory cells in the same column share the same bit line BL/BLB.

It should be noted that, according to the number of enabled columns of the storage array, a sense amplifier circuit of a corresponding specification should be selected.

If the number of selected columns of the storage array is 2 ⁱ each time, that is, corresponding to the SRAM with a bit width of 2 ⁱ bits, the corresponding selected sense amplifier circuit includes 2 ⁱ sense amplifier modules, 2 ⁱ switch modules, and 2 ⁱ error detection A circuit module, a word line control module; i=0, 1, 2, . . .

The switch module, the sensitive amplifier module, and the error detection module correspond one by one, and the kth switch module, the kth sensitive amplifier module, and the kth error detection module are connected in sequence, 1≤k≤2 ⁱ . The bit line BL/BLB of the j*2 ⁱ +k column is connected to the k switch, 0≤j≤N/2 ⁱ −1.

It should be noted that, referring to FIG. 4 , the memory array is counted from 0, [0] is the first column and the first row; while the sense amplifier circuit is counted from 1, [1] is the first column.

The sensitive amplification module is used to read the data on the bit line BL/BLB. The switch module is connected between the sensitive amplifier module and the memory array, and is used for switching the positive/reverse connection between the bit line BL/BLB of the memory array and the sense amplifier when the sensitive amplifier module reads data twice adjacently. The error detection circuit module is connected to the output terminal of the sensitive amplifier module, and is used for error detection and comparison between the even-numbered read data of the sensitive amplifier module and the previous odd-number read data until the output result signal FLAG is "1", and the The read data is output to an external combinational logic circuit. The word line control module is connected to the output terminal of the error detection circuit module, and is used to adjust the enable signal EN acting on the word line buffer WL_Buffer according to the result signal FLAG, and then control the closing time of the memory array word line WL, and realize the self-adaptive control bit Line BL/BLB discharge time.

In order to facilitate the description of the structure of each module, for the switch module, the sensitive amplifier module, and the error detection module, one of them is firstly used for description.

(1) Referring to Fig. 5, it is a structural diagram of the diverter switch module. The switch module includes PMOS transistors KEY1, KEY2, KEY3, KEY4.

The source of KEY1 is connected to the bit line BL, the gate is connected to the control signal SW, and the drain is connected to the positive input IN of the sensitive amplifier module. The source of KEY2 is connected to the bit line BL, the gate is connected to the control signal SWN, and the drain is connected to the input negative electrode INB of the sensitive amplification module. The source of KEY3 is connected to the bit line BLB, the gate is connected to the control signal SWN, and the drain is connected to the positive input IN of the sensitive amplifier module. The source of KEY4 is connected to the bit line BLB, the gate is connected to the control signal SW, and the drain is connected to the input negative electrode INB of the sensitive amplification module.

It should be noted that the control signal SW is divided into three paths; the first path directly controls KEY1; the second path directly controls KEY4; the third path is converted into a control signal SWN by a signal inverter, and then divided into two paths, one of which controls KEY2 , Another way to control KEY3. Therefore, the on-off states of KEY1 and KEY4 are the same, the on-off states of KEY2 and KEY3 are the same, and the on-off states of KEY1 and KEY2 are opposite.

Referring to FIG. 6 , it is a schematic diagram of the working state of the diverter switch module. That is to say, when the control signal SW is at low potential, the control signal SWN is at high potential, the bit line BL is connected to the positive input terminal IN of the sensitive amplifier module through KEY1, and the bit line BLB is connected to the negative input terminal INB of the sensitive amplifier module through KEY4. When the control signal SW is at a high potential, the control signal SWN is at a low potential, the bit line BL is connected to the input negative pole INB of the sensitive amplifier module through KEY2, and the bit line BLB is connected to the input positive pole IN of the sensitive amplifier module through KEY3.

In this way, by adjusting the potential level of the control signal SW, the rapid switching of the input voltage polarity of the sensitive amplifying module is realized, so that when the sensitive amplifying module reads data twice adjacently, the bit line BL/BLB performs positive/reverse connection switching. It should be emphasized that the bit line BL/BLB is positively connected to the sensitive amplifying module during odd-numbered readings; and the bit-line BL/BLB is reversely connected to the sensitive amplifying module during even-numbered readings.

It should be noted that the 2 ⁱ transfer switch modules share the same control signal SW, which can realize overall control.

If the above is the kth switch, KEY1, KEY2, KEY3, KEY4 are KEY1[k], KEY2[k], KEY3[k], KEY4[k]; correspondingly, it is connected to the kth sensitive amplifier Module, the bit line BL/BLB of the j*2 ⁱ +k column, that is, the input positive pole IN is IN[k], the input negative pole INB is INB[k], and the bit line BL is BL[j*2 ⁱ +k-1 ], the bit line BLB is BLB[j*2 ⁱ +k-1].

(2) Referring to Fig. 7, it is a structural diagram of the sensitive amplification module. The sensitive amplification module includes 9 PMOS transistors P1-P9 and 3 NMOS transistors N1-N3.

The gate of P1 is connected to the output node OUTN, the source is connected to the power supply VDD, and the drain is connected to the output node OUT. The gate of P2 is connected to the output node OUT, the source is connected to the power supply VDD, and the drain is connected to the output node OUTN. The gate of P3 is connected to the control signal EQ, the source is connected to the power supply VDD, and the drain is connected to the output node OUT. The gate of P4 is connected to the control signal EQ, the source is connected to the power supply VDD, and the drain is connected to the output node OUTN. The gate of P5 is connected to the control signal RD, the source is connected to the output node OUT, and the drain is connected to the positive input IN. The gate of P6 is connected to the control signal RD, the source is connected to the output node OUTN, and the drain is connected to the negative electrode INB. The gate of P7 is connected to the control signal PRE, the source is connected to the power supply VDD, and the drain is connected to the positive input IN. The gate of P8 is connected to the control signal PRE, the source is connected to the power supply VDD, and the drain is connected to the negative input INB. The gate of P9 is connected to the control signal PRE, the source is connected to the positive pole IN of the sensitive amplifier module, and the drain is connected to the negative pole INB of the input.

The gate of N1 is connected to the output node OUTN, the drain is connected to the output node OUT, and the source is connected to the node NET. The gate of N2 is connected to the output node OUT, the drain is connected to the output node OUTN, and the source is connected to the node NET. The gate of N3 is connected to the enable signal SAE, the drain is connected to the node NET, and the source is connected to the power ground.

Specifically, if the voltage on the bit line BL is greater than the voltage on the bit line BLB, the output node OUT is low level 0; when the voltage on the bit line BL is lower than the voltage on the bit line BLB, the output node OUT is high level 1 .

When the sensitive amplifying module reads data twice adjacently, before the next reading, the output nodes OUT and OUTN are charged to VDD through P3 and P4, and then P5 and P6 are turned on to sense the bit lines BL and BLB for the second time. The voltage difference is used to avoid the influence of the previous amplified readout result on the error detection readout.

See Table 1, which shows the influence of the input and offset voltage of the sensitive amplifier module on the output of the sensitive amplifier module. ①V _OFFSET >0, defined as the driving ability of N1 is stronger than that of N2; ②V _OFFSET <0, defined as the driving ability of N1 is weaker than that of N2.

Table 1 The influence of the input and offset voltage of the sensitive amplifier module on the output of the sensitive amplifier module

As shown in Table 1, when the polarity of the bit line swing is opposite to that of the offset voltage, the reading must be correct. When the polarities are the same, the bit line swing must be greater than the offset voltage to read correctly (the bit line swing is defined as |V _BL -V _BLB |).

It should be noted that the 2 ⁱ sensitive amplifying modules share the same control signal EQ, the same control signal RD, the same control signal SAE, and the same control signal PRE, which can realize the overall control.

If the above is the kth sensitive amplifying module, P1-P9 are P1[k]-P9[k]; N1-N3 are N1[k]-N3[k]. The output node OUTN is OUTN[k], the output node OUT is OUT[k], the positive input IN is IN[k], the negative input INB is INB[k], and the node NET is NET[k].

(3) Referring to FIG. 8 , it is a structural diagram of the error detection circuit module. The error detection circuit module includes a D flip-flop LATCH, a transmission gate TG1, a transmission gate TG2, a two-input XOR gate, and a transmission gate TG3.

The first input terminal of the D flip-flop LATCH is connected to the output node OUT of the sensitive amplification module, the second input terminal is connected to the clock signal LA, and the output is divided into two paths.

The input end of the transmission gate TG1 is connected with an output of the D flip-flop LATCH, and the enable end is connected with the enable signal CO. The input end of the transmission gate TG2 is connected to the output node OUT of the sensitive amplification module, and the enable end is connected to the enable signal CO. The first input terminal of the two-input XOR gate is connected to the output terminal of the transmission gate TG1, the second input terminal is connected to the output terminal of the transmission gate TG2, and the output terminal outputs the result signal FLAG. The first input terminal of the transmission gate TG3 is connected to the other output of the D flip-flop LATCH, the second input terminal is connected to the result signal FLAG, and the output terminal outputs the data signal Right_OUT.

Specifically, for odd-numbered reads and subsequent even-numbered reads:

First look at the odd number of times, the D flip-flop LATCH latches the readout result 1st_OUT of the odd number of times through the clock signal LA, and the transmission gates TG1 and TG2 are closed, so the two-input XOR gate XOR has no result comparison;

Then perform an even number of times, after reading the result 2nd_OUT, the transmission gates TG1 and TG2 are opened, 2nd_OUT passes through the transmission gate TG2 to the two-input exclusive OR gate XOR, and one output 1st_OUT of the D flip-flop LATCH passes through the transmission gate TG1 to the two-input exclusive OR gate XOR, the two-input XOR gate XOR is to compare the two readout results to realize the error detection function.

If the error detection circuit module determines that the reading is correct, it outputs a FLAG signal of "1" to the word line control module, and then controls the shutdown of the word line WL to realize the self-adaptive stop of discharge of the bit line BL/BLB. Moreover, when the FLAG signal is "1", it also controls the transmission gate TG3 to open, and the other output 1st_OUT of the D flip-flop LATCH passes through the transmission gate TG3, thereby adaptively outputting correct readout data Right_OUT.

Referring to Table 2, it shows the relationship between the error detection result of the error detection circuit module and the swing of the memory cell bit line in this embodiment.

Table 2 Relationship between error detection results and memory cell bit line swing

As shown in Table 2, 1st_OUT is odd-number read data, and 2nd_OUT is even-number read data. The two are the same, the output result signal FLAG is "0"; the two are different, the output result signal FLAG is "1".

In the error detection circuit, although the output is correct, the FLAG may be misjudged as "0". However, the energy loss in this case is basically negligible, because as the bit line swing increases, the misjudgment will soon be eliminated, and the probability of this situation is extremely small.

It should be noted that 2 ⁱ error detection modules share the same clock signal LA.

If the above is the kth error detection circuit module, the D flip-flop LATCH is LATCH[k], the transmission gates TG1, TG2, TG3 are TG1[k], TG2[k], TG3[k], and the two-input exclusive OR gate XOR is XOR[k], the resulting signal FLAG is FLAG[k], and the data signal Right_OUT is Right_OUT[k].

That is, the kth error detection module outputs the result signal FLAG[k] and the data signal Right_OUT[k].

(4) Referring to FIG. 9 , it is a structural diagram of the word line control module. The word line control module includes a PMOS transistor MP, a capacitor CAP, and 2 ⁱ NMOS transistors M[1]˜M[2 ⁱ ].

The gate of the PMOS transistor MP is connected to the precharge signal PRE, the source is connected to the power supply VDD, and the drain is connected to the output node Ctr_OUT. The output node Ctr_OUT outputs an enable signal EN. The upper electrode of the capacitor CAP is connected to the output node Ctr_OUT, and the lower electrode is connected to the power ground.

M[1]～M[2 ⁱ ] are connected in series in sequence, the source of the previous NMOS transistor M[h] is connected to the drain of the next NMOS transistor M[h+1], 1≤h≤2 ⁱ −1.

Wherein, the gate of the kth NMOS transistor M[k] is connected to the result signal FLAG[k], the drain of M[1] is connected to the output node Ctr_OUT, and the source of M[2 ⁱ ] is connected to the power ground.

It should be noted that the word line control module and the 2 ⁱ sensitive amplification modules share the same control signal PRE.

The memory cells in the same row share the same word line WL. The enable signal EN is connected to the M word line buffers WL_Buffer of the M rows of memory cells, and is used for uniformly controlling the M word line buffers WL_Buffer.

Specifically, MP is responsible for charging the capacitor CAP before receiving the FLAG signal, so that the enable signal EN is kept at a high potential, and M[1]~M[2 ⁱ ] are responsible for receiving the FLAG signal, and the working state is controlled by the FLAG signal: when When FLAG[1]～FLAG[2 ⁱ ] are all high level "1", there is a leakage path between the enable signal EN and the power ground, so that the level of the enable signal EN is low "0", thereby controlling the word line buffer The WL_Buffer stops working, and the word line WL is turned off, so as to realize adaptive control of the discharge time of the bit line BL/BLB.

In addition, the word line WL of each row is connected to a row decoder (DEW) through a word line buffer WL_Buffer; the row decoder is used to select a specific row that needs to be opened for calculation of the memory array. Each column of memory cells is connected to a column selection circuit (MUX), and the column selection circuit is controlled by a column decoder to select specific columns that need to be opened for calculation of the storage array.

Example 2

Embodiment 2 discloses timing diagrams of two situations when the sense amplifier circuit in embodiment 1 performs a read operation.

Referring to FIG. 10 , it is a schematic diagram of a timing sequence of a read operation in which the read data is determined to be correct after the first error detection, taking a single column as an example.

Specifically: in the first step, the word line WL is turned on, the bit line BL/BLB is discharged, after a short time, the SAE signal is enabled, the sensitive amplifier module is started, and the read data is latched by the D flip-flop LATCH for error detection Read data comparison. The second step is to close P5, P6, and N3, open P3, and P4 to recharge the two output nodes of the sensitive amplifier module to VDD, and quickly adjust the polarity of the input voltage of the sensitive amplifier module; then the control signal RD controls P5, P6 to turn on again, SAE The signal is enabled for the second time, the sensitive amplifier module is started for the second time, the error detection data is read out, and then the transmission tubes TG1 and TG2 are controlled to open through the control signal CO, and the output signal FLAG of the two-input exclusive OR gate XOR is "1", then the first read The result is correct, the data is quickly output to the external combinational logic circuit, the result signal FLAG is input to the word line control module, and there is a leakage path between the enable signal EN and the power ground, so that the EN level is low "0", and then control M words The line buffers WL_Buffer stop working uniformly, the word line WL is turned off, the bit line BL/BLB stops discharging, and the read operation ends.

Referring to FIG. 11 , it is a schematic diagram of a timing sequence of a read operation in which the read data is determined to be correct only after the nth error detection, taking a single column as an example.

Specifically, in the first step, the word line WL is turned on, and the bit line BL/BLB is discharged. After a short time, the SAE signal is enabled, the sensitive amplifier module is started, and the read data is latched by the D flip-flop LATCH for error detection. Read data comparison. The second step is to turn off P5, P6, and N3, turn on P3, and P4 to recharge the two output nodes of the sensitive amplifier module to VDD, quickly adjust the polarity of the input voltage of the sensitive amplifier module, and then control the signal RD to control P5 and P6 to turn on again, SAE The signal is enabled for the second time, the sensitive amplifier module is started for the second time, the error detection data is read out, and then the transmission tubes TG1 and TG2 are controlled to open through the control signal CO. If the output result signal FLAG of the two-input XOR gate is "0", the read out Data error, FLAG is input to the word line control module, the EN level remains high, the control word line WL continues to be turned on, the bit line BL/BLB continues to discharge, the swing of the bit line BL/BLB is further amplified, and the sensitive amplification module starts again, in turn Loop until the data is read correctly.

This embodiment 2 also simulates and compares the adaptive sense amplifier circuit applied to the low-voltage SRAM of embodiment 1 and the traditional scheme SA, and compares the dynamic power consumption comparison of the two in the read operation at different voltages. The comparison diagram is as follows Figure 12 shows. The simulation conditions are 1.2V, 1.1V, 1.0V, 0.9V, 0.8V, 0.7V and 0.6V, ttg process angle, 27°C.

The results show that: the adaptive sense amplifier circuit design scheme applied to low-voltage SRAM provided by embodiment 1 has lower power consumption than the traditional scheme SA under low operating voltage, and the lower the operating voltage, the greater the power consumption reduction. Therefore, it has a better application prospect.

Similarly, this embodiment 2 also simulates and compares the adaptive sense amplifier circuit applied to low-voltage SRAM in embodiment 1 with the traditional scheme SA, compares the turn-on time of the word line when reading operations at different voltages, and compares the schematic diagrams As shown in Figure 13. The simulation conditions are 1.2V, 1.1V, 1.0V, 0.9V, 0.8V, 0.7V and 0.6V, ttg process angle, 27°C.

The results show that: the adaptive sense amplifier circuit design scheme applied to low-voltage SRAM provided by Example 1, the average turn-on time of the word line is shorter than that of the traditional scheme SA under low operating voltage, which also confirms the simulation results of the above power consumption .

In addition, this embodiment 2 also simulates the discharge condition of the adaptive sense amplifier circuit applied to the low-voltage SRAM of the embodiment 1 and the existing SRAM storage unit in the background technology at VDD=0.6v, and the result diagram is shown in FIG. 14 Show. The results show that most of the correct results will be read out in the first 4 times, and the word line WL will be turned off before 6ns in most read operations, while using the traditional scheme, all word lines WL need to be turned on for 12ns during the read operation, It is proved that this scheme can shorten the turn-on time of the word line WL during the read operation, thereby reducing the read power consumption of the SRAM.

Example 3

On the basis of the adaptive sense amplifier circuit applied to low-voltage SRAM disclosed in Embodiment 1, Embodiment 3 also discloses a sense amplifier module, which adopts the layout of the sense amplifier circuit disclosed in Embodiment 1.

The mode of being packaged into a module is easier to popularize and apply an adaptive sense amplifier circuit applied to a low-voltage SRAM.

The interface of the sense amplifier module includes:

SW port, BL[0] port~BL[2 ⁱ -1] port, BLB[0] port~BLB[2 ⁱ -1] port, EQ port, RD port, SAE port, PRE port, LA port, CO port , Right_OUT[1] interface ~ Right_OUT[2 ⁱ ] interface, EN interface.

Wherein, the SW interface is used to transmit the control signal SW.

BL[0] interface is used to connect with bit line BL[j*2 ⁱ ]; BL[1] interface is used to connect with bit line BL[j*2 ⁱ +1]; ...; BL[2 ⁱ -1] interface It is used to connect with the bit line BL[j*2 ⁱ +2 ⁱ -1].

The BLB[0] interface is used to connect to the bit line BLB[j*2 ⁱ ]; the BLB[1] interface is used to connect to the bit line BLB[j*2 ⁱ +1]; ...; BLB[2 ⁱ -1] interface It is used to connect with the bit line BLB[j*2 ⁱ +2 ⁱ -1].

The EQ interface is used to transmit the control signal EQ. The RD interface is used to transmit the control signal RD. The SAE interface is used to transmit the enable signal SAE. The PRE interface is used to transmit the control signal PRE. The LA interface is used to transmit the clock signal LA. The CO interface is used to transmit the enable signal CO.

The Right_OUT[1] interface is used to connect to the data signal Right_OUT[1]; the Right_OUT[2] interface is used to connect to the data signal Right_OUT[2]; ...; the Right_OUT[2 ⁱ ] interface is used to connect to the data signal Right_OUT[2 ⁱ ] connect. The EN interface is used to transmit the enable signal EN.

The various technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of concise description, all possible combinations of the various technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. An adaptive sense amplifier circuit applied to a low voltage SRAM for adaptively controlling a bit line BL/BLB discharge time of a memory array and adaptively outputting correct data, the adaptive sense amplifier circuit comprising:

the sensitive amplification module is used for reading data on the bit line BL/BLB;

the switch module is connected between the sensitive amplification module and the storage array and is used for switching the positive/negative connection between a bit line BL/BLB of the storage array and the sensitive amplifier when the sensitive amplification module reads data for two times;

the error detection circuit module is connected to the output end of the sensitive amplification module and is used for carrying out error detection comparison on even-numbered read data of the sensitive amplification module and previous odd-numbered read data of the sensitive amplification module until an output result signal FLAG is '1' and outputting correct read data to an external combinational logic circuit; and

and the word line control module is connected to the output end of the error detection circuit module and is used for adjusting an enable signal EN acting on a word line Buffer WL _ Buffer according to a result signal FLAG so as to control the closing time of the word line WL of the memory array and realize the self-adaptive control of the discharge time of the bit line BL/BLB.

2. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 1, wherein said switch module, sense amplifier module, and error detection module are all set to 2 ⁱ I =0,1,2, \ 8230; the change-over switch module, the sensitive amplification module and the error detection module correspond to each other one by one, the kth change-over switch module, the kth sensitive amplification module and the kth error detection module are connected in sequence, and k is greater than or equal to 1 and less than or equal to 2 ⁱ 。

3. The adaptive sense amplifier circuit applied to the low-voltage SRAM as claimed in claim 2, wherein the kth sense amplifier module comprises:

the grid of the kth PMOS transistor P1[ k ], P1[ k ] is connected with the kth output node OUTN [ k ], the source is connected with the power supply VDD, and the drain is connected with the kth output node OUT [ k ];

the grid of the kth PMOS transistor P2[ k ], P2[ k ] is connected with the output node OUT [ k ], the source is connected with the power supply VDD, and the drain is connected with the output node OUTN [ k ];

the grid electrode of the kth PMOS transistor P3[ k ], P3[ k ] is connected with a control signal EQ, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an output node OUT [ k ];

the grid electrodes of the kth PMOS transistors P4[ k ] and P4[ k ] are connected with a control signal EQ, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an output node OUTN [ k ];

the grid electrode of the kth PMOS transistor P5[ k ], P5[ k ] is connected with the control signal RD, the source electrode is connected with the output node OUT [ k ], and the drain electrode is connected with the kth input anode IN [ k ];

the grid electrodes of the kth PMOS transistors P6[ k ] and P6[ k ] are connected with a control signal RD, the source electrodes are connected with an output node OUTN [ k ], and the drain electrodes are connected with the kth input negative electrode INB [ k ];

the grid electrode of the kth PMOS transistor P7[ k ], P7[ k ] is connected with a control signal PRE, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an input positive electrode IN [ k ];

the grid electrode of the kth PMOS transistor P8[ k ], P8[ k ] is connected with a control signal PRE, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an input cathode INB [ k ];

the grid electrodes of the kth PMOS transistors P9[ k ], P9[ k ] are connected with a control signal PRE, the source electrodes are connected with an input positive electrode IN [ k ], and the drain electrodes are connected with an input negative electrode INB [ k ];

the grid of the kth NMOS transistor N1[ k ], N1[ k ] is connected with an output node OUTN [ k ], the drain is connected with an output node OUT [ k ], and the source is connected with the kth node NET [ k ];

the grid of the kth NMOS transistor N2[ k ], N2[ k ] is connected with the output node OUT [ k ], the drain is connected with the output node OUTN [ k ], and the source is connected with the node NET [ k ]; and

the gate of the kth NMOS transistor N3[ k ], N3[ k ] is connected to the enable signal SAE, the drain is connected to the node NET [ k ], and the source is connected to the power ground.

4. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 3, wherein said memory array comprises N columns and M rows of memory cells; the same column of memory cells shares the same bit line BL/BLB; j 2 th ⁱ The bit line BL/BLB of + k column is connected with the kth switch, and j is more than or equal to 0 and less than or equal to N/2 ⁱ -1；

The kth diverter switch module comprises:

kth PMOS transistor KEY1[ k ]]，KEY1[k]Is connected to the j 2 th source ⁱ + k bit lines BL [ j × 2 ⁱ +k-1]A gate connected to the control signal SW, a drain connected to the input anode IN [ k ]]；

Kth PMOS transistor KEY2[ k ]]，KEY2[k]Is connected to bit line BL [ j 2 ] ⁱ +k-1]A gate connected to the control signal SWN, a drain connected to the input cathode INB [ k ]]；

The kth PMOS transistor KEY3[ k ]]，KEY3[k]Is connected to the j 2 th source ⁱ + k bit lines BLB [ j × 2 ⁱ +k-1]A gate connected to a control signal SWN, a drain connected to an input positive electrode IN [ k ]](ii) a And

the kth PMOS transistor KEY4[ k ]]，KEY4[k]Is connected to bit line BLB [ j 2 ] ⁱ +k-1]Grid is connected toA drain connected to the input cathode INB k]。

5. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 2, wherein said control signal SW is divided into three paths; the first path directly controls KEY1[ k ]; the second path directly controls KEY4[ k ]; the third path is converted into a control signal SWN through a signal inverter and then is divided into two paths, wherein one path controls KEY2[ k ] and the other path controls KEY3[ k ].

6. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 2, wherein the kth error detection circuit module comprises:

a kth D flip-flop LATCH [ k ], wherein the input end I is connected with an output node OUT [ k ], the input end II is connected with an enable signal CO, and the output is divided into two paths;

the kth transmission gate TG1[ k ], the input end of which is connected with one output of the D trigger LATCH [ k ], and the enable end of which is connected with an enable signal CO;

a kth transmission gate TG2[ k ], the input end of which is connected with the output node OUT [ k ], and the enabling end of which is connected with an enabling signal CO;

a kth two-input exclusive-or gate XOR [ k ], of which the input end one is connected with the output end of the transmission gate TG1[ k ], the input end two is connected with the output end of the transmission gate TG2[ k ], and the output end outputs a kth result signal FLAG [ k ]; and

the kth transmission gate TG3[ k ], whose input end one is connected with the other output of the D flip-flop LATCH [ k ], whose input end two is connected with the result signal FLAG [ k ], and whose output end outputs the kth data signal Right _ OUT [ k ].

7. The adaptive sense amplifier circuit applied to low-voltage SRAM of claim 6, wherein the word line control module comprises:

a PMOS tube MP, the grid electrode of which is connected with a PRE-charge signal PRE, the source electrode of which is connected with a power supply VDD, and the drain electrode of which is connected with an output node Ctr _ OUT; the output node Ctr _ OUT outputs an enable signal EN;

the upper electrode of the capacitor CAP is connected with the output node Ctr _ OUT, and the lower electrode of the capacitor CAP is connected with the power ground; and

2 ⁱ an NMOS transistor M [1]～M[2 ⁱ ]，M[1]～M[2 ⁱ ]Sequentially connected in series, and the last NMOS tube M [ h ]]Is connected to the next NMOS transistor M [ h + 1]]H is more than or equal to 1 and less than or equal to 2 ⁱ -1; wherein, the Kth NMOS transistor M [ K ]]Gate connection result signal FLAG k]，M[1]Is connected to the output node Ctr _ OUT, M [2 ] ⁱ ]Is connected to power ground.

8. The adaptive sense amplifier circuit applied to the low-voltage SRAM of claim 7, wherein the same row of memory cells share the same word line WL; the enable signal EN is connected to M word line buffers WL _ Buffer of the M rows of memory cells, and controls the M word line buffers WL _ Buffer to stop operating in unison when the enable signal EN is low.

9. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 7, wherein 2 ⁱ The switching switch modules share the same control signal SW;2 ⁱ The sensitive amplification modules share the same control signal EQ, the same control signal RD and the same control signal SAE;2 ⁱ The error detection modules share the same clock signal LA; word line control module, 2 ⁱ The sensitive amplifying modules share the same control signal PRE.

10. A sense amplifier module, characterized in that an adaptive sense amplifier circuit layout according to any of claims 1-9 is used.

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