CN115938413A

CN115938413A - Adaptive sense amplifier circuit and module applied to low-voltage SRAM

Info

Publication number: CN115938413A
Application number: CN202211697141.4A
Authority: CN
Inventors: 周永亮; 武赛赛; 施琦; 杨震; 韦一鸣; 周子璇; 刘立; 彭春雨; 吴秀龙
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-04-07

Abstract

The invention relates to the technical field of integrated circuits, in particular to a self-adaptive sense amplifier circuit applied to a low-voltage SRAM (static random access memory) and a sense amplifier module adopting the circuit layout. The invention adjusts the connection relation between the bit line BL/BLB and the two input ends of the sensitive amplifying module through the change-over switch module to realize the positive connection or the negative connection of the bit line BL/BLB and the sensitive amplifying module, so that the sensitive amplifying module can quickly and continuously read two opposite signals for a subsequent error detection circuit to judge whether the read data is correct or not; compared with the traditional error detection circuit, the invention improves the error detection delay and greatly advances the error detection time. According to the invention, after the error detection circuit module judges that the data read by the sensitive amplification module is correct, the enable signal EN acting on the word line Buffer WL _ Buffer is immediately reduced to a low level through the word line control module, so that the word line WL is closed, the discharge of the bit line BL/BLB is stopped, namely, the discharge time of the bit line BL/BLB is reduced, and the reading power consumption of the SRAM is obviously reduced.

Description

Adaptive sense amplifier circuit and module applied to low-voltage SRAM

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a self-adaptive sense amplifier circuit applied to a low-voltage SRAM (static random access memory) and a sense amplifier module adopting the circuit layout.

Background

With the popularization and portable application of devices such as mobile phones and notebook computers, and the rapid development of the scientific and technological fields such as Artificial Intelligence (AI), new energy, unmanned technology, quantum science and technology, the characteristics of Static Random Access Memory (SRAM) with high speed and low power consumption play an increasingly important role in circuit design, and the demands for higher density, lower power consumption and higher speed of SRAM Memory chips are increasing, which requires the continuous reduction of the feature size of devices and the continuous reduction of the power supply voltage. However, as dimensions shrink, local process fluctuations cause mismatch problems between pairs of transistors to be more severe. Referring to fig. 1, as the operating voltage VDD is decreased from 1.2v, the discharge capability of the memory cell is weaker, that is, the SRAM discharge speed at low voltage has a tailing phenomenon, and the delay required by the SRAM read operation is larger and larger, which results in that the design margin required by the delay of the SRAM read operation is larger and larger, and especially the excessively pessimistic design margin at low voltage greatly increases the read power consumption of the memory array.

A Sense Amplifier (SA) is used as a core circuit of the SRAM, and largely determines whether information in a memory cell can be read out quickly and correctly, and mainly plays a role in amplifying a weak signal difference on a bit line connected to the memory cell and then correctly reading the weak signal difference. The performance index of the sense amplifier mainly includes offset voltage, read speed, yield, power consumption, etc., and the most important parameter is the offset voltage. The presence of offset voltage may cause the sense amplifier to erroneously amplify the information in the memory cell, which seriously affects the operating performance of the SRAM. To ensure that the data read is correct, the design margin of the bit line swing has to be increased to overcome the effect of the offset voltage. However, the design margin set by the slow discharge time of very few memory cells can cause unnecessary power consumption in most memory cell read operations due to the long word line on time, as shown in fig. 2 and 3.

Disclosure of Invention

Therefore, it is necessary to provide an adaptive sense amplifier circuit and a module applied to a low voltage SRAM, aiming at the problem of power consumption waste in the read operation of the conventional SRAM at a low voltage.

The invention is realized by adopting the following technical scheme:

in a first aspect, the present invention provides an adaptive sense amplifier circuit applied to a low voltage SRAM, which is used for adaptively controlling the bit line BL/BLB discharge time of a memory array and adaptively outputting correct data.

The self-adaptive sensitive amplifier circuit comprises a sensitive amplifying module, a change-over switch module, an error detection circuit module and a word line control module.

The sensitive amplifying module is used for reading data on the bit line BL/BLB. The switch module is connected between the sensitive amplification module and the memory array and is used for switching the positive/negative connection between the bit line BL/BLB of the memory array and the sensitive amplifier when the sensitive amplification module reads data twice. The error detection circuit module is connected to the output end of the sensitive amplification module and is used for carrying out error detection comparison on even-numbered read data of the sensitive amplification module and previous odd-numbered read data of the sensitive amplification module until an output result signal FLAG is '1', and outputting correct read data to an external combinational logic circuit. The word line control module is connected to the output end of the error detection circuit module and used for adjusting an enable signal EN acting on a word line Buffer WL _ Buffer according to a result signal FLAG, so that the closing time of a word line WL of the memory array is controlled, and the self-adaptive control of the discharge time of the bit line BL/BLB is realized.

Implementation of such an adaptive sense amplifier circuit applied to a low voltage SRAM is in accordance with the methods or processes of embodiments of the present disclosure.

In a second aspect, the present invention discloses a sense amplifier module employing an adaptive sense amplifier circuit layout as disclosed in the first aspect applied to a low voltage SRAM.

Compared with the prior art, the invention has the following beneficial effects:

the invention adjusts the connection relation between the bit line BL/BLB and the two input ends of the sensitive amplification module through the change-over switch module to realize the positive connection or the negative connection of the bit line BL/BLB and the sensitive amplification module, so that the sensitive amplification module can rapidly and continuously read two opposite signals for a subsequent error detection circuit to judge whether the read data is correct; compared with the traditional error detection circuit, the invention improves the error detection delay and greatly advances the error detection time.

2, the invention self-adaptively outputs correct data to an external combinational logic circuit after the error detection circuit module judges that the data read by the sensitive amplification module is correct, and immediately reduces the enable signal EN acting on the word line Buffer WL _ Buffer to a low level through the word line control module, thereby closing the word line WL and stopping the discharge of the bit line BL/BLB, namely reducing the discharge time of the bit line BL/BLB and obviously reducing the read power consumption of the SRAM.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor.

FIG. 1 is a diagram of simulation results of 60mV discharge delay of a prior art SRAM cell at VDD =1.2v and VDD =0.5v lower bit lines;

FIG. 2 is a diagram illustrating the existing problems of the prior art SRAM cell read operation;

FIG. 3 is a diagram illustrating the trend of the read operation power consumption and delay time of the prior art SRAM memory cell varying with the power supply voltage;

fig. 4 is a structural diagram of an adaptive sense amplifier circuit and a memory array used together in a low voltage SRAM according to embodiment 1 of the present invention;

FIG. 5 is a block diagram of the diverter switch module of FIG. 4;

FIG. 6 is a schematic diagram of the operating state of the diverter switch module of FIG. 5;

FIG. 7 is a block diagram of the sensitive amplification module of FIG. 4;

FIG. 8 is a block diagram of the error circuit block of FIG. 4;

FIG. 9 is a block diagram of the word line control module of FIG. 4;

FIG. 10 is a timing diagram illustrating a read operation of the sense amplifier circuit of FIG. 4 to determine that read data is correct when an error is first detected;

FIG. 11 is a timing diagram illustrating a read operation performed by the sense amplifier circuit of FIG. 4 to determine that read data is correct after an nth error detection;

FIG. 12 is a diagram illustrating dynamic power consumption comparison of the sense amplifier circuit of FIG. 4 for read operations at different voltages compared to a conventional scheme;

FIG. 13 is a diagram comparing turn-on time of word lines in read operation at different voltages for the sense amplifier circuit of FIG. 4 and a conventional scheme;

fig. 14 is a diagram of simulation results of the sense amplifier circuit of fig. 4 and the discharge condition of the prior art SRAM memory cell under VDD =0.6 v.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that when an element is referred to as being "mounted on" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "or/and" includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to fig. 4, a block diagram of an adaptive sense amplifier circuit applied to a low voltage SRAM and used together with a memory array is disclosed in this embodiment.

As shown in FIG. 4, an adaptive sense amplifier circuit applied to a low voltage SRAM is used for adaptively controlling the bit line BL/BLB discharge time of a memory array.

For a memory array, it includes N columns and M rows of memory cells (BITCELL). The same column of memory cells shares the same bit line BL/BLB.

It should be noted that the sense amplifier circuit with the corresponding specification is selected according to the number of columns of the memory array.

If the number of columns selected by the memory array at each time is 2 ⁱ I.e. correspond to 2 ⁱ SRAM of bits width, so that the sense amplifier circuit selected correspondingly includes 2 ⁱ Is one sensitiveAmplification module, 2 ⁱ A change-over switch module, 2 ⁱ The error detection circuit module and the 1 word line control module are connected with the error detection circuit module; i =0,1,2, \ 8230;.

The k-th change-over switch module, the k-th sensitive amplification module and the k-th error detection module are sequentially connected, and k is more than or equal to 1 and less than or equal to 2 ⁱ . J 2 th ⁱ The bit line BL/BLB of + k column is connected with the kth switch, and j is more than or equal to 0 and less than or equal to N/2 ⁱ -1。

Note that, referring to FIG. 4, the memory array is counted as 0, [0] as column 1, row 1; the sense amplifier circuit is counted as 1, and [1] is taken as the 1st column.

The sensitive amplifying module is used for reading data on the bit line BL/BLB. The switch module is connected between the sensitive amplification module and the memory array and used for switching the positive/negative connection between the bit line BL/BLB of the memory array and the sensitive amplifier when the sensitive amplification module reads data twice. The error detection circuit module is connected to the output end of the sensitive amplification module and is used for carrying out error detection comparison on even-numbered read data of the sensitive amplification module and previous odd-numbered read data of the sensitive amplification module until an output result signal FLAG is '1', and outputting the read data to an external combinational logic circuit. The word line control module is connected to the output end of the error detection circuit module and used for adjusting an enable signal EN acting on a word line Buffer WL _ Buffer according to a result signal FLAG, so that the closing time of a word line WL of the memory array is controlled, and the self-adaptive control of the discharge time of the bit line BL/BLB is realized.

For convenience of explaining the structure of each module, 1 of the diverter switch module, the sensitive amplification module and the error detection module is taken for explanation.

Referring to fig. 5, a structure diagram of the switch module is shown. The switch module includes PMOS transistors KEY1, KEY2, KEY3, and KEY4.

The source of KEY1 is connected with the bit line BL, the grid is connected with the control signal SW, and the drain is connected with the input anode IN of the sensitive amplification module. The source of KEY2 is connected with the bit line BL, the gate is connected with the control signal SWN, and the drain is connected with the input cathode INB of the sensitive amplification module. KEY3 has a source connected to bit line BLB, a gate connected to control signal SWN, and a drain connected to the positive input terminal IN of the sense amplifier module. The source of KEY4 is connected to bit line BLB, the gate is connected to control signal SW, and the drain is connected to negative input terminal INB of the sense amplifier module.

It should be noted that the control signal SW is divided into three paths; the first path directly controls KEY1; the second path directly controls KEY4; the third path is converted into a control signal SWN through a signal inverter and then is divided into two paths, wherein one path controls KEY2, and the other path controls KEY3. Therefore, the on-off states of KEY1 and KEY4 are the same, the on-off states of KEY2 and KEY3 are the same, and the on-off states of KEY1 and KEY2 are opposite.

Referring to fig. 6, a schematic diagram of the working state of the switch module is shown. That is, when the control signal SW is at a low potential, the control signal SWN is at a high potential, the bit line BL is connected to the input anode IN of the sense amplifier module through KEY1, and the bit line BLB is connected to the input cathode INB of the sense amplifier module through KEY4. When the control signal SW is at a high potential, the control signal SWN is at a low potential, the bit line BL is connected with the input cathode INB of the sensitive amplification module through KEY2, and the bit line BLB is connected with the input anode IN of the sensitive amplification module through KEY3.

Therefore, the polarity of the input voltage of the sensitive amplification module is rapidly switched by adjusting the potential of the control signal SW, so that the bit line BL/BLB is switched in a positive/negative connection mode when the sensitive amplification module reads data twice. It is emphasized that the bit line BL/BLB and the sense amplifier module are connected in the positive direction for the odd number of reads; the bit line BL/BLB is connected to the sense amplifier block in reverse for even number of reads.

In addition, 2 ⁱ The switch modules share the same control signal SW, and the whole control can be realized.

If the above is the kth switch, KEY1, KEY2, KEY3, KEY4 are KEY1[ k ]]、KEY2[k]、KEY3[k]、KEY4[k](ii) a Correspondingly, a kth sensitive amplifying module, a jth x 2 ⁱ Bit line BL/BLB of + k column, i.e. input positive IN, is IN [ k]The input negative electrode INB is INB [ k ]]Bit line BL is BL [ j × 2 ⁱ +k-1]Bit line BLB is BLB [ j 2 ] ⁱ +k-1]。

(II) refer to FIG. 7, which is a structural diagram of the sensitive amplifying module. The sensitive amplification module comprises 9 PMOS transistors P1-P9 and 3 NMOS transistors N1-N3.

The gate of P1 is connected to output node OUTN, the source is connected to power supply VDD, and the drain is connected to output node OUT. The gate of P2 is connected to the output node OUT, the source is connected to the power supply VDD, and the drain is connected to the output node OUTN. The gate of P3 is connected to the control signal EQ, the source is connected to the power supply VDD, and the drain is connected to the output node OUT. The gate of P4 is connected to the control signal EQ, the source is connected to the power supply VDD, and the drain is connected to the output node OUTN. P5 has a gate connected to the control signal RD, a source connected to the output node OUT, and a drain connected to the input anode IN. P6 has a gate connected to the control signal RD, a source connected to the output node OUTN, and a drain connected to the negative terminal INB. The gate of P7 is connected to the control signal PRE, the source is connected to the power supply VDD, and the drain is connected to the input positive electrode IN. The gate of P8 is connected to the control signal PRE, the source is connected to the power supply VDD, and the drain is connected to the input cathode INB. The grid electrode of the P9 is connected with a control signal PRE, the source electrode is connected with the positive electrode IN of the sensitive amplifying module, and the drain electrode is connected with the negative electrode INB of the input.

The gate of N1 is connected to the output node OUTN, the drain is connected to the output node OUT, and the source is connected to the node NET. The gate of N2 is connected to the output node OUT, the drain is connected to the output node OUTN, and the source is connected to the node NET. The gate of N3 is connected to the enable signal SAE, the drain is connected to the node NET, and the source is connected to ground.

Specifically, if the voltage on bit line BL is greater than the voltage on bit line BLB, output node OUT is at low level 0; when the voltage on bit line BL is less than the voltage on bit line BLB, output node OUT is high 1.

When the sensitive amplification module reads data twice and adjacently, before the next reading, the output nodes OUT and OUTN are charged to VDD through P3 and P4, and then P5 and P6 are turned on to sense the voltage difference on the bit lines BL and BLB for the second time, so that the influence of the previous amplification reading result on the error detection reading is avoided.

Referring to table one, the influence of the input of the sensitive amplification module and the offset voltage on the output of the sensitive amplification module is shown. (1) V _OFFSET >0, defined as the driving capability of N1 is stronger than that of N2; (2) v _OFFSET <0, drive with driving capability of N1 weaker than that of N2And (4) the ability to move.

Table-influence of input and offset voltage of sensitive amplifying module on output of sensitive amplifying module

As can be seen from the table I, when the bit line swing is opposite to the offset voltage polarity, the reading must be correct, and when the polarity is the same, the bit line swing must be larger than the offset voltage to read correctly (the bit line swing is defined as | V |) _BL -V _BLB |)。

In addition, 2 ⁱ The sensitive amplifying modules share the same control signal EQ, the same control signal RD, the same control signal SAE and the same control signal PRE, and the whole control can be realized.

If the amplification module is the kth sensitive amplification module, P1 to P9 are P1[ k ] to P9[ k ]; N1-N3 are N1[ k ] to N3[ k ]. The output node OUTN is OUTN [ k ], the output node OUT is OUT [ k ], the input anode IN is IN [ k ], the input cathode INB is INB [ k ], and the node NET is the node NET [ k ].

Third, referring to fig. 8, a block diagram of an error detection circuit module is shown. The error detection circuit module comprises a D flip-flop LATCH, a transmission gate TG1, a transmission gate TG2, a two-input exclusive-OR gate XOR and a transmission gate TG3.

The first input end of the D trigger LATCH is connected with an output node OUT of the sensitive amplification module, the second input end of the D trigger LATCH is connected with a clock signal LA, and the output is divided into two paths.

The input end of the transmission gate TG1 is connected with one output of the D flip-flop LATCH, and the enabling end is connected with an enabling signal CO. The input end of the transmission gate TG2 is connected with the output node OUT of the sensitive amplification module, and the enabling end of the transmission gate TG2 is connected with an enabling signal CO. The first input end of the two-input exclusive-or gate XOR is connected with the output end of the transmission gate TG1, the second input end of the two-input exclusive-or gate XOR is connected with the output end of the transmission gate TG2, and the output end of the two-input exclusive-or gate XOR outputs the result signal FLAG. The first input end of the transmission gate TG3 is connected with the other output of the D flip-flop LATCH, the second input end of the transmission gate TG3 is connected with the result signal FLAG, and the output end of the transmission gate TG outputs a data signal Right _ OUT.

Specifically, for an odd read and an even read following it:

firstly, looking at the odd number of times, the D trigger LATCH controls to LATCH the read result 1st _OUTof the odd number of times through the clock signal LA, the transmission gates TG1 and TG2 are both closed, and therefore the XOR of the two input XOR gates has no result comparison;

then, even number of times is carried out, after a result 2nd_OUT is read out, the transmission gates TG1 and TG2 are opened, the 2nd _OUTis transmitted to the two-input exclusive OR gate XOR through the transmission gate TG2, one path of output 1st _OUTof the D trigger LATCH is transmitted to the two-input exclusive OR gate XOR through the transmission gate TG1, and the two-input exclusive OR gate XOR compares the two read-out results, so that the error detection function is realized.

If the error detection circuit module judges that the reading is correct, the FLAG signal is output to the word line control module to be 1, and then the turning-off of the word line WL is controlled, and the self-adaption discharge stopping of the bit line BL/BLB is achieved. When the FLAG signal is "1", the transmission gate TG3 is also controlled to be opened, and the other output 1st OUT of the D flip-flop LATCH passes through the transmission gate TG3, so that the correct read data Right _ OUT is adaptively output.

Referring to table two, it is the relationship between the error detection result of the error detection circuit module and the swing of the bit line of the memory cell in this embodiment.

TABLE II error detection result vs. memory cell bit line swing

As shown in table 2, 1st _outindicates odd-numbered read data, and 2nd _outindicates even-numbered read data. The two are the same, and the output result signal FLAG is 0; the two are different, and the output result signal FLAG is "1".

The error detection circuit may erroneously determine that FLAG is "0" although the output is correct. However, the loss of energy for this case is almost negligible, because as the bit line swing increases, the false decision is quickly eliminated and the probability of this occurring is extremely small.

To say thatIt is clear that 2 ⁱ The error detection modules share the same clock signal LA.

If the above is the kth error detection circuit block, the D flip-flop LATCH is LATCH [ k ], the transmission gates TG1, TG2, TG3 are TG1[ k ], TG2[ k ], TG3[ k ], the XOR of the two-input XOR gates is XOR [ k ], and the result signal FLAG is FLAG [ k ], and the data signal Right _ OUT is Right _ OUT [ k ].

Namely the kth error detection block outputs the result signal FLAG [ k ], and the data signal Right _ OUT [ k ].

(IV) referring to FIG. 9, it is a structural diagram of the word line control module. The word line control module comprises a PMOS transistor MP, a capacitor CAP, and a capacitor 2 ⁱ An NMOS transistor M [1]～M[2 ⁱ ]。

The gate of the PMOS transistor MP is connected to the PRE-charge signal PRE, the source is connected to the power supply VDD, and the drain is connected to the output node Ctr _ OUT. The output node Ctr _ OUT outputs an enable signal EN. The upper electrode of the capacitor CAP is connected to the output node Ctr _ OUT, and the lower electrode is connected to the power ground.

M[1]～M[2 ⁱ ]Sequentially connected in series, and the last NMOS tube M [ h ]]Is connected to the next NMOS transistor M [ h + 1]]H is more than or equal to 1 and less than or equal to 2 ⁱ -1。

Wherein, the kth NMOS transistor M [ k]Gate connection result signal FLAG [ k ]]，M[1]Is connected to the output node Ctr _ OUT, M [2 ] ⁱ ]Is connected to power ground.

In addition, the word line control module 2 ⁱ The sensitive amplifying modules share the same control signal PRE.

The memory cells in the same row share the same word line WL. The enable signal EN is connected to M word line buffers WL _ Buffer of M rows of memory cells, and is used to perform unified control on the M word line buffers WL _ Buffer.

Specifically, MP is responsible for charging capacitor CAP before receiving FLAG signal, keeping enable signal EN at high level, M [1]]～M[2 ⁱ ]The system is responsible for receiving the FLAG signal and controlling the working state of the system by the FLAG signal: when FLAG [1]]～FLAG[2 ⁱ ]When all the signals are high level "1", a leakage path exists between the enable signal EN and the power ground, the level of the enable signal EN is low "0", thereby controlling the word line Buffer WL _ Buffer to stop working, and the word line WL is turned off, thereby achieving adaptive control of the discharge time of the bit line BL/BLB.

In addition, the word line WL of each row is connected to a row Decoder (DEW) through a word line Buffer WL _ Buffer; the row decoder is used to select the particular row of the memory array that needs to be opened. Each column of memory cells is connected with a column selection circuit (MUX), and the column selection circuit is controlled by a column decoder to select a specific column of the memory array which needs to be opened.

Example 2

This embodiment 2 discloses timing charts of two cases when the sense amplifier circuit of embodiment 1 performs a read operation.

Referring to FIG. 10, a single example is shown, the timing of the read operation is determined to be correct by first error detection.

Specifically, the method comprises the following steps: in the first step, word line WL is turned on, bit line BL/BLB discharges, after a short time, SAE signal enables, sensitive amplification module starts, and D flip-flop LATCH latches read data to be compared with error detection read data. Secondly, closing P5, P6 and N3, opening P3 and P4 to recharge two output nodes of the sensitive amplification module to VDD, and quickly adjusting the polarity of the input voltage of the sensitive amplification module; then the control signal RD controls P5 and P6 to be turned on again, SAE signals are enabled for the second time, the sensitive amplification module is started for the second time, error detection data are read, transmission tubes TG1 and TG2 are controlled to be turned on through a control signal CO, the XOR output result signal FLAG of the two input XOR gates is '1', the first read result is correct, data are output to an external combinational logic circuit quickly, the result signal FLAG is input to the word line control module, a leakage path exists between an enable signal EN and a power ground, the EN level is low '0', further M word line buffers WL _ Buffer are controlled to stop working uniformly, word lines WL are turned off, bit lines BL/BLB stop discharging, and the read operation is finished.

Referring to FIG. 11, a timing diagram of a read operation in which the nth error detection determines that the read data is correct is shown as an example.

Specifically, in the first step, the word line WL is turned on, the bit line BL/BLB is discharged, after a short time, the SAE signal is enabled, the sense amplifier module is enabled, and the D flip-flop LATCH latches the read data to be compared with the error detection read data. And secondly, closing P5, P6 and N3, opening P3 and P4 to recharge two output nodes of the sensitive amplification module to VDD, quickly adjusting the polarity of input voltage of the sensitive amplification module, then controlling P5 and P6 to be opened again by a control signal RD, enabling SAE signals for the second time, starting the sensitive amplification module for the second time, reading error detection data, controlling transmission tubes TG1 and TG2 to be opened by a control signal CO, reading data errors if a result signal FLAG output by a two-input exclusive-OR gate is 0, inputting the FLAG into a word line control module, keeping the EN level at a high potential, controlling the word line WL to be continuously started, continuously discharging the bit line BL/BLB, further amplifying the swing amplitude of the bit line BL/BLB, starting the sensitive amplification module again, and sequentially circulating until the data are correctly read.

In this embodiment 2, simulation comparison is also performed between the adaptive sense amplifier circuit applied to the low-voltage SRAM in embodiment 1 and the conventional scheme SA, comparison between dynamic power consumption of the adaptive sense amplifier circuit and dynamic power consumption of the adaptive sense amplifier circuit applied to the low-voltage SRAM under different voltages is compared, and a schematic comparison diagram is shown in fig. 12. The simulation conditions are 1.2V, 1.1V, 1.0V, 0.9V, 0.8V, 0.7V and 0.6V respectively, the ttg process angle is 27 ℃.

The results show that: the adaptive sense amplifier circuit design scheme applied to the low-voltage SRAM provided in embodiment 1 has lower power consumption than the conventional scheme SA at a low operating voltage, and the lower the operating voltage, the larger the power consumption reduction amplitude, and thus has a better application prospect.

Similarly, this embodiment 2 also performs simulation comparison on the adaptive sense amplifier circuit applied to the low voltage SRAM in embodiment 1 and the conventional scheme SA, and compares the turn-on time of the word line during the read operation under different voltages, and the comparison schematic diagram is shown in fig. 13. The simulation conditions are 1.2V, 1.1V, 1.0V, 0.9V, 0.8V, 0.7V and 0.6V respectively, the ttg process angle is 27 ℃.

The results show that: the adaptive sense amplifier circuit design scheme applied to the low-voltage SRAM provided in embodiment 1 is shorter in average word line turn-on time at low operating voltage than the conventional scheme SA, and also proves the simulation result of the above power consumption.

In addition, in this embodiment 2, the adaptive sense amplifier circuit applied to the low voltage SRAM in embodiment 1 and the discharging condition of the prior art SRAM memory cell in the background art are also simulated, and the result graph is shown in fig. 14. The results show that: most correct results are read out in the first 4 times, the word line WL is closed before 6ns in most read operations, and by using the traditional scheme, all the word line WLs need to be opened for 12ns in the read operation process.

Example 3

On the basis of the adaptive sense amplifier circuit applied to the low-voltage SRAM disclosed in embodiment 1, embodiment 3 further discloses a sense amplifier module, which adopts the sense amplifier circuit layout disclosed in embodiment 1.

The mode of packaging into a module is easier for popularization and application of the self-adaptive sense amplifier circuit applied to the low-voltage SRAM.

The interface of the sensitive amplifier module comprises:

SW interface, BL [0]]interface-BL 2 ⁱ -1]Interface, BLB [0]]interface-BLB 2 ⁱ -1]Interface, EQ interface, RD interface, SAE interface, PRE interface, LA interface, CO interface, right _ OUT [1]]Interface Right _ OUT [2 ] ⁱ ]Interface, EN interface.

The SW interface is used for transmitting a control signal SW.

BL[0]The interface is used for connecting with bit lines BL [ j ] 2 ⁱ ]Connecting; BL [1]]The interface is used for connecting with bit lines BL [ j ] 2 ⁱ +1]Connecting; 8230; BL [2 ] ⁱ -1]The interface is used for connecting with bit lines BL [ j ] 2 ⁱ +2 ⁱ -1]And (4) connecting.

BLB[0]The interface being for connection to bit lines BLB [ j ] 2 ⁱ ]Connecting; BLB [1]]The interface being for connection to bit lines BLB [ j × 2[ ] ⁱ +1]Connecting; 8230; BLB 2 ⁱ -1]The interface being for connection to bit lines BLB [ j ] 2 ⁱ +2 ⁱ -1]And (4) connecting.

The EQ interface is used to transmit control signals EQ. The RD interface is used for transmitting the control signal RD. The SAE interface is used to transmit an enable signal SAE. The PRE interface is used for transmitting a control signal PRE. The LA interface is used to transmit a clock signal LA. The CO interface is used for transmitting the enable signal CO.

Right_OUT[1]Interface for interfacing with data signal Right _ OUT [1]]Connecting; right _ OUT [2]Interface for interfacing with data signal Right _ OUT [2 ]]Connecting; 8230; right _ OUT [2 ⁱ ]Interface for data signal Right _ OUT [2 ] ⁱ ]And (4) connecting. The EN interface is used to transmit an enable signal EN.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. An adaptive sense amplifier circuit applied to a low voltage SRAM for adaptively controlling a bit line BL/BLB discharge time of a memory array and adaptively outputting correct data, the adaptive sense amplifier circuit comprising:

the sensitive amplification module is used for reading data on the bit line BL/BLB;

the switch module is connected between the sensitive amplification module and the storage array and is used for switching the positive/negative connection between a bit line BL/BLB of the storage array and the sensitive amplifier when the sensitive amplification module reads data for two times;

the error detection circuit module is connected to the output end of the sensitive amplification module and is used for carrying out error detection comparison on even-numbered read data of the sensitive amplification module and previous odd-numbered read data of the sensitive amplification module until an output result signal FLAG is '1' and outputting correct read data to an external combinational logic circuit; and

and the word line control module is connected to the output end of the error detection circuit module and is used for adjusting an enable signal EN acting on a word line Buffer WL _ Buffer according to a result signal FLAG so as to control the closing time of the word line WL of the memory array and realize the self-adaptive control of the discharge time of the bit line BL/BLB.

2. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 1, wherein said switch module, sense amplifier module, and error detection module are all set to 2 ⁱ I =0,1,2, \ 8230; the change-over switch module, the sensitive amplification module and the error detection module correspond to each other one by one, the kth change-over switch module, the kth sensitive amplification module and the kth error detection module are connected in sequence, and k is greater than or equal to 1 and less than or equal to 2 ⁱ 。

3. The adaptive sense amplifier circuit applied to the low-voltage SRAM as claimed in claim 2, wherein the kth sense amplifier module comprises:

the grid of the kth PMOS transistor P1[ k ], P1[ k ] is connected with the kth output node OUTN [ k ], the source is connected with the power supply VDD, and the drain is connected with the kth output node OUT [ k ];

the grid of the kth PMOS transistor P2[ k ], P2[ k ] is connected with the output node OUT [ k ], the source is connected with the power supply VDD, and the drain is connected with the output node OUTN [ k ];

the grid electrode of the kth PMOS transistor P3[ k ], P3[ k ] is connected with a control signal EQ, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an output node OUT [ k ];

the grid electrodes of the kth PMOS transistors P4[ k ] and P4[ k ] are connected with a control signal EQ, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an output node OUTN [ k ];

the grid electrode of the kth PMOS transistor P5[ k ], P5[ k ] is connected with the control signal RD, the source electrode is connected with the output node OUT [ k ], and the drain electrode is connected with the kth input anode IN [ k ];

the grid electrodes of the kth PMOS transistors P6[ k ] and P6[ k ] are connected with a control signal RD, the source electrodes are connected with an output node OUTN [ k ], and the drain electrodes are connected with the kth input negative electrode INB [ k ];

the grid electrode of the kth PMOS transistor P7[ k ], P7[ k ] is connected with a control signal PRE, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an input positive electrode IN [ k ];

the grid electrode of the kth PMOS transistor P8[ k ], P8[ k ] is connected with a control signal PRE, the source electrode is connected with a power supply VDD, and the drain electrode is connected with an input cathode INB [ k ];

the grid electrodes of the kth PMOS transistors P9[ k ], P9[ k ] are connected with a control signal PRE, the source electrodes are connected with an input positive electrode IN [ k ], and the drain electrodes are connected with an input negative electrode INB [ k ];

the grid of the kth NMOS transistor N1[ k ], N1[ k ] is connected with an output node OUTN [ k ], the drain is connected with an output node OUT [ k ], and the source is connected with the kth node NET [ k ];

the grid of the kth NMOS transistor N2[ k ], N2[ k ] is connected with the output node OUT [ k ], the drain is connected with the output node OUTN [ k ], and the source is connected with the node NET [ k ]; and

the gate of the kth NMOS transistor N3[ k ], N3[ k ] is connected to the enable signal SAE, the drain is connected to the node NET [ k ], and the source is connected to the power ground.

4. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 3, wherein said memory array comprises N columns and M rows of memory cells; the same column of memory cells shares the same bit line BL/BLB; j 2 th ⁱ The bit line BL/BLB of + k column is connected with the kth switch, and j is more than or equal to 0 and less than or equal to N/2 ⁱ -1；

The kth diverter switch module comprises:

kth PMOS transistor KEY1[ k ]]，KEY1[k]Is connected to the j 2 th source ⁱ + k bit lines BL [ j × 2 ⁱ +k-1]A gate connected to the control signal SW, a drain connected to the input anode IN [ k ]]；

Kth PMOS transistor KEY2[ k ]]，KEY2[k]Is connected to bit line BL [ j 2 ] ⁱ +k-1]A gate connected to the control signal SWN, a drain connected to the input cathode INB [ k ]]；

The kth PMOS transistor KEY3[ k ]]，KEY3[k]Is connected to the j 2 th source ⁱ + k bit lines BLB [ j × 2 ⁱ +k-1]A gate connected to a control signal SWN, a drain connected to an input positive electrode IN [ k ]](ii) a And

the kth PMOS transistor KEY4[ k ]]，KEY4[k]Is connected to bit line BLB [ j 2 ] ⁱ +k-1]Grid is connected toA drain connected to the input cathode INB k]。

5. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 2, wherein said control signal SW is divided into three paths; the first path directly controls KEY1[ k ]; the second path directly controls KEY4[ k ]; the third path is converted into a control signal SWN through a signal inverter and then is divided into two paths, wherein one path controls KEY2[ k ] and the other path controls KEY3[ k ].

6. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 2, wherein the kth error detection circuit module comprises:

a kth D flip-flop LATCH [ k ], wherein the input end I is connected with an output node OUT [ k ], the input end II is connected with an enable signal CO, and the output is divided into two paths;

the kth transmission gate TG1[ k ], the input end of which is connected with one output of the D trigger LATCH [ k ], and the enable end of which is connected with an enable signal CO;

a kth transmission gate TG2[ k ], the input end of which is connected with the output node OUT [ k ], and the enabling end of which is connected with an enabling signal CO;

a kth two-input exclusive-or gate XOR [ k ], of which the input end one is connected with the output end of the transmission gate TG1[ k ], the input end two is connected with the output end of the transmission gate TG2[ k ], and the output end outputs a kth result signal FLAG [ k ]; and

the kth transmission gate TG3[ k ], whose input end one is connected with the other output of the D flip-flop LATCH [ k ], whose input end two is connected with the result signal FLAG [ k ], and whose output end outputs the kth data signal Right _ OUT [ k ].

7. The adaptive sense amplifier circuit applied to low-voltage SRAM of claim 6, wherein the word line control module comprises:

a PMOS tube MP, the grid electrode of which is connected with a PRE-charge signal PRE, the source electrode of which is connected with a power supply VDD, and the drain electrode of which is connected with an output node Ctr _ OUT; the output node Ctr _ OUT outputs an enable signal EN;

the upper electrode of the capacitor CAP is connected with the output node Ctr _ OUT, and the lower electrode of the capacitor CAP is connected with the power ground; and

2 ⁱ an NMOS transistor M [1]～M[2 ⁱ ]，M[1]～M[2 ⁱ ]Sequentially connected in series, and the last NMOS tube M [ h ]]Is connected to the next NMOS transistor M [ h + 1]]H is more than or equal to 1 and less than or equal to 2 ⁱ -1; wherein, the Kth NMOS transistor M [ K ]]Gate connection result signal FLAG k]，M[1]Is connected to the output node Ctr _ OUT, M [2 ] ⁱ ]Is connected to power ground.

8. The adaptive sense amplifier circuit applied to the low-voltage SRAM of claim 7, wherein the same row of memory cells share the same word line WL; the enable signal EN is connected to M word line buffers WL _ Buffer of the M rows of memory cells, and controls the M word line buffers WL _ Buffer to stop operating in unison when the enable signal EN is low.

9. The adaptive sense amplifier circuit applied to low-voltage SRAM as claimed in claim 7, wherein 2 ⁱ The switching switch modules share the same control signal SW;2 ⁱ The sensitive amplification modules share the same control signal EQ, the same control signal RD and the same control signal SAE;2 ⁱ The error detection modules share the same clock signal LA; word line control module, 2 ⁱ The sensitive amplifying modules share the same control signal PRE.

10. A sense amplifier module, characterized in that an adaptive sense amplifier circuit layout according to any of claims 1-9 is used.