CN214201543U

CN214201543U - JTAG-based chip connection structure

Info

Publication number: CN214201543U
Application number: CN202023287600.0U
Authority: CN
Inventors: 张明洋
Original assignee: Shanghai Keliang Information Technology Co ltd
Current assignee: Shanghai Keliang Information Technology Co ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-09-14
Anticipated expiration: 2030-12-30

Abstract

The utility model discloses embodiment relates to embedded field, discloses a chip connection structure based on JTAG. The method comprises the following steps: the first JTAG interface, the signal selector and the N chips; the first JTAG interface and the N chips are respectively provided with a mode selection TMS end, a data input TDI end, a clock TCK end and a data output TDO end; TMS ends of the N chips are connected to the TMS end of the first JTAG interface; the TDI ends of the N chips are connected to the TDI end of the first JTAG interface; TCK ends of the N chips are connected to a TCK end of the first JTAG interface; the TDO terminal of the first JTAG interface is connected to the first terminal of the signal selector, and the TDO terminals of the N chips are connected to the N second terminals of the signal selector. According to the JTAG-based chip connection structure provided by the embodiment of the application, signals can directly reach a chip to be processed or a chip group to be processed without flowing through a non-target chip, the signal transmission time delay of the target chip is shorter, and the signal transmission efficiency of the chip can be improved.

Description

JTAG-based chip connection structure

Technical Field

The utility model discloses embodiment relates to embedded field, in particular to chip connection structure based on JTAG.

Background

Joint Test Action Group (JTAG) is an international standard Test protocol (IEEE 1149.1 compliant) and is mainly used for chip internal Test. Most of the existing embedded processing chips support the JTAG protocol to perform online debugging or program upgrading, such as Field Programmable Gate Array (FPGA), Digital Signal Processor (DSP), Advanced RISC Machine (ARM), Microprocessor (MCU), etc.

When a system contains a plurality of embedded processing chips, the related technology adopts a single JTAG interface to serially connect all the chips in a daisy chain manner to realize downloading programming, so that the PCB space occupied by a plurality of JTAG interfaces can be saved; when the embedded system is in the closed case, the JTAG interface can be led out of the closed case without disassembly. However, for serial links implemented in a daisy chain manner by the JTAG interface, signals need to be transmitted in the serial link sequence, and the signals cannot be quickly transmitted to a designated chip or a chipset with the same function.

Disclosure of Invention

An object of the embodiment of the utility model is to provide a chip connection structure based on JTAG improves the efficiency of signal transmission to appointed chip.

In order to solve the above technical problem, an embodiment of the present invention provides a chip connection structure based on JTAG, including:

the first JTAG interface, the signal selector and the N chips; the first JTAG interface and the N chips are provided with a Mode selection (TMS) end, a Data input (Test Data In, TDI) end, a Clock (Test Clock, TCK) end and a Data output (Test Data Out, TDO) end;

TMS ends of the N chips are connected to the TMS end of the first JTAG interface;

the TDI ends of the N chips are connected to the TDI end of the first JTAG interface;

TCK ends of the N chips are connected to a TCK end of the first JTAG interface;

the TDO ends of the N chips are connected to the TDO end of the first JTAG interface through a signal selector; the TDO terminal of the first JTAG interface is connected to the first terminal of the signal selector, and the TDO terminals of the N chips are connected to the N second terminals of the signal selector.

The utility model discloses embodiment is for prior art, and the chip connection structure based on JTAG that proposes is connected for parallel, mainly sets up the selection that the signal selector realized treating the processing chip through the TDO end. In the related technology, the serial connection is performed in a daisy chain manner, and when signals are transmitted to a chip to be processed, all chip connection structures in front of the chip to be processed need to be traversed; and the utility model provides a chip connection structure based on JTAG, the pending chip or the pending chip group that can reach by the signal need not flow through the non-target chip, and signal transmission time delay to the target chip is shorter, can improve the signal transmission efficiency to the chip.

In addition, a signal selector includes: a multiplexer; the TDO terminal of the first JTAG interface is connected to the first terminal of the multiplexer, and the TDO terminals of the N chips are connected to the N second terminals of the multiplexer.

In addition, the signal selector further includes: an encoder connected to the multiplexer; the first end of the encoder is connected to a power supply, the second end of the encoder is grounded, and the third end of the encoder is connected to the third end of the multiplexer.

In addition, the JTAG-based chip connection structure further includes: n paths of parallel switches; TCK ends of the N chips are connected to a TCK end of the first JTAG interface through the N paths of parallel switches; the TCK end of the first JTAG interface is connected to the first end of the N-path parallel switch, and the TCK ends of the N chips are connected to the N second ends of the N-path parallel switch.

In addition, the JTAG-based chip connection structure further includes: n paths of parallel switches; the TDI ends of the N chips are connected to the TDI end of the first JTAG interface through the N paths of parallel switches; the TDI end of the first JTAG interface is connected to the first end of the N-path parallel switch, and the TDI ends of the N chips are connected to the N second ends of the N-path parallel switch.

In addition, the JTAG-based chip connection structure further includes: n paths of parallel switches; TMS ends of the N chips are connected to a TMS end of the first JTAG interface through the N paths of parallel switches; the TMS end of the first JTAG interface is connected to the first end of the N-path parallel switch, and the TMS ends of the N chips are connected to the N second ends of the N-path parallel switch.

In addition, the JTAG-based chip connection structure further includes: a first driver, a second driver and a third driver; TMS ends of the N chips are connected to a TMS end of the first JTAG interface through a first driver; the TDI ends of the N chips are connected to the TDI end of the first JTAG interface through a second driver; the TCK terminals of the N chips are connected to the TCK terminal of the first JTAG interface through a third driver.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a schematic diagram of a JTAG-based chip connection arrangement according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of a multiplexer according to a first embodiment of the present application;

FIG. 3 is a schematic diagram of an encoder according to a first embodiment of the present application;

FIG. 4 is a schematic diagram of a JTAG-based chip connection arrangement according to a second embodiment of the present application;

FIG. 5 is a schematic diagram of another JTAG-based chip connection configuration according to a second embodiment of the present application;

fig. 6 is a schematic diagram of a JTAG-based chip connection structure according to a third embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present invention, and the embodiments may be mutually incorporated and referred to without contradiction.

The terms "first" and "second" in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, the terms "comprise" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a system, product or apparatus that comprises a list of elements or components is not limited to only those elements or components but may alternatively include other elements or components not expressly listed or inherent to such product or apparatus. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise.

The utility model discloses a first embodiment relates to a chip connection structure based on JTAG. The method is applied to parallel computation based on an embedded processing chip, such as JTAG connection of Multiple FPGAs In 5G large-scale antennas (Massive Multiple-In Multiple-Out, Massive MIMO); or in the application of Modular Multilevel Converter (MMC) digital simulation equipment in the field of power electronic simulation test, the multi-FPGA JTAG connection of the independent low-speed optical fiber transceiving protocol, which is up to thousands in number and connects with the valve control equipment, is realized. As shown in particular in figure 1.

A first JTAG interface 101, a signal selector 102, N chips 103; the first JTAG interface 101 and the N chips 103 are respectively provided with a mode selection TMS end, a data input TDI end, a clock TCK end and a data output TDO end; TMS ends of the N chips 103 are connected to a TMS end of the first JTAG interface 101; the TDI terminals of the N chips 103 are connected to the TDI terminal of the first JTAG interface 101; the TCK ends of the N chips 103 are connected to the TCK end of the first JTAG interface 101; the TDO terminals of the N chips 103 are connected to the TDO terminal of the first JTAG interface through the signal selector 102; among them, the TDO terminal of the first JTAG interface 101 is connected to the first terminal of the signal selector 102, and the TDO terminals of the N chips 103 are connected to the N second terminals of the signal selector 102. In fig. 1, Chip refers to Chip, i.e., Chip1 is Chip1, Chip2 is Chip2, and Chip N is Chip N.

In practical application, if a signal needs to be transmitted to a specific chip 103 to complete upgrading, the TDO end of the chip 103 is communicated with the TDO end of the first JTAG interface 101 by controlling the signal selector 102; since no other chip exists on the connection path between the first JTAG interface 101 and the chip 103, and the connection state is direct connection, the signal to be transmitted can be transmitted to the chip 103 with a relatively low delay. If a signal needs to be transmitted to the chipset 1031 to complete the upgrade, wherein the chipset 1031 includes m chips 103 that need to be upgraded with the same function; the TDO end of the first JTAG interface 101 can only process one signal at the same time, so that any one of the TDO ends of m chips 103 in the designated chipset 1031 needs to be communicated with the TDO end of the first JTAG interface 101 by controlling the signal selector 102, and after the TDO end of any one of the chips 103 is communicated with the TDO end of the first JTAG interface 101, since the chip feedback signals of the same function are the same, the other chips 103 in the designated chipset 1031 that need to be upgraded with the same function can also be upgraded; in addition, since the first JTAG interface 101 and the chip 103 in the designated chipset 1031 are both in a direct connection relationship, that is, the chips in the designated chipset 1031 can simultaneously realize the upgrading of the same function with low time delay.

It should be noted that, in fig. 1, the first device 104 is only used to describe a connection relationship between the first JTAG interface 101 and an external device in practical application, the first JTAG interface 101 is located in the first device 104 or has a communication connection with the first device 104, and the first device 104 is used to provide signals transmitted to a chip in the JTAG-based chip connection structure. The first device 104 is not part of the JTAG-based chip attach architecture; in practical applications, different first devices 104 may be replaced according to actual requirements, and the specific type of the first device 104 is not limited in this embodiment.

In addition, the N chips 103 only need to have the TMS terminal, the TDI terminal, the TCK terminal, and the TDO terminal at the same time in one example, and the structures other than these four ports are not limited to be identical.

In one example, the signal selector 102 includes a multiplexer 1021, wherein the TDO terminal of the first JTAG interface is connected to a first terminal of the multiplexer 1021, and the TDO terminals of the N chips 103 are connected to N second terminals of the multiplexer 1021; multiplexer 1021 is used to select which of the TDO terminals of the first JTAG interface and N chips 103 is on. For ease of understanding, the implementation principle of the multiplexer is illustrated in fig. 2 in a 1-out-of-16 configuration of a CD4067 chip, in which the selection of the connection channel of CD4067 is controlled by A, B, C, D, Inh five interface levels, whose logic truth table is shown in table 1:

TABLE 1 CD4067 logic truth table

A	B	C	D	Inh	Connecting channel
						x	x	x	x	1	None
0	0	0	0	0	0
						1	0	0	0	0	1
0	1	0	0	0	2
						1	1	0	0	0	3
0	0	1	0	0	4
						1	0	1	0	0	5
0	1	1	0	0	6
						1	1	1	0	0	7
0	0	0	1	0	8
						1	0	0	1	0	9
0	1	0	1	0	10
						1	1	0	1	0	11
0	0	1	1	0	12
						1	0	1	1	0	13
0	1	1	1	0	14
						1	1	1	1	0	15

Wherein the control signal for controlling the A, B, C, D, Inh interface level is obtained by an external device communicatively connected thereto, or by receiving a user command, wherein the user command may be a manual action. When no operation is desired on any chip, Inh may be set high.

In one example, the signal selector 102 further includes an encoder 1022 connected to the multiplexer; a first terminal of the encoder 1022 is connected to a power supply, a second terminal of the encoder 1022 is grounded, and a third terminal of the encoder 1022 is connected to the third terminal of the multiplexer 1021. For ease of understanding, a five-bit encoder configured with a 16-to-1 multiplexer is taken as an example to illustrate a specific implementation principle of the encoder 1022. Wherein the control signal is provided using an external device (not shown) communicatively coupled to the fourth terminal of the encoder 1022; or the control signal is obtained inside the encoder in a manner of controlling a switch, as shown in fig. 3, the switch portion may be any one type of mechanical micro-motion switch, electronic inductive switch, photoelectric inductive switch, and infrared inductive switch. Wherein, the A, B, C, D, Inh interface at the third end of the encoder 1022 is correspondingly connected with the A, B, C, D, Inh interface at the third end of the multiplexer 1021.

In this embodiment, a JTAG-based chip connection structure is proposed as a parallel connection, and a signal selector is provided at the TDO terminal to select a chip to be processed. In the related technology, the serial connection is carried out in a daisy chain mode, and when signals are transmitted to a chip to be processed, all chip connection structures in front of the chip to be processed need to be traversed; according to the JTAG-based chip connection structure, signals can directly reach a chip to be processed or a chip group to be processed without flowing through a non-target chip, so that the signal transmission time delay of the target chip is shorter, and the signal transmission efficiency of the chip can be improved.

The utility model discloses a second embodiment relates to a chip connection structure based on JTAG, compares in first embodiment, still includes N way parallel switch 201, and wherein, N way parallel switch 201 can have N first ends, or N way parallel switch 201's N first end polymerization is all the way.

The TCK terminals of the N chips 103 are connected to the TCK terminal of the first JTAG interface 101 through the N-way parallel switch 201; the TCK terminal of the first JTAG interface 101 is connected to the first terminal of the N-way parallel switch 201, and the TCK terminals of the N chips 103 are connected to the N second terminals of the N-way parallel switch 201, as shown in fig. 4.

In the specific implementation process, the TCK terminal is mainly used for transmitting an independent and basic clock signal, and all operations are driven by the clock signal. After the N paths of parallel switches 201 are added, the N paths of parallel switches 201 control the on-off of clock signal transmission to determine whether the chip 103 is driven or not, so that the operation on a non-target chip is avoided, the misoperation in the debugging process of the chip is prevented, and the misoperation in the function upgrading process of the chip is also avoided.

In one example, the TDI terminals of the N chips 103 are connected to the TDI terminal of the first JTAG interface 101 through the N-way parallel switch 201; the TDI terminal of the first JTAG interface 101 is connected to the first terminal of the N-way parallel switch 201, and the TDI terminals of the N chips 103 are connected to the N second terminals of the N-way parallel switch 201, as shown in fig. 5.

In a specific implementation process, the TDI terminal of the chip 103 is a signal inflow terminal, and whether a control signal flows into the chip 103 is controlled by the N-way parallel switch 201 of the TDI terminal. In this embodiment, an N-way parallel switch 201 is added to assist in controlling the signal input to the chip, and the target chip or the target chip set is selected according to whether the control data is input, thereby achieving the effect of matching the control clock input.

The utility model discloses a third embodiment relates to a chip connection structure based on JTAG, compares in first embodiment, still includes: a first driver 301, a second driver 302 and a third driver 303.

In one example, the TMS terminals of the N chips 103 are connected to the TMS terminal of the first JTAG interface 101 through a first driver 301; the TDI terminals of the N chips 103 are connected to the TDI terminal of the first JTAG interface 101 through a second driver 302; the TCK terminals of the N chips 103 are connected to the TCK terminal of the first JTAG interface 103 through the third driver 303, as shown in fig. 6.

Since the first JTAG interface 101 needs to drive the N chips 103, if the number of the chips 103 that need to be driven at the same time is too large, the first JTAG interface 101 may fail to meet the transmission requirement, and the signal transmission quality of the chip 103 is affected in terms of the result. In this embodiment, drivers are respectively added to the TMS terminal, the TDI terminal, and the TDI terminal of the first JTAG interface 101, so as to improve the signal transmission quality of the first JTAG interface 101 to the plurality of chips 103 at the same time; for the TDO terminal, a signal selector is present to limit processing of only one signal at a time, so no signal drive setting is required.

In addition, the first driver 301, the second driver 302, and the third driver 303 do not conflict with the connection structure in the second embodiment, and may be applied to the connection structure in the second embodiment for improving the driving functions of the TMS terminal, the TDI terminal, and the TDI terminal.

It should be noted that the first driver 301, the second driver 302, and the third driver 303 are not limited to be driving structures that operate independently; if there is a device that simultaneously drives any combination of the TMS terminal, TDI terminal, and TCK terminal of the first JTAG interface 101, for example, the first driver 301 and the second driver 302 may be replaced by a combination of driving devices, the combination of driving devices (not shown in the figure) and the third driver 303 are used to implement the driving function in this embodiment.

In this embodiment, a driving device is added to the TMS terminal, the TDI terminal, and the TCK terminal in the first JTAG interface 101 to ensure the parallel signal transmission quality of the first JTAG interface 101 to the plurality of chips 103 at the same time, so that the JTAG-based chip connection structure is more reasonable, and the user experience is improved.

It will be understood by those skilled in the art that the foregoing embodiments are specific to the implementation of the present invention and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application.

Claims

1. A JTAG-based chip attach structure, comprising: the first JTAG interface, the signal selector and the N chips; the first JTAG interface and the N chips are respectively provided with a mode selection TMS end, a data input TDI end, a clock TCK end and a data output TDO end;

the TCK ends of the N chips are connected to the TCK end of the first JTAG interface;

the TDO ends of the N chips are connected to the TDO end of the first JTAG interface through the signal selector; wherein, the TDO terminal of the first JTAG interface is connected to the first terminal of the signal selector, and the TDO terminals of the N chips are connected to the N second terminals of the signal selector.

2. The JTAG-based chip connection structure of claim 1, wherein the signal selector includes: a multiplexer;

wherein the TDO terminal of the first JTAG interface is connected to the first terminal of the multiplexer, and the TDO terminals of the N chips are connected to the N second terminals of the multiplexer.

3. The JTAG-based chip connection structure of claim 2, wherein the signal selector further includes: an encoder connected to the multiplexer;

the first end of the encoder is connected to a power supply, the second end of the encoder is grounded, and the third end of the encoder is connected to the third end of the multiplexer.

4. The JTAG-based chip connection structure of claim 1, further comprising: n paths of parallel switches;

the TCK ends of the N chips are connected to the TCK end of the first JTAG interface through the N paths of parallel switches;

the TCK end of the first JTAG interface is connected to the first end of the N-path parallel switch, and the TCK ends of the N chips are connected to the N second ends of the N-path parallel switch.

5. The JTAG-based chip connection structure of claim 1, further comprising: n paths of parallel switches;

the TDI ends of the N chips are connected to the TDI end of the first JTAG interface through the N-path parallel switch;

the TDI end of the first JTAG interface is connected to the first end of the N-path parallel switch, and the TDI ends of the N chips are connected to the N second ends of the N-path parallel switch.

6. The JTAG-based chip connection structure of any one of claims 1 to 3, further comprising: a first driver, a second driver and a third driver;

the TMS ends of the N chips are connected to the TMS end of the first JTAG interface through the first driver;

the TDI ends of the N chips are connected to the TDI end of the first JTAG interface through the second driver;

the TCK ends of the N chips are connected to the TCK end of the first JTAG interface through the third driver.

7. The JTAG-based chip connection structure of any one of claims 4 to 5, wherein the signal selector and/or the N-way parallel switch are controlled by an external device or manually.