CN202855255U - Switch matrix control circuit with three-wire serial connection peripheral interface - Google Patents
Switch matrix control circuit with three-wire serial connection peripheral interface Download PDFInfo
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- CN202855255U CN202855255U CN 201220496407 CN201220496407U CN202855255U CN 202855255 U CN202855255 U CN 202855255U CN 201220496407 CN201220496407 CN 201220496407 CN 201220496407 U CN201220496407 U CN 201220496407U CN 202855255 U CN202855255 U CN 202855255U
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Abstract
The utility model provides a switch matrix control circuit with a three-wire serial connection peripheral interface. The switch matrix control circuit comprises an upper control circuit, a shift register group and a PIN driver, wherein the shift register group comprises at least one shift resister. According to the switch matrix control circuit, the connection of each shift resister in the shift resister group with the upper control circuit only needs three control wires which are a data wire, a set wire and a clock wire, the number of the control wires is greatly reduced, and output port resource of the upper control circuit is reduced. At the same time, according to the switch matrix control circuit, a parallel data output end of each shift resister is connected with an input end of the PIN driver, which means that each shift resister directly outputs a control signal to the PIN driver, the adding of a control circuit such as a single chip microcomputer, an FPGA or the like is not needed, the design and test difficulties of the product are reduced, and for the product, the guarantee of the reliability of a device is facilitated.
Description
Technical field
The application relates to microwave matrix switch bus design technical field, in particular, relates to a kind of switch matrix control circuit of three line Serial Peripheral Interface (SPI)s.
Background technology
Switch matrix is that the radiofrequency signal with multichannel input equipment input makes up and distributes, and available radiofrequency signal is carried out the equipment that multichannel is exported at one time.Switch matrix commonly used is by PIN(positive-intrinsic negative, the low-doped intrinsic semiconductor layer of adding skim between P and N semiconductor material) driver carries out current drives, and the PIN driver is by TTL(Transistor Transistor Logic, the transistor-transistor logic level) controls, therefore, the way of the PIN driver of switch matrix circuit needs has determined the way of TTL.For different switch matrix circuits, wherein need the PIN driver of different ways.
At present, have two kinds of switch matrix control modes relatively commonly used, comprising: parallel control mode and Asynchronous Serial Interface RS(Recommended Standard, proposed standard) 232 control mode.To be controlled to be example two kinds of switch matrix control modes are described.
The specific works principle of wherein parallel control mode is, the upper control circuit provides 72 TTL control lines, is connected respectively to 72 road PIN drivers of 12 * 6G switch matrix circuit, realizes directly the control to 12 * 6G switch matrix circuit.But the control line that this parallel control mode needs is too many, and the upper control circuits assembly that is not easy to adopt the parallel control mode is in the higher circuit of dimensional requirement, and the upper control circuit can not provide a large amount of control lines.
The control mode specific works principle of Asynchronous Serial Interface RS232 is that switch matrix circuit is connected with the upper control circuit by Asynchronous Serial Interface RS232.Wherein, the upper control circuit only is connected the reception line, sends line and three control lines of ground wire with Asynchronous Serial Interface RS232, has greatly reduced the quantity of control line.But switch matrix circuit need to be resolved the RS232 serial port communicating protocol, and needed 72 the TTL control signals of output are connected to the PIN driver with 72 control signals again after the successfully resolved, realize the control to switch matrix.Therefore, switch matrix circuit need to increase single-chip microcomputer or FPGA(Field-Programmable Gate Array, field programmable gate array) etc. control circuit is resolved the RS232 serial port communicating protocol, and need to increase the Software for Design part, design and test for the high product of reliability requirement, all correspondingly increased very large technical difficulty.
The utility model content
For the problems referred to above, the application provides a kind of switch matrix control circuit of three line Serial Peripheral Interface (SPI)s, too many with the control line that solution available technology adopting parallel control mode needs, be not easy to be assemblied in the higher circuit of dimensional requirement, the upper control circuit can not provide the problem of a large amount of control lines simultaneously, and the control mode that adopts Asynchronous Serial Interface RS232 need to increase the control circuits such as single-chip microcomputer or FPGA the RS232 serial port communicating protocol is resolved, and need to increase the Software for Design part, design and test for the high product of reliability requirement, all the corresponding problem that has increased very large technical difficulty.Technical scheme is as follows:
The application provides a kind of switch matrix control circuit of three line Serial Peripheral Interface (SPI)s, comprising: upper control circuit and add the PIN driver of the low-doped intrinsic semiconductor layer of skim between the P of general-purpose diode and N semiconductor material also comprises:
Input end is connected with the transmit port of described upper control circuit, the shift register group that output terminal is connected with the input end of described PIN driver; Wherein, the transmit port of described upper control circuit comprises serial data signal transmit port, clock signal transmit port and asserts signal transmit port; Described shift register group comprises at least one shift register;
The input end of described shift register group comprises the serial data input end of each shift register, the shift register clock pulse input end of each shift register and the storage register clock pulse input terminal of each shift register; The output terminal of described shift register group comprises the serial data output terminal of each shift register and the parallel data output terminal of each shift register;
Wherein, the shift register clock pulse input end of described each shift register is connected with described clock signal transmit port by clock line;
The storage register clock pulse input terminal of described each shift register is connected with the asserts signal transmit port by the set line;
The serial data input end of first shift register in the described shift register group is connected with described serial data signal transmit port by data line; The serial data input end of other shift registers in the described shift register group connects the serial data output terminal of a upper shift register that is adjacent;
The parallel data output terminal of described each shift register is connected with the input end of described PIN driver.
Preferably, described shift register comprises that model is the shift register of 54HC595.
Preferably, described PIN driver comprises that model is the driver of JLQ-22.
Preferably, described PIN driver comprises 4 road input ends and 4 road output terminals, wherein,
4 road input ends of described PIN driver are connected with 4 channel parallel data output terminals of shift register respectively.
Preferably, also comprise:
The first transtation mission circuit that is connected with the serial data signal transmit port of described upper control circuit;
The second transtation mission circuit that is connected with the clock signal transmit port of described upper control circuit;
The 3rd transtation mission circuit that is connected with the asserts signal transmit port of described upper control circuit;
The first receiving circuit that is connected with the output terminal of described the first transtation mission circuit;
The second receiving circuit that is connected with the output terminal of described the second transtation mission circuit;
The 3rd receiving circuit that is connected with the output terminal of described the 3rd transtation mission circuit; Wherein,
The output terminal of described the first receiving circuit connects the serial data input end of first shift register in the described shift register group;
The output terminal of described the second receiving circuit connects the shift register clock pulse input end of each shift register in the described shift register group;
The output terminal of described the 3rd receiving circuit connects the storage register clock pulse input terminal of each shift register in the described shift register group;
Described the first transtation mission circuit, described the second transtation mission circuit and described the 3rd transtation mission circuit are three transtation mission circuits that structure is identical;
Described the first receiving circuit, described the second receiving circuit and described the 3rd receiving circuit are three receiving circuits that structure is identical.
Use technique scheme, each shift register in the switch matrix control circuit of the three line Serial Peripheral Interface (SPI)s that the application provides in the shift register group with only need data line, set line and three control lines of clock line being connected of upper control circuit, greatly reduce the quantity of control line, saved upper control circuit delivery outlet resource.Simultaneously, the parallel data output terminal of each shift register among the application is connected with the input end of PIN driver, be that each shift register directly outputs control signals to the PIN driver, do not need to increase the control circuits such as single-chip microcomputer or FPGA, do not need to increase the Software for Design part, reduced design and the difficulty of test of product, for product, device reliability is convenient to guarantee.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiment of the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 1 provides for the application;
The structural representation of shift register in the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 2 provides for the application;
The another kind of structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 3 provides for the application;
The structural representation of PIN driver in the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 4 provides for the application;
Another structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 5 provides for the application;
Another structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 6 provides for the application;
The signal of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 7 provides for the application sends synoptic diagram;
The structural representation of the transtation mission circuit of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 8 provides for the application;
The structural representation of the receiving circuit of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that Fig. 9 provides for the application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the application's protection.
Among the application, the quantity of shift register can arrange according to the way of the PIN driver of switch matrix circuit needs in the shift register group.In the introduction of following examples, based on the application's main thought, the switch matrix circuit of the different PIN driver of needs way is described in detail.
An embodiment
See also Fig. 1, the structural representation that it shows the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides comprises: upper control circuit 100, shift register group 200 and PIN driver 300.
Wherein, the input end of shift register group 200 is connected with the transmit port of upper control circuit 100, and output terminal is connected with the input end of PIN driver 300.
Shift register group 200 comprises at least one shift register 201.In the present embodiment, shift register 201 can be the shift register of 54HC595 for model.
Particularly, see also Fig. 2, it shows the structural representation of shift register in the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides.Wherein, shift register 201 comprises 16 pins, and pin 1 to 7 is Q1 to Q7, and pin 15 is Q0, and Q0 to Q7 is 8 bit parallel data output ends of shift register 201; Pin 8 is that GND is the port that connects ground wire; Pin 9 is that Q ' 7 is the serial data output terminal, can be connected with the pin 14 of adjacent next shift register 201, realizes and the cascade of next shift register 201.
Need to prove that the serial data that the cascade between the shift register 201 is about to input expands to not only the conversion of 8 parallel data output.A shift register 201 comprises 8 bit parallel data output ends, and the cascade of a plurality of shift registers 201 has namely comprised a plurality of 8 bit parallel data output ends, has realized that namely serial data expands to the conversion of more 8 bit parallel data outputs.
Need to prove that serial data is to enter at first by low level, the high-order principle that enters is at last inputted, and adopts number namely when the clock pulse signal of input is in rising edge, and a data of current serial data is preserved.
The transmit port of upper control circuit 100 comprises serial data signal transmit port 101, clock signal transmit port 102 and asserts signal transmit port 103.
Need to prove, in the present embodiment, the number of shift register 201 is determined by the way of the PIN driver that needs in the switch matrix circuit in the shift register group 200, switch matrix circuit for one or two PIN driver of needs, a shift register group 201 in the shift register group 200 can satisfy PIN driver in this switch matrix circuit of connection, see also Fig. 3, it shows the another kind of structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides, include only a shift register 201 in the shift register group 200, wherein
The pin 11 of shift register 201 is that SCK shift register clock pulse input end is connected with the clock signal transmit port 102 of upper control circuit 100 by clock line.
The pin 12 of shift register 201 is that RCK storage register clock pulse input terminal is connected with the asserts signal transmit port 103 of upper control circuit 100 by the set line.
The pin 14 of shift register 201 is that SER serial data input end is connected with the serial data signal transmit port 101 of upper control circuit 100 by data line.
The pin 1 to 7 of shift register 201 is Q1 to Q7, and pin 15 is Q0, and 8 bit parallel data output ends are connected with the input end of PIN driver 300.
Especially, in the present embodiment, it is the driver of JLQ-22 that PIN driver 300 can be selected model, and it comprises 4 road input ends and 4 road output terminals.See also Fig. 4, it shows the structural representation of PIN driver in the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides.Wherein, PIN driver 300 comprises 14 pins, and pin 1,4,6 and 7 is that OUT1 to OUT4 is 4 road output terminals of PIN driver 300; Pin 2,8 is that NC is the port that need not connect with being connected; Pin 3 is that VCC is the port that connects outer power voltage; Pin 5 is that VEE is the port that connects outside negative voltage.
In the present embodiment, order is chosen 4 road input end IN1 to IN4 that 4 channel parallel data output terminal Q0 to Q3 in the shift register 201 are connected respectively PIN driver 300 successively.Therefore, a shift register 201 can be exported 8 channel parallel datas, namely can connect two PIN drivers 300.Only needing in the switch matrix circuit of one or two PIN driver 300 of connection, including only a shift register 201 in the shift register group 200 can meet the demands.
Certainly, connect in the switch matrix circuit of a plurality of PIN drivers 300 at needs, corresponding shift register group 200 comprises a plurality of shift registers 201, please in conjunction with Fig. 5 and Fig. 6, wherein Fig. 5 shows another structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides, and it has mainly described the annexation of each shift register 201 in the shift register group 200.Fig. 6 shows another structural representation of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides, and it has mainly described the annexation of shift register 201 and PIN driver 300 in the shift register group 200.Particularly,
The pin 11 of each shift register 201 is that SCK shift register clock pulse input end is connected with the clock signal transmit port 102 of upper control circuit 100 by clock line in the shift register group 200.
The pin 12 of each shift register 201 is that RCK storage register clock pulse input terminal is connected with the asserts signal transmit port 103 of upper control circuit 100 by the set line in the shift register group 200.
The pin 14 of first shift register 201 is that SER serial data input end is connected with the serial data signal transmit port 101 of upper control circuit by data line in the shift register group 200.
The pin 14 of other shift registers 201 is that the pin 9 that SER serial data input end connects the upper shift register 201 be adjacent is Q ' 7 serial data output terminals in the shift register group 200.
The pin 15 of each shift register 201 is that Q0, pin 1 to 7 are Q1 to Q7 in the shift register group 200, in the 8 bit parallel data output ends, Q0 to Q3 is the corresponding input end IN1 to IN4 that connects a PIN driver 300 of order successively, and Q4 to Q7 is the corresponding input end IN1 to IN4 that connects a PIN driver 300 of order successively.
In the present embodiment, the transmit port of upper control circuit 100 comprises serial data signal transmit port 101, clock signal transmit port 102 and asserts signal transmit port 103.Wherein,
The serial data signal transmit port 101 of upper control circuit 100 is connected with first shift register 201 realizations in the shift register group 200 by data line, and serial data signal is transferred to shift register group 200.Especially, the serial data signal low level enters at first, and a high position enters at last.
The clock signal transmit port 102 of upper control circuit 100 is realized being connected with the shift register clock pulse input end of each shift register 201 in the shift register group 200 by clock line, and clock pulse signal is transferred to shift register group 200.Especially, the clock pulse signal frequency is 1MHz, and when clock pulse signal was in rising edge, the serial data of the 201 pairs of inputs of shift register in the shift register group 200 was adopted number, and the data that collect are kept in the shift register 201.When the time clock signal is in rising edge again, the serial data of input is adopted again number, simultaneously the data that collect also are kept in the shift register 201.Wherein, when clock pulse signal is in rising edge, namely the serial data of input is once adopted number, simultaneously the data that gather are kept in the shift register 201.
In the present embodiment, shift register 201 has 8 bit parallel data-out ports, and each shift register 201 is each to gather the data of preserving a parallel data output port in can corresponding displaced register 201.Particularly, first parallel data output port that gathers for the first time the data corresponding displaced register 201 of preserving is pin Q0, second parallel data output port that the data that for the second time collection is preserved can be displaced to the data that for the first time collection is preserved corresponding displaced register 201 is pin Q1, first parallel data output port that gathers for the second time simultaneously the data corresponding displaced register 201 of preserving is pin Q0, the 3rd the parallel data output port that the data that for the third time collection is preserved can be displaced to the data that gather for the first time preservation corresponding displaced register 201 is pin Q2, second the parallel data output port that the data that gather for the second time preservation is displaced to corresponding displaced register 201 is pin Q1, and first parallel data output port that gathers for the third time simultaneously the data corresponding displaced register 201 of preserving is pin Q0.With this form, a secondary data is preserved in every collection, once is shifted gathering before the data of preserving.
A shift register 201 comprises 8 bit parallel data output ends, and therefore a shift register 201 can only gather at most and preserve 8 secondary data.When having gathered, a shift register 201 preserved 8 secondary data, and need shift register 201 to gather again save data, this moment, a shift register 201 can not satisfy the demands, so need a plurality of shift registers 201 to carry out cascade, to realize the to gather purpose of preserving long numeric data.
The pin 14 of other shift registers 201 is that the pin 9 that SER serial data input end connects the upper shift register 201 be adjacent is Q ' 7 serial data output terminals in the shift register group 200.Particularly, first shift register 201 gathers has preserved 8 secondary data, gather save data again after, first shift register 201 is gathered the data of preserving for the first time is displaced to next shift register 201 relayings and continues insurance and deposit.Then, the shifting principle of a same shift register 201 is the same, and first shift register 201 gathers again preserves a secondary data, once is shifted at next shift register 201 gathering before the data of preserving.For the concrete displacement implementation procedure in next shift register 201, the shifting principle of a same shift register 201 is the same, repeats no more here.
The asserts signal transmit port 103 of upper control circuit 100 is realized being connected with the storage register clock pulse input terminal of each shift register 201 in the shift register group 200 by the set line, and the set pulse signal is transferred to shift register group 200.After shift register 201 in the shift register group 200 receives the set pulse signal of upper control circuit 100 transmissions, when the set pulse signal is in rising edge, the data of preserving will be gathered in each shift register 201 in the shift register group 200, the parallel data output terminal of corresponding each shift register 201 latchs, exports, and will gather before the data of preserving simultaneously and empty.
Need to prove, in the present embodiment, see also Fig. 7, its signal that shows the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides sends synoptic diagram.In each clock pulse signal and the serial data one is corresponding, and the set pulse signal is delayed last clock pulse signal in one-period internal clock pulse signal.After clock pulse signal all was sent, the set pulse signal was sent to shift register 201, will gather the data of preserving in the shift register 201, and the parallel data output terminal of corresponding each shift register 201 latchs, exports.
Use technique scheme, each shift register 201 in the switch matrix control circuit of the three line Serial Peripheral Interface (SPI)s that the application provides in the shift register group 200 with only need data line, set line and three control lines of clock line being connected of upper control circuit 100, greatly reduce the quantity of control line, saved upper control circuit 100 delivery outlet resources.Simultaneously, the parallel data output terminal of each shift register 201 among the application is connected with the input end of PIN driver 300, be that each shift register directly outputs control signals to PIN driver 300, do not need to increase the control circuits such as single-chip microcomputer or FPGA, do not need to increase the Software for Design part, reduced design and the difficulty of test of product, for product, device reliability is convenient to guarantee.
Another embodiment
In the present embodiment, to control 12 * 6G switch matrix circuit as example.In 12 * 6G switch matrix circuit, altogether need 12 * 6=72 road PIN driving circuit to carry out current drives.PIN driver 300 is the driver of JLQ-22 for model, and it comprises 4 road input ends, and therefore, 12 * 6G switch matrix circuit needs altogether to connect 72/4=18 sheet PIN driver 300.
Particularly, please in conjunction with Fig. 5 and Fig. 6, comprising: shift register group 200 and PIN driver 300.Wherein, comprise 9 shift registers 201 in the shift register group 200.
The pin 11 of each shift register 201 is that SCK shift register clock pulse input end is connected with the clock signal transmit port 102 of upper control circuit 100 by clock line in the shift register group 200.
The pin 12 of each shift register 201 is that RCK storage register clock pulse input terminal is connected with the asserts signal transmit port 103 of upper control circuit 100 by the set line in the shift register group 200.
The pin 14 of first shift register 201 is that SER serial data input end is connected with the serial data signal transmit port 101 of upper control circuit 100 by data line in the shift register group 200.
The pin 14 of second shift register 201 is that SER serial data input end is that Q ' 7 serial data output terminals are connected with the pin 9 of first shift register 201 in the shift register group 200.
The pin 14 of the 3rd shift register 201 is that SER serial data input end is that Q ' 7 serial data output terminals are connected with the pin 9 of second shift register 201 in the shift register group 200.With this type of attachment, except first shift register 201, the pin 14 of other 8 shift registers 201 is that the pin 9 that SER serial data input end connects the upper shift register 201 be adjacent is Q ' 7 serial data output terminals in the shift register group 200.
The pin 15 of each shift register 201 and pin 1 to 3 parallel data output terminal in the shift register group 200, the corresponding pin 9,10,12 and 13 that connects a PIN driver 300 of order is 4 road input ends of IN1 to IN4 successively; Pin 4 to the 7 parallel data output terminals of each shift register 201 in the shift register group 200, the corresponding pin 9,10,12 and 13 that connects a PIN driver 300 of order is 4 road input ends of IN1 to IN4 successively.
In the present embodiment, the serial data signal transmit port 101 of upper control circuit 100 is realized being connected by first shift register 201 in data line and the shift register group 200, and the serial data signal of upper control circuit 100 transmissions is transferred in the shift register group 200 in first shift register 201.
Each shift register 201 in the shift register group 200 is realized being connected with the clock signal transmit port 102 of upper control circuit 100 by clock line, receives the clock pulse signal that upper control circuit 100 sends constantly.Wherein, the clock pulse signal frequency is 1MHz, and when clock pulse signal was in rising edge, the serial data of the 201 pairs of inputs of shift register in the shift register group 200 was adopted number, and the data that collect are saved in the shift register 201.For data shifting principle in each shift register 201 in shift register group 200 of gather preserving, and with the corresponding relation of the parallel data output terminal of each shift register 201, describe in detail in the above-described embodiments, repeat no more here.
In the present embodiment, need altogether the output of 72 channel parallel datas, so the parallel data output terminal of 9 shift registers 201 all has been assigned with data.
Each shift register 201 in the shift register group 200 is realized being connected with the asserts signal transmit port 103 of upper control circuit 100 by the set line, receives the set pulse signal that upper control circuit 100 sends constantly.After each shift register 201 in the shift register group 200 receives the set pulse signal, when the set pulse signal is in rising edge, the data of preserving will be gathered in each shift register 201 in the shift register group 200, the parallel data output terminal of corresponding each shift register 201 latchs, exports, and will gather before the data of preserving simultaneously and empty.
At this moment, each shift register 201 in the shift register group 200 is sent to the PIN driver 300 that is connected by the parallel data output terminal with parallel data signal, has realized 72 road PIN driving circuits are carried out current drives.
Another embodiment
In the above-described embodiments, upper control circuit 100 comprises three transmit ports, realizes and being connected of shift register group 200 by three control lines, and serial data signal, clock pulse signal and set pulse signal are sent to shift register group 200.In the present embodiment, the application is provided with three transtation mission circuits and three receiving circuits that structure is identical that structure is identical between upper control circuit 100 and shift register group 200, namely three control lines between upper control circuit 100 and shift register group 200 are provided with three transtation mission circuits and three receiving circuits that structure is identical that structure is identical, do not need to send different different transtation mission circuit and the receiving circuits of Design of Signal, simplicity of design according to upper control circuit 100.Wherein transtation mission circuit and receiving circuit are corresponding one by one, and the input end of each transtation mission circuit connects a transmit port of upper control circuit 100, and the output terminal of each receiving circuit connects an input end of shift register group 200.
In the present embodiment, because may there be swinging of signal in serial data signal, clock pulse signal and set pulse signal that upper control circuit 100 sends, pulse voltage is crossed low or too high situation, so that shift register group 200 is when receiving serial data signal that upper control circuit 100 send, clock pulse signal and set pulse signal, cause shift register 201 job insecurities, thereby reduce the serviceable life of shift register 201, even may burn out shift register 201.Therefore increase transtation mission circuit in the present embodiment and receiving circuit is processed signal, to avoid burning out shift register 201.
Please in conjunction with Fig. 8 and Fig. 9, Fig. 8 shows the structural representation of transmitting terminal circuit of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides, and Fig. 9 shows the structural representation of receiving circuit of the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application provides.On the basis of above-described embodiment, also comprise: the first transtation mission circuit, the second transtation mission circuit, the 3rd transtation mission circuit, the first receiving circuit, the second receiving circuit and the 3rd receiving circuit.Wherein,
The first transtation mission circuit is connected with the serial data signal transmit port 101 of upper control circuit 100, the second transtation mission circuit is connected with the clock signal transmit port 102 of upper control circuit 100, and the 3rd transtation mission circuit is connected with the asserts signal transmit port 103 of upper control circuit 100.
The first receiving circuit is connected with the output terminal of the first transtation mission circuit, and the second receiving circuit is connected with the output terminal of the second transtation mission circuit, and the 3rd receiving circuit is connected with the output terminal of the 3rd transtation mission circuit.
The output terminal of the first receiving circuit connects the serial data input end of first shift register 201 in the shift register group 200, the output terminal of the second receiving circuit connects the shift register clock pulse input end of each shift register 201 in the shift register group 200, and the output terminal of the 3rd receiving circuit connects the storage register clock pulse input terminal of each shift register 201 in the shift register group 200.
Simultaneously, the first transtation mission circuit, the second transtation mission circuit and the 3rd transtation mission circuit are three transtation mission circuits that structure is identical, and the first receiving circuit, the second receiving circuit and the 3rd receiving circuit are three receiving circuits that structure is identical.
In the present embodiment, upper control circuit 100 sends to transtation mission circuit with signal, transfer to receiving circuit through transtation mission circuit, by receiving circuit signal is sent to shift register group 200 at last, wherein, the specific works principle of transtation mission circuit and receiving circuit is identical with available circuit, and present embodiment is no longer set forth.
Use technique scheme; the application is provided with three transtation mission circuits and three receiving circuits that structure is identical that structure is identical between upper control circuit 100 and shift register group 200; the signal that serial data signal, clock pulse signal and the set pulse signal that sends in the upper control circuit 100 is converted into first another kind of type is processed; and then send being converted to shift register 201 receivable signals; overcome the interference that pulse voltage is crossed low or too high signal in the signal, protected shift register 201.
Need to prove that each embodiment in this instructions all adopts the mode of going forward one by one to describe, what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
At last, also need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.Do not having in the situation of more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
More than the switch matrix control circuit of a kind of three line Serial Peripheral Interface (SPI)s that the application is provided be described in detail, used specific case herein the application's principle and embodiment are set forth, the explanation of above embodiment just is used for helping to understand the application's method and core concept thereof; Simultaneously, for one of ordinary skill in the art, the thought according to the application all will change in specific embodiments and applications, and in sum, this description should not be construed as the restriction to the application.
Claims (5)
1. the switch matrix control circuit of a line Serial Peripheral Interface (SPI) comprises: upper control circuit and between the P of general-purpose diode and N semiconductor material, add the PIN driver of the low-doped intrinsic semiconductor layer of skim, it is characterized in that, and also comprise:
Input end is connected with the transmit port of described upper control circuit, the shift register group that output terminal is connected with the input end of described PIN driver; Wherein, the transmit port of described upper control circuit comprises serial data signal transmit port, clock signal transmit port and asserts signal transmit port; Described shift register group comprises at least one shift register;
The input end of described shift register group comprises the serial data input end of each shift register, the shift register clock pulse input end of each shift register and the storage register clock pulse input terminal of each shift register; The output terminal of described shift register group comprises the serial data output terminal of each shift register and the parallel data output terminal of each shift register;
Wherein, the shift register clock pulse input end of described each shift register is connected with described clock signal transmit port by clock line;
The storage register clock pulse input terminal of described each shift register is connected with the asserts signal transmit port by the set line;
The serial data input end of first shift register in the described shift register group is connected with described serial data signal transmit port by data line; The serial data input end of other shift registers in the described shift register group connects the serial data output terminal of a upper shift register that is adjacent;
The parallel data output terminal of described each shift register is connected with the input end of described PIN driver.
2. switch matrix control circuit according to claim 1 is characterized in that, described shift register comprises that model is the shift register of 54HC595.
3. switch matrix control circuit according to claim 1 is characterized in that, described PIN driver comprises that model is the driver of JLQ-22.
4. switch matrix control circuit according to claim 3 is characterized in that, described PIN driver comprises 4 road input ends and 4 road output terminals, wherein,
4 road input ends of described PIN driver are connected with 4 channel parallel data output terminals of shift register respectively.
5. switch matrix control circuit according to claim 1 is characterized in that, also comprises:
The first transtation mission circuit that is connected with the serial data signal transmit port of described upper control circuit;
The second transtation mission circuit that is connected with the clock signal transmit port of described upper control circuit;
The 3rd transtation mission circuit that is connected with the asserts signal transmit port of described upper control circuit;
The first receiving circuit that is connected with the output terminal of described the first transtation mission circuit;
The second receiving circuit that is connected with the output terminal of described the second transtation mission circuit;
The 3rd receiving circuit that is connected with the output terminal of described the 3rd transtation mission circuit; Wherein,
The output terminal of described the first receiving circuit connects the serial data input end of first shift register in the described shift register group;
The output terminal of described the second receiving circuit connects the shift register clock pulse input end of each shift register in the described shift register group;
The output terminal of described the 3rd receiving circuit connects the storage register clock pulse input terminal of each shift register in the described shift register group;
Described the first transtation mission circuit, described the second transtation mission circuit and described the 3rd transtation mission circuit are three transtation mission circuits that structure is identical;
Described the first receiving circuit, described the second receiving circuit and described the 3rd receiving circuit are three receiving circuits that structure is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220496407 CN202855255U (en) | 2012-09-26 | 2012-09-26 | Switch matrix control circuit with three-wire serial connection peripheral interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220496407 CN202855255U (en) | 2012-09-26 | 2012-09-26 | Switch matrix control circuit with three-wire serial connection peripheral interface |
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| CN202855255U true CN202855255U (en) | 2013-04-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220496407 Expired - Lifetime CN202855255U (en) | 2012-09-26 | 2012-09-26 | Switch matrix control circuit with three-wire serial connection peripheral interface |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103729326A (en) * | 2013-12-06 | 2014-04-16 | 南京智达康无线通信科技股份有限公司 | GPIO expansion method based on shifting registers |
| CN105510800A (en) * | 2015-12-01 | 2016-04-20 | 华大半导体有限公司 | Electronic label testing device and implementation method capable of simplifying PAD design |
| CN108646299A (en) * | 2018-03-30 | 2018-10-12 | 中国空间技术研究院 | A kind of satellite fabric interface load end Test Diode circuit |
| CN109062851A (en) * | 2018-08-22 | 2018-12-21 | 同源微（北京）半导体技术有限公司 | Control the Transmission system and method, subsystem, computer equipment and computer readable storage medium of data |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
-
2012
- 2012-09-26 CN CN 201220496407 patent/CN202855255U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103729326A (en) * | 2013-12-06 | 2014-04-16 | 南京智达康无线通信科技股份有限公司 | GPIO expansion method based on shifting registers |
| CN105510800A (en) * | 2015-12-01 | 2016-04-20 | 华大半导体有限公司 | Electronic label testing device and implementation method capable of simplifying PAD design |
| CN108646299A (en) * | 2018-03-30 | 2018-10-12 | 中国空间技术研究院 | A kind of satellite fabric interface load end Test Diode circuit |
| CN109062851A (en) * | 2018-08-22 | 2018-12-21 | 同源微（北京）半导体技术有限公司 | Control the Transmission system and method, subsystem, computer equipment and computer readable storage medium of data |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
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