CN214174787U - Display device - Google Patents

Abstract

Provided is a display device which can be visually recognized from one surface of a display panel with respect to an image displayed by a light source and a background on the other surface side opposite to the image, and which can reduce light leakage from a switching element. The display device includes a liquid crystal layer sealed between an array substrate and a counter substrate, and a light source arranged to allow light to enter a side surface of the array substrate or a side surface of the counter substrate. In the array substrate, a source electrode of the switching element connected to the scanning line and the signal line has a first straight portion extending in the second direction, a second straight portion arranged at intervals in the first direction and extending in the second direction, a connecting portion connecting one end of the first straight portion to one end of the second straight portion, and a bypass portion connecting the other end of the first straight portion to the signal line.

Description

Display device

Technical Field

The present disclosure relates to a display device.

Background

Patent document 1 describes a display device including: a first light-transmitting substrate; a second light-transmissive substrate disposed opposite to the first light-transmissive substrate; a liquid crystal layer having a polymer dispersed liquid crystal enclosed between the first light transmissive substrate and the second light transmissive substrate; and at least one light-emitting portion disposed to face at least one side surface of the first light-transmissive substrate and the second light-transmissive substrate.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2018-021974

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

In the display device described in patent document 1, the background on the other side opposite to the one side of the display panel can be visually recognized from the one side. Since the light source is disposed to face at least one side surface of the first transparent substrate and the second transparent substrate, it is necessary to reduce light leakage of the switching element due to the light source.

An object of the present invention is to provide a display device in which an image displayed using a light source can be visually recognized from the background on one surface of a display panel and the other surface on the opposite side, and light leakage of a switching element can be reduced.

Means for solving the problems

A display device according to an aspect includes: an array substrate; an opposing substrate; a liquid crystal layer between the array substrate and the opposite substrate; and a light source arranged to allow light to enter a side surface of the array substrate or a side surface of the counter substrate, the array substrate including: a plurality of signal lines arranged at intervals in a first direction; a plurality of scanning lines arranged at intervals in a second direction; and a switching element connected to the scanning line and the signal line, the switching element having: a drain electrode connected to the pixel electrode via the contact hole; a source electrode; and a gate electrode electrically connected to the scan line, the source electrode having: a first linear portion extending in the second direction; second straight line portions arranged at intervals in the first direction and extending in the second direction; a connecting portion connecting one end of the first linear portion and one end of the second linear portion; and a bypass portion connecting the other end of the first straight portion and the signal line.

Preferably, the bypass portion includes a first conductive line connected to the other end of the first straight portion, and the first conductive line extends in a direction inclined with respect to the second direction.

Preferably, an angle formed by the direction in which the first conductive wiring extends and the second direction is an acute angle.

Preferably, the bypass portion includes a first conductive wiring connected to the other end of the first linear portion, and a first side of the first conductive wiring on a side close to the light source extends obliquely with respect to the second direction.

Preferably, the first stepEdgeThe first angle with the second direction is an acute angle.

Preferably, a second angle formed by a second side of the first conductive wiring on a side away from the light source and the second direction is larger than the first angle.

Preferably, the first linear portion is shorter than the second linear portion.

Preferably, the display device includes an organic insulating layer covering at least the switching element, and a metal layer provided so as to overlap the organic insulating layer, wherein a region surrounded by the scanning line and the signal line has a thickness smaller than a thickness of the organic insulating layer overlapping the scanning line and the signal line in a plan view, and a first inclined surface of the organic insulating layer on a side closer to the light source than the switching element is covered with the metal layer.

Preferably, a second inclined surface of the organic insulating layer on a side farther from the light source than the switching element is not covered with the metal layer.

Preferably, the liquid crystal layer is a polymer dispersed liquid crystal, the background of the counter substrate is visually recognized from the array substrate, and the background of the array substrate is visually recognized from the counter substrate.

Drawings

Fig. 1 is a perspective view showing an example of a display device according to the present embodiment.

Fig. 2 is a block diagram showing a display device of embodiment 1.

Fig. 3 is a timing chart for explaining the timing of light emission of the light source in the field sequential method of embodiment 1.

Fig. 4 is an explanatory diagram showing a relationship between an applied voltage to a pixel electrode and a scattering state of a pixel.

Fig. 5 is a cross-sectional view showing an example of a cross section of the display device of fig. 1.

Fig. 6 is a plan view illustrating a plane of the display device of fig. 1.

Fig. 7 is an enlarged cross-sectional view partially enlarging the liquid crystal layer of fig. 5.

Fig. 8 is a cross-sectional view for explaining a non-scattering state in the liquid crystal layer.

Fig. 9 is a cross-sectional view for explaining a scattering state in the liquid crystal layer.

Fig. 10 is a plan view showing a scanning line, a signal line, and a switching element in a pixel.

Fig. 11 is a plan view showing a holding capacitance layer in a pixel.

Fig. 12 is a plan view showing an auxiliary metal layer and an opening region in a pixel.

Fig. 13 is a plan view showing a pixel electrode in a pixel.

Fig. 14 is a plan view showing a light-shielding layer in a pixel.

FIG. 15 is a cross-sectional view of XV-XV' of FIG. 14.

Fig. 16 is a cross-sectional view of XVI-XVI' of fig. 14.

Fig. 17 is a cross-sectional view of XVII-XVII' of fig. 14.

Fig. 18 is a cross-sectional view of the peripheral region.

Fig. 19 is an enlarged plan view showing the switching element according to embodiment 1.

Fig. 20 is an enlarged plan view of a switching element of a comparative example.

Fig. 21 is an enlarged plan view showing a switching element according to embodiment 2.

Fig. 22 is an enlarged plan view showing a switching element according to embodiment 3.

Description of the reference numerals

1 display device

2 display panel

3 light source

4 drive circuit

9 upper control part

10 array substrate

13F first inclined plane

13R second inclined plane

18 sealing part

20 opposed substrate

AA display area

AP opening part

CE common electrode

CH contact hole

CP conductive member

Distance D1

DE drain electrode

DEA contact electrode

Peripheral region of FR

GE gate electrode

GL scanning line

GS light-shielding layer

HC holding capacitor

HP hotspot (hot spot)

IO holding capacitor electrode

ITO (indium tin oxide) holding capacitor electrode

L light source light

LC high-molecular dispersion liquid crystal

LS light-shielding layer

Ld1, Ld2 and Lu light

PE pixel electrode

PX first direction

PY second direction

PZ third direction

SC semiconductor layer

SE source electrode

SEa first straight line part

SEb second straight line part

SEc connection

SL signal line

SLd detour portion

SLd1 first conductive wiring

SLd2 second conductive wiring

SLd3 third conductive wiring

TM, TMt metal layer

Tr switching element

Alpha 1 first angle

Second angle of alpha 2

Detailed Description

Embodiments (embodiments) for implementing the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. The constituent elements described below include substantially the same elements as those that can be easily conceived by those skilled in the art. The following constituent elements may be appropriately combined. It is to be noted that the disclosure is merely an example, and it is needless to say that the scope of the disclosure is included in the concept that a person skilled in the art can easily conceive of modifications for keeping the gist of the disclosure. In addition, although the drawings are intended to schematically show the width, thickness, shape, and the like of each part as compared with the actual form in order to more clearly explain the present disclosure, the present disclosure is not limited to these examples. In the present specification and the drawings, the same elements as those described above are denoted by the same reference numerals as those in the already described drawings, and detailed description thereof is omitted as appropriate.

(embodiment mode 1)

Fig. 1 is a perspective view showing an example of a display device according to the present embodiment. Fig. 2 is a block diagram illustrating the display device of fig. 1. Fig. 3 is a timing chart for explaining the timing of light emission of the light source in the field sequential method.

As shown in fig. 1, the display device 1 has a display panel 2, a light source 3, and a drive circuit 4. Here, one direction of the plane of the display panel 2 is a PX direction, a direction orthogonal to the PX direction is a second direction PY, and a direction orthogonal to the PX-PY plane is a third direction PZ.

The display panel 2 includes an array substrate 10, a counter substrate 20, and a liquid crystal layer 50 (see fig. 5). The counter substrate 20 is opposed to the array substrate 10 in a direction perpendicular to the surface of the array substrate 10 (the PZ direction shown in fig. 1). The liquid crystal layer 50 (see fig. 5) is sealed with a polymer dispersed liquid crystal LC described later by the array substrate 10, the counter substrate 20, and the sealing portion 18.

As shown in fig. 1, the display panel 2 includes a display area AA in which an image can be displayed, and a peripheral area FR outside the display area AA. In the display area AA, a plurality of pixels Pix are arranged in a matrix. In the present disclosure, a row refers to a pixel row having m pixels Pix arranged in one direction. The column refers to a pixel column having n pixels Pix arranged in a direction perpendicular to the direction in which the rows are arranged. The values of m and n are determined according to the display resolution in the vertical direction and the display resolution in the horizontal direction. The plurality of scanning lines GL are wired for each row, and the plurality of signal lines SL are wired for each column.

The light source 3 includes a plurality of light emitting portions 31. As shown in fig. 2, the light source control section 32 is included in the drive circuit 4. The light source control unit 32 may be a circuit different from the circuit of the drive circuit 4. The light emitting unit 31 and the light source control unit 32 are electrically connected by wiring in the array substrate 10.

As shown in fig. 1, the driving circuit 4 is fixed to the surface of the array substrate 10. As shown in fig. 2, the drive circuit 4 includes a signal processing circuit 41, a pixel control circuit 42, a gate drive circuit 43, a source drive circuit 44, and a common potential drive circuit 45. The array substrate 10 has a larger XY plane area than the counter substrate 20, and the drive circuit 4 is provided in a portion of the array substrate 10 exposed from the counter substrate 20.

An input signal (RGB signal or the like) VS is input from an image output unit 91 of the external host control unit 9 to the signal processing circuit 41 via the flexible substrate 92.

The signal processing circuit 41 includes an input signal analyzing section 411, a storage section 412, and a signal adjusting section 413. The input signal analyzing unit 411 generates a second input signal VCS based on a first input signal VS input from the outside.

The second input signal VCS is a signal for determining what gradation value is applied to each pixel Pix of the display panel 2 based on the first input signal VS. In other words, the second input signal VCS is a signal containing gradation information relating to the gradation value of each pixel Pix.

The signal adjustment section 413 generates a third input signal VCSA from the second input signal VCS. The signal adjusting unit 413 transmits the third input signal VCSA to the pixel control circuit 42 and transmits the light source control signal lca to the light source control unit 32. The light source control signal LCSA is a signal containing light amount information of the light emitting section 31 set in accordance with an input gradation value to the pixel Pix, for example. For example, when a dark image is displayed, the light amount of the light emitting section 31 is set to be small. When a bright image is displayed, the light amount of the light emitting section 31 is set large.

The pixel control circuit 42 generates the horizontal drive signal HDS and the vertical drive signal VDS based on the third input signal VCSA. In the present embodiment, since the driving is performed in a field sequential manner, the horizontal driving signal HDS and the vertical driving signal VDS are generated for each color that can be emitted by the light emitting unit 31.

The gate driving circuit 43 sequentially selects the scanning lines GL of the display panel 2 in one vertical scanning period based on the horizontal driving signal HDS. The selection order of the scanning lines GL is arbitrary.

The source drive circuit 44 supplies a gradation signal corresponding to the output gradation value of each pixel Pix to each signal line SL of the display panel 2 in one 1 horizontal scanning period based on the vertical drive signal VDS.

In the present embodiment, the display panel 2 is an active matrix panel. Therefore, there are a signal (source) line SL extending in the second direction PY and a scanning (gate) line GL extending in the first direction PX in a plan view, and a switching element Tr is provided at an intersection of the signal line SL and the scanning line GL.

As the switching element Tr, a thin film transistor can be used. As an example of the thin film transistor, a bottom gate transistor or a top gate transistor may be used. The switching element Tr is exemplified by a single-gate thin film transistor, but may be a double-gate transistor. One of a source electrode and a drain electrode of the switching element Tr is connected to the signal line SL, a gate electrode thereof is connected to the scanning line GL, and the other of the source electrode and the drain electrode thereof is connected to one end of a capacitor of the polymer dispersed liquid crystal LC described later. One end of the capacitor of the polymer dispersed liquid crystal LC is connected to the switching element Tr via the pixel electrode PE, and the other end is connected to the common potential line COML via the common electrode CE. Further, a storage capacitor HC is generated between the pixel electrode PE and a storage capacitor electrode IO electrically connected to the common potential wiring COML. The common potential wiring COML is supplied from the common potential driving circuit 45.

The light emitting section 31 includes an emitter 33R of a first color (for example, red), an emitter 33G of a second color (for example, green), and an emitter 33B of a third color (for example, blue). The light source control unit 32 controls the first color light emitter 33R, the second color light emitter 33G, and the third color light emitter 33B to emit light in a time-division manner based on the light source control signal LCSA. In this way, the light emitter 33R of the first color, the light emitter 33G of the second color, and the light emitter 33B of the third color are driven in a field sequential manner.

As shown in fig. 3, in the first subframe (first predetermined time period) RF, the first color light emitter 33R emits light in the first color light emission period RON, and the pixel Pix selected in one vertical scanning period GateScan is displayed so as to scatter light. In the entire display panel 2, if a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the signal lines SL selected in one vertical scanning period GateScan, only the first color lights up in the light emission period RON of the first color.

Next, in the second sub-frame (second predetermined time) GF, the light emitter 33G of the second color emits light in the light emission period GON of the second color, and the pixel Pix selected in one vertical scanning period GateScan displays light scattering. In the entire display panel 2, when a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the signal lines SL selected in one vertical scanning period GateScan, only the second color lights up in the light emission period GON of the second color.

Further, in the third subframe (third predetermined time) BF, the light emitter 33B of the third color emits light in the light emission period BON of the third color, and the pixel Pix selected in one vertical scanning period GateScan is displayed so as to scatter light. In the entire display panel 2, when a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the signal lines SL selected in one vertical scanning period GateScan, only the third color is turned on in the light emission period BON of the third color.

The human eye has a limited resolving power for time, and an afterimage occurs, so that a composite image of three colors can be recognized during one frame (1F). In the field sequential method, a color filter may not be required, and absorption loss by the color filter is reduced, so that high transmittance can be achieved. In the color filter system, the sub-pixels obtained by dividing the pixel Pix for each of the first color, the second color, and the third color are formed into one pixel, whereas in the field sequential system, such sub-pixel division may not be performed. The display device may further include a fourth sub-frame for emitting a fourth color different from the first color, the second color, and the third color.

Fig. 4 is an explanatory diagram showing a relationship between an applied voltage to a pixel electrode and a scattering state of a pixel. Fig. 5 is a cross-sectional view showing an example of a cross section of the display device of fig. 1. Fig. 6 is a plan view illustrating a plane of the display device of fig. 1. Fig. 5 is a section V-V' of fig. 6. Fig. 7 is an enlarged cross-sectional view partially enlarging the liquid crystal layer of fig. 5. Fig. 8 is a cross-sectional view for explaining a non-scattering state in the liquid crystal layer. Fig. 9 is a cross-sectional view for explaining a scattering state in the liquid crystal layer.

If a gradation signal corresponding to the output gradation value of each pixel Pix is supplied to each of the signal lines SL for the selected pixel Pix in one vertical scanning period GateScan, the voltage applied to the pixel electrode PE changes in accordance with the gradation signal. When the voltage applied to the pixel electrode PE changes, the voltage between the pixel electrode PE and the common electrode CE changes. As shown in fig. 4, the scattering state of the liquid crystal layer 50 in each pixel Pix is controlled by the voltage applied to the pixel electrode PE, and the scattering ratio in the pixel Pix changes.

As shown in fig. 4, when the voltage applied to the pixel electrode PE becomes equal to or higher than the saturation voltage Vsat, the change in the scattering ratio in the pixel Pix becomes small. Therefore, the drive circuit 4 changes the voltage applied to the pixel electrode PE in accordance with the vertical drive signal VDS in the voltage range Vdr lower than the saturation voltage Vsat.

As shown in fig. 5 and 6, the array substrate 10 includes a first main surface 10A, a second main surface 10B, a first side surface 10C, a second side surface 10D, a third side surface 10E, and a fourth side surface 10F. The first main surface 10A and the second main surface 10B are parallel planes. In addition, the first side surface 10C and the second side surface 10D are parallel planes. The third side 10E and the fourth side 10F are parallel planes.

As shown in fig. 5 and 6, the counter substrate 20 includes a first main surface 20A, a second main surface 20B, a first side surface 20C, a second side surface 20D, a third side surface 20E, and a fourth side surface 20F. The first main surface 20A and the second main surface 20B are parallel planes. The first side surface 20C and the second side surface 20D are parallel planes. The third side 20E and the fourth side 20F are parallel planes.

As shown in fig. 5 and 6, the light source 3 faces the second side surface 20D of the counter substrate 20. The light source 3 is also sometimes referred to as a point light source. As shown in fig. 5, the light source 3 irradiates the second side surface 20D of the counter substrate 20 with light source light L. The second side surface 20D of the counter substrate 20 facing the light source 3 serves as a light incident surface.

As shown in fig. 5, the light source light L emitted from the light source 3 propagates in a direction (second direction PY) away from the second side surface 20D while being reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20. When the light source light L is directed outward from the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20, the light source light L travels from a medium having a large refractive index to a medium having a small refractive index, and therefore, if the incident angle at which the light source light L enters the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20 is larger than the critical angle, the light source light L is totally reflected on the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20.

As shown in fig. 5, the light source light L propagating inside the array substrate 10 and the counter substrate 20 is scattered at the pixel Pix where the liquid crystal in the scattering state is present, the incident angle of the scattered light becomes an angle smaller than the critical angle, and the radiated lights 68 and 68A are radiated to the outside from the first main surface 20A of the counter substrate 20 and the first main surface 10A of the array substrate 10, respectively. The radiant lights 68 and 68A radiated to the outside from the first main surface 20A of the counter substrate 20 and the first main surface 10A of the array substrate 10 are observed by the observer. Hereinafter, a polymer dispersed liquid crystal in a scattering state and a polymer dispersed liquid crystal in a non-scattering state will be described with reference to fig. 7 to 9.

As shown in fig. 7, the array substrate 10 is provided with a first alignment film AL 1. The counter substrate 20 is provided with a second alignment film AL 2. The first alignment film AL1 and the second alignment film AL2 are, for example, vertical alignment films.

A solution containing a liquid crystal and a monomer is enclosed between the array substrate 10 and the counter substrate 20. Next, the monomer and the liquid crystal are aligned by the first alignment film AL1 and the second alignment film AL2, and then polymerized by ultraviolet rays or heat to form the bulk (bulk) 51. As a result, the liquid crystal layer 50 including the reverse (reverse mode) polymer dispersed liquid crystal LC in which the liquid crystal is dispersed in the gaps of the polymer mesh formed in the mesh shape is formed.

As described above, the polymer dispersed liquid crystal LC includes the bulk 51 made of a polymer and the plurality of fine particles 52 dispersed in the bulk 51. The microparticles 52 are formed of liquid crystal. The bulk 51 and the fine particles 52 each have optical anisotropy.

The orientation of the liquid crystal contained in the particles 52 is controlled by the voltage difference between the pixel electrode PE and the common electrode CE. The orientation of the liquid crystal changes according to the voltage applied to the pixel electrode PE. The orientation of the liquid crystal changes and thus the degree of scattering of light by the pixel Pix changes.

For example, as shown in fig. 8, in a state where no voltage is applied between the pixel electrode PE and the common electrode CE, the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the fine particles 52 are oriented in the same direction. The optical axes Ax2 of the microparticles 52 are parallel to the PZ direction of the liquid crystal layer 50. The optical axis Ax1 of the bulk 51 is parallel to the PZ direction of the liquid crystal layer 50 regardless of the presence or absence of voltage.

The ordinary refractive indices of the bulk 51 and the microparticle 52 are equal to each other. In a state where no voltage is applied between the pixel electrode PE and the common electrode CE, the refractive index difference between the bulk 51 and the microparticles 52 becomes zero in all directions. The liquid crystal layer 50 is in a non-scattering state in which the source light L is not scattered. The light source light L propagates in a direction away from the light source 3 (light emitting section 31) while being reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20. When the liquid crystal layer 50 is in a non-scattering state in which the light source light L is not scattered, the background on the first main surface 20A side of the counter substrate 20 can be visually recognized from the first main surface 10A of the array substrate 10, and the background on the first main surface 10A side of the array substrate 10 can be visually recognized from the first main surface 20A of the counter substrate 20.

As shown in fig. 9, between the pixel electrode PE and the common electrode CE to which a voltage is applied, the optical axis Ax2 of the microparticles 52 is inclined due to an electric field generated between the pixel electrode PE and the common electrode CE. The optical axis Ax1 of the block 51 is not changed by the electric field, and therefore the orientation of the optical axis Ax1 of the block 51 and the optical axis Ax2 of the microparticle 52 are different from each other. In the pixel Pix having the pixel electrode PE to which the voltage is applied, the light source light L is scattered. Part of the light source light L scattered as described above is emitted to the outside from the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20, and is observed by the observer.

In the pixel Pix having the pixel electrode PE to which no voltage is applied, the background on the first main surface 20A side of the counter substrate 20 is visually recognized from the first main surface 10A of the array substrate 10, and the background on the first main surface 10A side of the array substrate 10 is visually recognized from the first main surface 20A of the counter substrate 20. In the display device 1 according to the present embodiment, when the first input signal VS is input from the image output unit 91, a voltage is applied to the pixel electrode PE of the pixel Pix displaying an image, and the image and the background based on the third input signal VCSA can be visually recognized together. In this way, when the polymer dispersed liquid crystal is in a scattering state, an image is displayed in the display region.

In the pixel Pix having the pixel electrode PE to which a voltage is applied, an image displayed by light emitted to the outside by scattering the light source light L is displayed so as to overlap the background. In other words, the display device 1 of the present embodiment displays an image so that the image is superimposed on the background by the radiant light 68 or the combination of the radiant light 68A and the background.

In one vertical scanning period GateScan shown in fig. 3, the potential of each pixel electrode PE (see fig. 7) to be written needs to be held in at least one of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON after the one vertical scanning period GateScan. If the potential of each pixel electrode PE (see fig. 7) to be written cannot be held in at least one of the light emission period RON of the first color, the light emission period GON of the second color, and the light emission period BON of the third color after one vertical scanning period GateScan, so-called flicker (flicker) or the like is likely to occur. In other words, in order to shorten the selection time of the scanning line, that is, one vertical scanning period GateScan, and to improve the visibility when the driving is performed in a so-called field sequential manner, it is desirable to easily hold the potential of each pixel electrode PE (see fig. 7) to be written in each of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON.

Fig. 10 is a plan view showing a scanning line, a signal line, and a switching element in a pixel. Fig. 11 is a plan view showing a holding capacitance layer in a pixel. Fig. 12 is a plan view showing an auxiliary metal layer and an opening region in a pixel. Fig. 13 is a plan view showing a pixel electrode in a pixel. Fig. 14 is a plan view showing a light-shielding layer in a pixel. FIG. 15 is a cross-sectional view of XV-XV' of FIG. 14. Fig. 16 is a cross-sectional view of XVI-XVI' of fig. 14. Fig. 17 is a cross-sectional view of XVII-XVII' of fig. 14. Fig. 18 is a cross-sectional view of the peripheral region. As shown in fig. 1, 2, and 10, the array substrate 10 is provided with a plurality of signal lines SL and a plurality of scanning lines GL in a lattice shape in a plan view. In other words, the array substrate 10 includes a plurality of signal lines arranged at intervals in the first direction PX and a plurality of scanning lines arranged at intervals in the second direction PY on one surface thereof.

As shown in fig. 10, a region surrounded by the adjacent scanning line GL and the adjacent signal line SL is a pixel Pix. The pixel Pix is provided with a pixel electrode PE and a switching element Tr. In this embodiment, the switching element Tr is a bottom-gate thin film transistor. The switching element Tr has a gate electrode GE electrically connected to the scanning line GL and a semiconductor layer SC overlapping in a plan view.

As shown in fig. 10, the scanning line GL is a wiring of a metal such as molybdenum (Mo) or aluminum (Al), a laminate thereof, or an alloy thereof. The signal line SL is a wiring of metal such as aluminum or an alloy.

As shown in fig. 10, the semiconductor layer SC is provided so as not to protrude from the gate electrode GE in a plan view. This reflects the light source light L from the gate electrode GE toward the semiconductor layer SC, and thus light leakage is less likely to occur in the semiconductor layer SC.

As shown in fig. 5 and 10, the light source light L emitted from the light source 3 enters in the second direction PY as the incident direction. When the incident direction of the light source light L is the second direction PY, the length of the semiconductor layer SC in the first direction is smaller than the length of the semiconductor layer SC in the first direction PX. This reduces the length of the light source light L in the direction intersecting the incident direction, thereby reducing the influence of light leakage.

As shown in fig. 10, the source electrode SE is formed such that 2 conductors similar to the signal line SL extend from the signal line SL in the same layer as the signal line SL and in a direction intersecting the signal line. Thus, the source electrode SE electrically connected to the signal line SL overlaps one end portion of the semiconductor layer SC in a plan view.

As shown in fig. 10, in a plan view, a drain electrode DE is provided between the conductors of the adjacent source electrodes SE. The drain electrode DE overlaps with the semiconductor layer SC in a plan view. The portion not overlapping the source electrode SE and the drain electrode DE functions as a channel of the switching element Tr. As shown in fig. 13, the contact electrode DEA electrically connected to the drain electrode DE is electrically connected to the pixel electrode PE at the contact hole CH.

As shown in fig. 15, the array substrate 10 includes a first light-transmitting base material 19 formed of, for example, glass. The first light-transmitting substrate 19 may be a resin such as polyethylene terephthalate as long as it has light-transmitting properties.

As shown in fig. 15, the scanning line GL (see fig. 10) and the gate electrode GE are provided on the first light-transmissive substrate 19.

As shown in fig. 15, a first insulating layer 11 is provided so as to cover the scanning lines GL and the gate electrodes GE. The first insulating layer 11 is formed of a transparent inorganic insulating material such as silicon nitride.

A semiconductor layer SC is stacked on the first insulating layer 11. The semiconductor layer SC is formed of, for example, amorphous silicon, but may be formed of polycrystalline silicon or an oxide semiconductor. When viewed in the same cross section, the length Lsc of the semiconductor layer SC is smaller than the length Lge of the gate electrode GE superimposed on the semiconductor layer SC. This allows light Ld1 transmitted from gate electrode GE through first light-transmissive substrate 19 to be shielded. As a result, the light leakage of the switching element Tr of embodiment 1 is reduced.

The first insulating layer 11 is provided with a source electrode SE and a signal line SL covering a part of the semiconductor layer SC, and a drain electrode DE covering a part of the semiconductor layer SC. The drain electrode DE is formed of the same material as the signal line SL. A second insulating layer 12 is provided over the semiconductor layer SC, the signal line SL, and the drain electrode DE. The second insulating layer 12 is formed of a transparent inorganic insulating material such as silicon nitride, for example, as in the case of the first insulating layer.

A third insulating layer covering a part of the second insulating layer 12 is formed on the second insulating layer 12. The third insulating layer 13 is formed of an organic insulating material having light-transmitting properties such as an acrylic resin. The third insulating layer 13 has a film thickness larger than that of another insulating film formed of an inorganic material.

As shown in fig. 15, 16, and 17, there are a region with the third insulating layer 13 and a region without the third insulating layer 13. As shown in fig. 16 and 17, the region having the third insulating layer 13 is above the scanning line GL and above the signal line SL. The third insulating layer 13 is formed in a lattice shape covering the upper portions of the scanning lines GL and the signal lines SL along the scanning lines GL and the signal lines SL. In addition, as shown in fig. 15, the region having the third insulating layer 13 is also above the semiconductor layer SC, that is, above the switching element Tr. Therefore, the switching element Tr, the scanning line GL, and the signal line SL are separated from the storage capacitor electrode ITO by a relatively long distance, and are less likely to be affected by the common potential from the storage capacitor electrode ITO. Further, in the array substrate 10, since the region surrounded by the scanning line GL and the signal line SL is formed without the third insulating layer 13, a region having a smaller thickness of the insulating layer than the thickness of the insulating layer overlapping the signal line SL and the scanning line GL in a plan view is formed. In a region surrounded by the scanning line GL and the signal line SL, light transmittance and light transmittance are relatively improved as compared with those above the scanning line GL and above the signal line SL.

As shown in fig. 15, a metal layer TM is provided on the third insulating layer 13. The conductive metal layer TM is a metal such as molybdenum (Mo) or aluminum (Al), a laminate thereof, or an alloy thereof. As shown in fig. 12, the metal layer TM is provided in a region overlapping the signal line SL, the scanning line GL, and the switching element Tr in a plan view. Thereby, the metal layer TM is formed in a lattice shape, and the opening AP surrounded by the metal layer TM is formed.

As shown in fig. 15, a storage capacitor electrode IO is provided on the third insulating layer 13 and on the metal layer TM. The storage capacitor electrode IO is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). The storage capacitor electrode IO is also referred to as a third translucent electrode. As shown in fig. 11, the storage capacitor electrode IO has a region IOX where the translucent conductive material is not present in a region surrounded by the scanning line GL and the signal line SL. The holding capacitance electrode IO is provided across the plurality of pixels Pix across the adjacent pixels Pix. The region of the storage capacitor electrode IO having the translucent conductive material overlaps the scanning line GL or the signal line SL and extends toward the adjacent pixel Pix.

The storage capacitor electrode IO is in a grid shape covering the scanning line GL and the signal line SL along the scanning line GL and the signal line SL. Thus, the storage capacitance HC between the area IOX without the light-transmissive conductive material and the pixel electrode PE is reduced, and therefore the storage capacitance HC is adjusted by the size of the area IOX without the light-transmissive conductive material.

As shown in fig. 12, the switching element Tr connected to the scanning line GL and the signal line SL is provided, at least the switching element Tr is covered with the third insulating layer 13 which is an organic insulating layer, and a metal layer TM having a larger area than the switching element Tr is provided above the third insulating layer 13. This can suppress light leakage from the switching element Tr.

The metal layer TM may be on the storage capacitor electrode IO as long as it overlaps the storage capacitor electrode IO. The resistance of the metal layer TM is smaller than that of the storage capacitor electrode IO. Therefore, it is possible to suppress the potential variation of the storage capacitor electrode IO due to the position of the pixel Pix in the display area AA.

As shown in fig. 12, the width of the metal layer TM overlapping the signal line SL is larger than the width of the signal line SL in a plan view. This suppresses the emission of the reflected light reflected by the edge of the signal line SL from the display panel 2. Here, the width of the metal layer TM and the width of the signal line SL are lengths in a direction intersecting the extending direction of the signal line SL. The width of the metal layer TM overlapping the scanning line GL is larger than the width of the scanning line GL. Here, the width of the metal layer TM and the width of the scanning line GL are lengths in a direction intersecting with an extending direction of the scanning line GL.

As shown in fig. 15, a fourth insulating layer 14 is provided over the retention capacitor electrode IO and the metal layer TM. The fourth insulating layer 14 is an inorganic insulating layer formed of a transparent inorganic insulating material such as silicon nitride.

As shown in fig. 15, a pixel electrode PE is provided on the fourth insulating layer 14. The pixel electrode PE is formed of a light-transmitting conductive material such as ITO. The pixel electrode PE is electrically connected to the contact electrode DEA through a contact hole CH provided in the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12. As shown in fig. 13, the pixel electrode PE is divided for each pixel Pix. A first alignment film AL1 is provided over the pixel electrode PE.

As shown in fig. 15, the counter substrate 20 includes a second light-transmitting base material 29 formed of, for example, glass. The second light-transmitting substrate 29 may be a resin such as polyethylene terephthalate as long as it has light-transmitting properties. The second translucent substrate 29 is provided with a common electrode CE. The common electrode CE is formed of a light-transmissive conductive material such as ITO. A second alignment film AL2 is provided on the surface of the common electrode CE. The counter substrate 20 has a light-shielding layer LS between the second light-transmissive base material 29 and the common electrode CE. The light-shielding layer LS is formed of a black resin or metal material. In addition, a spacer PS is formed between the array substrate 10 and the counter substrate 20, and the spacer PS is interposed between the common electrode CE and the second alignment film AL 2.

As shown in fig. 12 and 16, in the display device of embodiment 1, the light-shielding layer GS on the same layer as the scanning line GL extends along the signal line SL and is provided at a position overlapping a part of the signal line SL. The light-shielding layer GS is formed of the same material as the scanning line GL. The light-shielding layer GS is not provided in a portion where the scanning line GL and the signal line SL intersect in a plan view.

As shown in fig. 12, the light-shielding layer GS and the signal line SL are electrically connected through the contact hole CHG. Thus, the wiring resistance of the light-shielding layer GS and the signal line SL is lower than the wiring resistance of only the signal line SL. As a result, delay of the gradation signal supplied to the signal line SL can be suppressed. Note that the light-shielding layer GS may not be connected to the signal line SL without the contact hole CHG.

As shown in fig. 16, the light-shielding layer GS is provided on the opposite side of the signal line SL from the metal layer TM. The light-shielding layer GS has a width larger than the width of the signal line SL and smaller than the width of the metal layer TM. The width of the light-shielding layer GS, the width of the metal layer TM, and the width of the signal line SL are lengths in a direction intersecting the extending direction of the signal line SL. In this way, the light-shielding layer GS is wider than the signal lines SL, and therefore, emission of reflected light reflected at the edges of the signal lines SL from the display panel 2 is suppressed. As a result, the display device 1 improves the visibility of the image.

As shown in fig. 14 and 15, the counter substrate 20 is provided with a light-shielding layer LS. The light-shielding layer LS is provided in a lattice shape in a region overlapping the signal line SL, the scanning line GL, and the switching element Tr in a plan view.

As shown in fig. 14, 15, 16, and 17, the light-shielding layer LS has a width larger than that of the metal layer TM. This suppresses the emission of the reflected light reflected by the edges of the signal lines SL, the scanning lines GL, and the metal layer TM from the display panel 2. As a result, the display device 1 improves the visibility of the image.

In contact hole CH and contact hole CHG, diffuse reflection is likely to occur when light source light L is irradiated. Therefore, the light-shielding layer LS is provided in a region overlapping the contact hole CH and the contact hole CHG in a plan view.

Further, the light-shielding layer LS is provided on the counter substrate, and the transparency of the display device 1 is more or less lowered, but the contrast and the visibility of the image are improved. However, the light-shielding layer LS may be removed from the counter substrate 20 because high transparency of the display device 1 is important.

As shown in fig. 15, the spacer SP is disposed between the array substrate 10 and the counter substrate 20, and the uniformity of the distance between the array substrate 10 and the counter substrate 20 is improved.

As shown in fig. 18, a common potential wiring COML is routed to the peripheral region FR. The common potential wiring COML has, for example, a first common potential wiring COML1 and a second common potential wiring COML 2. The first common potential wiring COML1 is electrically connected to the common electrode CE of the counter substrate 20 via a conductive member CP. The conductive member CP may be a conductive pillar (pillar), or may be a sealing material containing conductive particles such as Au particles.

As shown in fig. 18, in the peripheral region FR, the storage capacitor electrode IO is electrically connected to the second common potential wiring COML 2. The metal layer TM is disposed in the display area AA.

Fig. 19 is an enlarged plan view showing the switching element according to embodiment 1. Fig. 20 is an enlarged plan view of a switching element of a comparative example. As shown in fig. 19 and 20, the source electrode SE includes a first straight portion SEa, a second straight portion SEb, and a connecting portion SEc. The first straight portion SEa extends in the second direction. The second linear portion SEa is disposed at a position different from the first linear portion SEa in the first direction, and extends in the second direction. One end of the first linear portion SEa and one end of the second linear portion SEb are electrically connected by a connection portion SEc. Thus, the source electrode SE has a U shape. The source electrode SE is also called horseshoe.

As shown in fig. 20, in the switching element Tr of the comparative example, there is no difference in distance in the second direction PY from the other end of the first linear portion SEa to the other end of the second linear portion SEb. When the contact hole CH of the drain electrode DE electrically connected to the pixel electrode PE is arranged at a position aligned in the second direction PY of the semiconductor layer SC, the aperture ratio of the pixel Pix increases. However, as described above, when the incident direction of the light source light L is the second direction PY, the length of the semiconductor layer SC in the first direction PX is smaller than the length of the semiconductor layer SC in the second direction PY. Therefore, the other end of the first linear portion SEa is closer to the contact hole CH of the drain electrode DE. As a result, a hot spot HP that increases the leakage current when the switch is turned off is likely to occur near the other end of the first linear portion SEa to which the signal line SL is connected. Since the gate electrode GE is located below a portion where the signal line SL (source line) and the semiconductor layer SC (amorphous silicon) are orthogonal to each other, the hot spot HP is a region where the electric field strength is strongest, and a leak current at the hot spot HP easily flows to the pixel electrode PE.

In contrast, as shown in fig. 19, in the switching element Tr of embodiment 1, the contact hole CH of the drain electrode DE electrically connected to the pixel electrode PE is arranged at a position aligned in the second direction PY of the semiconductor layer SC. The other end of the first straight portion SEa is connected to the signal line SL via a bypass portion SLd. The detour portion SLd of embodiment 1 extends so as to be separated from the signal line SL in a first direction away from the semiconductor layer SC in a plan view, and then approaches the other end of the first straight portion SEa. As a result, the distance D1 is different in the second direction from the other end of the first linear portion SEa to the other end of the second linear portion SEb, and the second linear portion SEb is longer than the first linear portion SEa. Thus, even if a hot spot HP in which the leakage current increases occurs near the other end of the first straight portion SEa to which the detour portion SLd is connected, the leakage current when the switch is turned off decreases. The switching element Tr of embodiment 1 shown in fig. 19 has a smaller leakage current when the switch is off than the switching element Tr of the comparative example shown in fig. 20.

As described above, the display device 1 includes the array substrate 10, the counter substrate 20, the liquid crystal layer 50, and the light source 3. The array substrate 10 has a plurality of pixel electrodes PE as first translucent electrodes arranged for each pixel Pix. The array substrate 10 is provided with a plurality of signal lines SL arranged at intervals in the first direction PX and a plurality of scanning lines GL arranged at intervals in the second direction PY. The counter substrate 20 includes a common electrode CE as a second light transmissive electrode at a position overlapping the pixel electrode PE in a plan view. The liquid crystal layer 50 includes a polymer dispersed liquid crystal LC sealed between the array substrate 10 and the counter substrate 20. The light emitting portion 31 of the light source 3 emits light in the second direction PY toward the side surface of the counter substrate 20. The incident direction of light propagating through the array substrate 10 and the counter substrate 20 is the second direction. The light emitting unit 31 may emit light propagating through the array substrate 10 and the counter substrate 20 toward the side surface of the array substrate 10.

The switching element has a drain electrode DE connected to the pixel electrode PE via a contact hole CH, a source electrode SE, and a gate electrode GE electrically connected to the scanning line GL. The source electrode SE includes a first linear portion SEa extending in the second direction PY, a second linear portion SEb arranged at an interval in the first direction PX and extending in the second direction PY, and a connecting portion SEc connecting one end of the first linear portion SEa and one end of the second linear portion SEb. The source electrode SE has a bypass portion SLd connecting the other end of the first straight portion SEa to the signal line SL. The first linear portion SEa is made shorter than the second linear portion SEa in order to form a difference in distance D1 in the second direction PY from the other end of the first linear portion SEa to the other end of the second linear portion SEa. Thus, even if a hot spot HP in which the leakage current increases occurs near the other end of the first straight portion SEa to which the detour portion SLd is connected, the leakage current when the switch is turned off decreases.

The array substrate 10 includes: a third insulating layer 13 which is an organic insulating layer covering at least the switching element Tr; and a metal layer TM provided so as to overlap the third insulating layer 13 and having an area larger than that of the switching element Tr. The region surrounded by the scanning line GL and the signal line SL has a thickness smaller than the thickness of the third insulating layer 13 overlapping the scanning line GL and the signal line SL in a plan view. Therefore, a slope is formed in which the thickness of the third insulating layer 13 on the side closer to the light source 3 than the switching element Tr in a plan view changes. As shown in fig. 5 and 20, the light source light L emitted from the light source 3 enters in the second direction PY as the incident direction. As shown in fig. 15, the slopes include a first slope 13F of the third insulating layer 13 on the light Lu incident side and a second slope 13R of the third insulating layer 13 on the opposite side of the light Lu incident side in the light source light L. As shown in fig. 15, the first slope 13F of the third insulating layer 13 on the light Lu incident side is covered with the metal layer TMt. Here, the metal layer TMt is formed of the same material as the metal layer TM, and is a tapered portion formed by extending the metal layer TM.

As shown in fig. 15, the light Lu arrives in the incident direction. The light Lu is a part of the light source light L that reaches from a side closer to the light source 3 than the switching element Tr. Here, since the metal layer TMt blocks the light Lu, light leakage can be reduced.

In the case where the second slope 13R is covered with the metal layer TM and the background of the counter substrate 20 is visually recognized from the array substrate 10, the light Ld2 seen by the observer is reflected by the metal layer TM covering the second slope 13R, and the reflected light may be visually recognized by the observer. In embodiment 1, the metal layer TM covering the second slope 13R is not provided. Therefore, in the display device of embodiment 1, reflected light that hinders visual recognition by the observer can be reduced.

(embodiment mode 2)

Fig. 21 is an enlarged plan view showing a switching element according to embodiment 2. The same components as those described in the above embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

As shown in fig. 21, in the switching element Tr of embodiment 2, the contact holes CH of the drain electrodes DE electrically connected to the pixel electrodes PE are all arranged at positions aligned in the second direction PY of the semiconductor layer SC. The other end of the first straight portion SEa is connected to the signal line SL via a bypass portion SLd.

The detour SLd of embodiment 2 electrically connects the first conductor line SLd1, the second conductor line SLd2, and the third conductor line SLd 3. The third conductive line SLd3 is electrically connected to the signal line SL in a plan view and extends in the first direction away from the semiconductor layer SC. More specifically, the third conductive wiring SLd3 extends in a direction inclined with respect to the first direction PX or the second direction PY so as to be distant from the semiconductor SC. The second conductive wiring SLd2 is electrically connected to the third conductive wiring SLd3 and extends from the third conductive wiring SLd3 in the second direction PY. The first conductive line SLd1 is electrically connected to the second conductive line SLd2, and extends so as to approach from the second conductive line SLd2 to the other end of the first linear portion SEa. More specifically, the first conductive line SLd1 extends in a direction inclined with respect to the 1 st direction PX and the second direction PY so as to approach the other end of the first linear portion SEa. Note that the second conductive line SLd2 may not be present, and the first conductive line SLd1 may be electrically connected to the third conductive line SLd3 and extend from the third conductive line SLd3 to the other end of the first linear portion SEa. In this case, the first conductive line SLd1 and the third conductive line SLd3 have a V-shape in a plan view. The second straight line portion SEa is longer than the first straight line portion SEa by a difference of a distance D1 in the second direction PY from the other end of the first straight line portion SEa to the other end of the second straight line portion SEa. Thus, even if a hot spot HP in which the leakage current increases occurs near the other end of the first straight portion SEa to which the bypass portion SLd is connected, the leakage current when the switch is turned off decreases. The switching element Tr of embodiment 2 shown in fig. 21 has a smaller leakage current when the switch is off than the switching element Tr of the comparative example shown in fig. 20.

The first conductive wiring SLd1 extends to form a first angle α 1 with respect to the second direction PY. The first angle α 1 is, for example, 45 °. The light source light L is not shielded by the metal layer TMt and the metal layer TM shown in fig. 15 but irradiated to the first conductive wiring SLd1, which easily generates reflected light. If the first conductive line SLd1 extends obliquely with respect to the second direction PY, the light source light L is reflected in a direction different from the second direction PY at the edge of the first conductive line SLd1, and is hard to be noticed. If the first angle α 1 is an acute angle, preferably 30 ° or more and 85 ° or less, the reflected light of the light source light L reflected by the bypass portion SLd is less noticeable. If the first angle α 1 is 45 ° or more and 60 ° or less, the reflected light of the light source light L reflected by the detour portion SLd becomes less noticeable. The detour portion SLd is not limited to the above shape, and may have an arc shape.

(embodiment mode 3)

Fig. 22 is an enlarged plan view showing a switching element according to embodiment 3. The same components as those described in the above embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

As shown in fig. 22, the first side of the first conductive wire SLd1 makes a first angle α 1 with the second direction PY, and the second side of the first conductive wire SLd1 makes a second angle α 2 with the second direction PY. The first edge of the first conductive wiring line SLd1 is on the side close to the light source 3. The second side of the first conductive wiring line SLd1 is at a side away from the light source 3. The direction in which the first side of the first conductive wiring line SLd1 extends is extended obliquely with respect to the second direction PY. The light source light L is not shielded by the metal layer TMt and the metal layer TM shown in fig. 15, but is irradiated to the first side of the first conductive line SLd1, and reflected light is easily generated. When the first side of the first conductive line SLd1 and the second direction PY are at the first angle α 1, the light source light L is reflected in a direction different from the second direction PY at the first side of the first conductive line SLd1, and is hard to be noticed. If the first angle α 1 is an acute angle, preferably 30 ° or more and 85 ° or less, the reflected light of the light source light L reflected by the bypass portion SLd is less noticeable. If the first angle α 1 is 45 ° or more and 60 ° or less, the reflected light of the light source light L reflected by the detour portion SLd becomes less noticeable.

The second angle α 2 is larger than the first angle α 1. Accordingly, the width of the first conductive line SLd1 increases as it approaches the first straight line portion SEa, and the line resistance of the detour portion SLd decreases.

In embodiment 3, the distance D1 also differs in the second direction PY from the other end of the first linear portion SEa to the other end of the second linear portion SEb, and the second linear portion SEb is also longer than the first linear portion SEa. Thus, even if a hot spot HP with a large leakage current occurs near the other end of the first straight portion SEa to which the detour portion SLd is connected, the leakage current at the time of switch off becomes small.

(modification example)

In embodiments 1 to 3, the switching element Tr is described as being of a bottom gate type, but as described above, the switching element Tr may be of a top gate type instead of a bottom gate type. When the switching element Tr is of a top gate type, as described with reference to the insulating film laminated structure of fig. 15, the semiconductor layer SC is disposed between the first transparent substrate 19 and the first insulating layer, the gate electrode GE is disposed between the first insulating layer 11 and the second insulating layer 12, and the source electrode SE and the contact electrode DEA are formed between the second insulating layer 12 and the third insulating layer 13.

Further, the common potential may be a constant common potential to which a dc voltage is supplied, or may be an ac voltage having two values, i.e., an upper limit value and a lower limit value. The holding capacitor electrode IO and the common electrode CE are supplied with a common potential regardless of whether the common potential is a direct current or an alternating current.

In addition, as for the third insulating layer 13 as an organic insulating film in a lattice shape, a structure in which the third insulating layer 13 on the inner side of the lattice shape is completely removed and the second insulating layer 12 and/or the storage capacitor electrode IO on the lower layer are exposed is disclosed, but the invention is not limited thereto. For example, the inside of the lattice-shaped region surrounded by the plurality of signal lines SL and the plurality of scanning lines GL may be a structure in which a part of the film thickness of the third insulating layer 13 is thinned and left by screen exposure. Thus, the third insulating layer 13 has a smaller film thickness inside the lattice-shaped region than the lattice-shaped region surrounded by the plurality of signal lines SL and the plurality of scanning lines GL.

Although the preferred embodiments have been described above, the present disclosure is not limited to such embodiments. The disclosure of the embodiments is merely an example, and various modifications can be made without departing from the scope of the disclosure. It is needless to say that appropriate modifications can be made within the scope not departing from the gist of the present disclosure, and the technical scope of the present disclosure is also included.

Claims (10)

1. A display device is provided with:

an array substrate;

an opposing substrate;

a liquid crystal layer between the array substrate and the opposite substrate; and

a light source arranged so that light enters a side surface of the array substrate or a side surface of the counter substrate,

the display device is characterized in that it is provided with,

the array substrate has:

a plurality of signal lines arranged at intervals in a first direction;

a plurality of scanning lines arranged at intervals in a second direction; and

a switching element connected to the scanning line and the signal line,

the switching element has:

a drain electrode connected to the pixel electrode via the contact hole;

a source electrode; and

a gate electrode electrically connected to the scan line,

the source electrode has:

a first linear portion extending in the second direction;

second straight line portions arranged at intervals in the first direction and extending in the second direction;

a connecting portion connecting one end of the first linear portion and one end of the second linear portion; and

and a bypass portion connecting the other end of the first straight portion to the signal line.

2. The display device according to claim 1,

the detour portion has a first conductive wiring connected to the other end of the first straight portion,

the direction in which the first conductive wiring extends obliquely with respect to the second direction.

3. The display device according to claim 2,

an angle formed by the extending direction of the first conductive wiring and the second direction is an acute angle.

4. The display device according to claim 1,

the detour portion has a first conductive wiring connected to the other end of the first straight portion,

a first edge of the first conductive wiring on a side close to the light source extends obliquely with respect to the second direction.

5. The display device according to claim 4,

a first angle formed by the first edge and the second direction is an acute angle.

6. The display device according to claim 5,

a second angle formed by a second edge of the first conductive wiring on a side far away from the light source and the second direction is larger than the first angle.

7. The display device according to claim 1,

the first linear portion is shorter than the second linear portion.

8. The display device according to claim 1,

the display device has an organic insulating layer covering at least the switching element, and a metal layer provided so as to overlap over the organic insulating layer,

a region surrounded by the scanning line and the signal line includes a region having a thickness smaller than a thickness of the organic insulating layer overlapping the scanning line and the signal line in a plan view,

a first slope of the organic insulating layer on a side closer to the light source than the switching element is covered with the metal layer.

9. The display device according to claim 8,

a second slope of the organic insulating layer on a side farther from the light source than the switching element is not covered by the metal layer.

10. The display device according to any one of claims 1 to 9,

the liquid crystal layer is a high molecular dispersion type liquid crystal,

the background of the counter substrate is visually recognized from the array substrate, and the background of the array substrate is visually recognized from the counter substrate.

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