CN214123885U - Semiconductor device with a plurality of transistors - Google Patents

Abstract

Disclosed is a semiconductor device including: a substrate; a first epitaxial layer on the substrate; a plurality of doped trench structures arranged in an array, the doped trench structures being located in the first epitaxial layer, the doped trench structures extending from the first epitaxial layer towards the substrate; an isolation trench structure in the first epitaxial layer, the isolation trench structure extending from the first epitaxial layer toward the substrate, the isolation trench structure surrounding the plurality of doped trench structures; and the injection region is positioned in the first epitaxial layer and is electrically connected with the plurality of doping groove structures. The utility model discloses a semiconductor device has improved the surge protective capability of device, has reduced the clamping voltage of device.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to a semiconductor manufacturing technical field, in particular to semiconductor device.

Background

In the related art, a Transient Voltage Suppressor (TVS) is a high performance circuit protection device capable of absorbing surge power up to several kilowatts. Under reverse application conditions, when the TVS diode is subjected to a high energy pulse, it can be generally 10^-12The high impedance value is reduced to the low impedance value within a second, so that large current is allowed to pass, and meanwhile, the voltage is clamped at a preset level, so that precision components in an electronic circuit can be effectively protected from various surge pulses. The current transient voltage suppression diode mainly adopts a planar structure, and a P-N junction is directly formed on a substrate through special-shaped doping. The anti-electrostatic discharge (ESD) capability of the planar transient voltage suppressor diode is limited by the size of the die, and to further improve the surge protection capability of the device, the die size can be increased only further, which is contrary to the trend of precision miniaturization of the device. In particular, the clamping voltage of planar transient voltage suppressor diodes operating at higher voltages is typically high and the surge protection capability is low. Further improvements in the structure of the tvs are desired to improve the surge protection capability of the tvs without increasing the die size of the device and to reduce the clamping voltage of the tvs.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, an object of the present invention is to provide a semiconductor device, which improves surge protection capability of the device and reduces clamping voltage of the device.

The utility model provides a semiconductor device, include:

a substrate;

a first epitaxial layer on the substrate;

a plurality of doped trench structures arranged in an array, the plurality of doped trench structures being located in the first epitaxial layer, the plurality of doped trench structures extending from the first epitaxial layer towards the substrate;

an isolation trench structure in the first epitaxial layer, the isolation trench structure extending from the first epitaxial layer toward the substrate, the isolation trench structure surrounding the plurality of doped trench structures;

an implant region in the first epitaxial layer, the implant region electrically connected to the plurality of doped trench structures.

Optionally, the top of the plurality of doped trench structures is electrically connected with the implantation region, and the bottom is located in the substrate;

the top of the isolation trench structure is located in the first epitaxial layer, and the bottom of the isolation trench structure is located in the substrate.

Optionally, the semiconductor device further comprises:

a second epitaxial layer on the substrate, the first epitaxial layer on the second epitaxial layer.

Optionally, the top of the plurality of doped trench structures is electrically connected to the implanted region, and the bottom is located in the second epitaxial layer;

the top of the isolation trench structure is located in the first epitaxial layer, and the bottom of the isolation trench structure is located in the second epitaxial layer.

Optionally, the plurality of doped trench structures comprises:

a plurality of first trenches in an array in the first epitaxial layer, the plurality of first trenches being separated from one another;

an electrode conductor located within the plurality of first trenches, the electrode conductor filling the plurality of first trenches, the electrode conductor being electrically connected with the implanted region.

Optionally, the isolation trench structure includes:

a second trench in the first epitaxial layer, the second trench surrounding the plurality of doped trench structures;

the shielding dielectric layer is positioned in the second groove and covers the side wall and the bottom of the second groove;

and the filling dielectric body is positioned on the shielding dielectric layer and fills the second groove.

Optionally, the semiconductor device further comprises:

a first passivation layer on the implant region, the first passivation layer covering the first epitaxial layer, the first passivation layer including a first opening, the first opening exposing a portion of the implant region.

Optionally, the semiconductor device further comprises:

a first electrode on the first passivation layer and electrically connected to the implantation region through the first opening;

and the second electrode is positioned below the substrate and is electrically connected with the substrate.

Optionally, the semiconductor device further comprises:

a second passivation layer on the first electrode, the second passivation layer covering the first passivation layer and a portion of the first electrode, the second passivation layer including a second opening exposing a portion of the first electrode.

Optionally, the substrate, the first epitaxial layer, and the second epitaxial layer are of a first doping type, and the plurality of doped trench structures and the implanted region are of a second doping type.

Optionally, the depth of the isolation trench structure is greater than or equal to the depth of the plurality of doping trench structures.

Optionally, the resistivity of the first epitaxial layer is greater than the resistivity of the substrate; the doping concentration of the first epitaxial layer is smaller than that of the substrate.

Optionally, the resistivity of the first epitaxial layer is greater than the resistivity of the second epitaxial layer, and the doping concentration of the first epitaxial layer is less than the doping concentration of the second epitaxial layer.

Optionally, the thickness of the first epitaxial layer comprises: 2um to 50 um; the thickness of the second epitaxial layer includes 3um to 15 um.

Optionally, the width of the plurality of doped trench structures includes 0.5um to 3um, the depth of the plurality of doped trench structures includes 4um to 60um, and the inter-trench spacing of the plurality of doped trench structures includes 0.5um to 3 um.

Optionally, the width of the isolation trench structure comprises 0.5um to 3um, and the depth of the isolation trench structure comprises 4um to 60 um.

Optionally, the distance between the isolation trench structure and the doping trench structure closest to the isolation trench structure includes 3um to 15 um.

Optionally, the thickness of the shielding dielectric layer comprises

To

The shielding dielectric layer is made of silicon dioxide, and the filling dielectric body is made of polysilicon.

Optionally, the surface resistance of the electrode conductor comprises 3 Ω/□ to 10 Ω/□, and the material of the electrode conductor comprises doped polysilicon or amorphous silicon.

Optionally, the semiconductor device is a transient voltage suppressor diode.

According to the utility model provides a semiconductor device, a plurality of doping trench structure are arranged in first epitaxial layer, and a plurality of doping trench structure extend to the substrate from first epitaxial layer. The plurality of doped groove structures lead breakdown to the inside of the device, the problems that surge protection capability is insufficient and junction depth is difficult to control due to electric field edge concentration of a transient voltage suppression diode with a planar structure are solved, abrupt junction can be easily realized through the plurality of doped groove structures, and the voltage breakdown characteristic of the device is better controlled. Compare with the transient voltage suppression diode of the planar structure with the space of a whole page area, the embodiment of the utility model provides an in semiconductor device has improved surge protective capability, has reduced clamping voltage. The embodiment of the utility model provides an in semiconductor device has reduced the device size, has reduced the cost of manufacture.

The isolation trench structure surrounds the plurality of doped trench structures. The isolation groove structure can isolate the influence of the external environment on the device, reduce the impact influence of surge pulse on the device, avoid the failure of the device caused by the too-fast heat accumulation due to the overlarge surge pulse, and improve the surge protection capability of the device.

The first epitaxial layer inhibits the surface electric field of the device, improves the breakdown voltage and surge protection capability of the device, and reduces the clamping voltage of the device. The second epitaxial layer is on the substrate and the first epitaxial layer is on the second epitaxial layer. The top of the plurality of doped trench structures is electrically connected to the implanted region and the bottom is in the second epitaxial layer. The body resistance of the high-voltage device can be reduced by arranging the second epitaxial layer, and the clamping voltage is reduced, so that the surge protection capability of the device is further improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention;

fig. 2 to 8 show schematic cross-sectional views of different stages of a method of manufacturing the semiconductor device shown in fig. 1;

fig. 9 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;

fig. 10 is a schematic layout view of a semiconductor device according to a third embodiment of the present invention;

fig. 11 is a schematic layout diagram of a semiconductor device according to a fourth embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

Fig. 1 shows a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention. The embodiment of the utility model provides a semiconductor device is transient voltage suppression diode. As shown in fig. 1, the semiconductor device 100 includes: a substrate 111; a first epitaxial layer 112 on the substrate 111; the resistivity of the first epitaxial layer 112 is greater than the resistivity of the substrate 111. The doping concentration of the first epitaxial layer 112 is less than the doping concentration of the substrate 111. The thickness of the first epitaxial layer 112 includes: 2um to 50 um. The thickness of the substrate 111 includes 80um to 200 um. A plurality of doped trench structures 130 arranged in an array, the doped trench structures 130 being located in the first epitaxial layer 112, the doped trench structures 130 extending from the first epitaxial layer 112 to the substrate 111, the bottom being located in the substrate 111; an implant region 140 in the first epitaxial layer 112, the implant region 140 electrically connected to the plurality of doped trench structures 130; an isolation trench structure 120 located in the first epitaxial layer 112, the isolation trench structure 120 extending from the first epitaxial layer 112 towards the substrate 111, the isolation trench structure 120 surrounding the plurality of doped trench structures 130. In some embodiments, the plurality of doped trench structures 130 have a top electrically connected to the implant region 140 and a bottom located in the substrate 111. The isolation trench structure 130 is located at the top of the first epitaxial layer 112 and at the bottom in the substrate 111. The depth of the isolation trench structure 120 is greater than or equal to the depth of the plurality of doping trench structures 130. The width of the isolation trench structure 120 includes 0.5um to 3um, and the depth includes 4um to 60 um. The width of the plurality of doped trench structures 130 includes 0.5um to 3um, the depth includes 4um to 60um, and the slot pitch includes 0.5um to 3 um. The spacing between the isolation trench structure 120 and the doped trench structure 130 closest to the isolation trench structure 120 comprises 3um to 15 um.

In some embodiments, the plurality of doped trench structures 130 includes: a plurality of first trenches 131 arranged in an array in the first epitaxial layer 112, the plurality of first trenches 131 being separated from each other, a top of the plurality of first trenches 131 being located in the first epitaxial layer 112 and a bottom thereof being located in the substrate 111; and an electrode conductor 132 disposed in the plurality of first trenches 131, the electrode conductor 132 filling the plurality of first trenches 131, the electrode conductor 132 being electrically connected to the implantation region 140. The surface resistance of the electrode conductor 132 includes 3 Ω/□ to 10 Ω/□, and the material of the electrode conductor 132 includes doped polysilicon or amorphous silicon.

In some embodiments, the isolation trench structure 120 includes: a second trench 121 in the first epitaxial layer 112, the second trench 121 surrounding the plurality of doped trench structures 130, the second trench 121 having a top in the first epitaxial layer 112 and a bottom in the substrate 111; the shielding dielectric layer 122 is positioned in the second trench 121, and the sidewall and the bottom of the second trench 121 are covered by the shielding dielectric layer 122; a filling dielectric body 123 is located on the shielding dielectric layer 122, and the filling dielectric body 123 fills the second trench 121. The thickness of the shield dielectric layer 122 includes

To

The material of the shield dielectric layer 122 comprises silicon dioxide and the material of the fill dielectric body 123 comprises polysilicon. In some embodiments, the trench width of the second trench 121 comprises 0.8um to 1.5um, and the thickness of the fill dielectric 123 comprises

To

The semiconductor device 100 further includes: a first passivation layer 150, a first electrode 160, a second passivation layer 170, and a second electrode 180. A first passivation layer 150 is positioned on the implantation region 140, the first passivation layer 150 covers the first epitaxial layer 112 and the isolation trench structure 120, the first passivation layer 150 includes a first opening 151, and the first opening 151 exposes a portion of the implantation region 140. The first electrode 160 is on the first passivation layer 150 and electrically connected to the implantation region 140 through the first opening 151. Further, the first electrode 160 is electrically connected to the plurality of doped trench structures 130 through the implantation region 140. The second electrode 180 is located under the substrate 111 and electrically connected to the substrate 111. The second passivation layer 170 is disposed on the first electrode 160, the second passivation layer 170 covers a portion of the first electrode 160, the second passivation layer 170 includes a second opening 171, and the second opening 171 exposes a portion of the first electrode 160. The material of the first passivation layer 150 and the second passivation layer 170 includes at least one of silicon oxide and silicon nitride.

The semiconductor device 100 further includes: after the annealing process is performed on the device, the plurality of doping trench structures 130 are diffused to form the second doping region 190. The temperature of the annealing process is 1000 to 1200 ℃, and the time of the annealing process is 30 to 200 min.

It is noted that the substrate 111 and the first epitaxial layer 112 are doped with a first doping type, such as P-type doping, and the doped trench structures 130 and the implanted regions 140 are doped with a second doping type, such as N-type doping. The first doping type and the second doping type are opposite.

It should be noted that the substrate 111 and the plurality of doped trench structures 130 form a P-N junction array, which implements the function of a tvs. For example, the substrate 111 is a P-type doped electrode region, the plurality of doped trench structures 130 are N-type doped electrode regions, the semiconductor device 100 is in a reverse operation state when a positive voltage is applied to the first electrode 160 and a negative voltage is applied to the second electrode 180, and the semiconductor device 100 clamps a voltage difference across a circuit connected in parallel with the semiconductor device 100 within a specific voltage range when a large surge pulse voltage is applied between the first electrode 160 and the second electrode 180 of the semiconductor device 100.

It should be noted that the isolation trench structure 120 surrounds the plurality of doping trench structures 130. As the trench depth of the isolation trench structure 120 increases, the surge protection capability of the device increases. The isolation trench structure 120 can isolate the influence of the external environment on the device, reduce the impact influence of surge pulse on the device, avoid the failure of the device caused by the too fast heat accumulation due to the too large surge pulse, and improve the surge protection capability of the device.

The first epitaxial layer 112 suppresses the surface electric field of the device, improves the breakdown voltage and surge protection capability of the device, and reduces the clamping voltage of the device.

A plurality of doped trench structures 130 is located in the first epitaxial layer 112, the plurality of doped trench structures 130 extending from the first epitaxial layer 112 towards the substrate 111. The plurality of doped groove structures 130 lead breakdown to the inside of the device, so that the problems of insufficient surge protection capability and difficulty in controlling junction depth caused by electric field edge concentration of the transient voltage suppression diode with a planar structure are solved, abrupt junction can be easily realized through the plurality of doped groove structures 130, and the voltage breakdown characteristic of the device can be better controlled. Compare with the transient voltage suppression diode of the planar structure with the page area, the embodiment of the utility model provides an in semiconductor device 110 has improved 30% to 100% surge protective capability, has reduced 10% to 30% clamping voltage. Meanwhile, the embodiment of the present invention provides a semiconductor device 110 with reduced device size and reduced manufacturing cost.

Fig. 2 to 8 show schematic cross-sectional views of different stages of a method of manufacturing the semiconductor device shown in fig. 1. Referring to fig. 2 to 8, the method of manufacturing the semiconductor device 100 includes the following steps.

As shown in fig. 2, a substrate 111 is provided, the substrate 111 being a semiconductor substrate of a first doping type. The first doping type is for example P-type. The substrate 111 is, for example, a P-type doped silicon substrate. The first epitaxial layer 112 is grown on the substrate 111 by an epitaxial growth technique. The resistivity of the first epitaxial layer 112 is greater than the resistivity of the substrate 111. The thickness of the first epitaxial layer 112 includes: 2um to 50 um.

As shown in fig. 3, a second trench 121 is formed in the first epitaxial layer 112 by photolithography and etching processes, the second trench 121 extending downward from the surface of the first epitaxial layer 112 and having a bottom located in the substrate 111. A shield dielectric layer 122 is formed in the second trench 121 by a thermal oxidation process, and the shield dielectric layer 122 covers sidewalls and a bottom of the second trench 121. And depositing a filling dielectric material on the shielding dielectric layer 122 by using a chemical vapor deposition technology, removing the filling dielectric material on the surface by using an etching process, only keeping the filling dielectric material in the second trench 121, forming a filling dielectric body 123, and filling the second trench 121 with the filling dielectric body 123. The second trench 121, the shield dielectric layer 122 and the fill dielectric body 123 form an isolation trench structure 120. The thickness of the shield dielectric layer 122 includes

To

ShieldingThe material of the dielectric layer 122 comprises silicon dioxide and the material of the filled dielectric body 123 comprises polysilicon. The width of the isolation trench structure 120 includes 0.5um to 3um, and the depth includes 4um to 60 um.

As shown in fig. 4, a plurality of first trenches 131 are formed in the first epitaxial layer 112 by photolithography and etching, the plurality of first trenches 131 are separated from each other, the plurality of first trenches 131 extend downward from the surface of the first epitaxial layer 112, and the bottom of the plurality of first trenches 131 is located in the substrate 111. Doped conductor material is deposited in the first trenches 131 by a Low Pressure Chemical Vapor Deposition (LPCVD) process, and then the doped conductor material on the surface is removed by an etching process to form electrode conductors 133 in the first trenches 131, and the electrode conductors 133 fill the first trenches 131. The plurality of first trenches 131 and the electrode conductor 133 constitute a plurality of doped trench structures 130. The depth of the isolation trench structure 120 is greater than or equal to the depth of the plurality of doping trench structures 130. The width of the plurality of doped trench structures 130 includes 0.5um to 3um, the depth includes 4um to 60um, and the slot pitch includes 0.5um to 3 um. The spacing between the isolation trench structure 120 and the doped trench structure 130 closest to the isolation trench structure 120 comprises 3um to 15 um. The surface resistance of the electrode conductor 132 includes 3 Ω/□ to 10 Ω/□, and the material of the electrode conductor 132 includes doped polysilicon or amorphous silicon.

And performing an annealing process on the device, wherein the temperature of the annealing process is 1000-1200 ℃, and the time of the annealing process is 30-200 min. After the annealing process is performed on the device, the plurality of doped trench structures 130 are diffused to form the second doped region 190.

A layer of SiO prepared from Tetraethylorthosilicate (TEOS) is deposited on the first epitaxial layer 112 by conventional semiconductor processing techniques such as Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD)₂ Material 141, SiO by photolithography, etching, etc₂The material 141 is patterned to form implantation windows 142 in the regions of the plurality of doped trench structures 130. SiO 2₂The thickness of material 141 comprises

To

Ions of a second doping type (e.g., phosphorus ions) are implanted into the implantation window 142 to form an implantation region 140. The second doping type ions have an implantation energy of 60KeV to 120KeV and an implantation dose of 1e15/cm²To 2e16/cm²。

As shown in FIG. 5, the conventional semiconductor process such as Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) is performed on SiO₂Continued deposition of SiO from Tetraethylorthosilicate (TEOS) on material 141₂Material, etching SiO by photoetching and other processes₂The material is patterned to form a first passivation layer 150 on the surface of the first epitaxial layer 112, the first passivation layer 150 including a first opening 151. The first opening 151 exposes a portion of the implantation region 140.

The first passivation layer 150 material includes at least one of silicon oxide and silicon nitride.

As shown in fig. 6, a layer of a first electrode material is deposited on the first passivation layer 150 by a semiconductor conventional process technique such as sputtering or evaporation, and the first electrode material is patterned by a photolithography, etching, or the like process to form a first electrode 160 on a surface of the first passivation layer 150. The first electrode 160 is electrically connected to the implantation region 140 through the first opening 151.

As shown in fig. 7, a second passivation layer material is deposited on the first electrode 160 by a semiconductor conventional process technique such as Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), and patterned by photolithography, etching, or the like to form a second passivation layer 170 on the surface of the first electrode 160. The second passivation layer 170 includes a second opening 171, and the second opening 171 exposes a portion of the first electrode 160. The material of the second passivation layer 170 includes at least one of silicon oxide and silicon nitride.

As shown in fig. 8, the substrate 111 is thinned by a conventional semiconductor thinning process, and a layer of second electrode material is deposited under the substrate 111 by conventional semiconductor processing techniques, such as sputtering or evaporation, to form a second electrode 180 under the substrate 111. The second electrode 180 is electrically connected to the substrate 111. After thinning the substrate 111, the thickness of the substrate 111 includes 80um to 200 um.

Fig. 9 shows a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention. The semiconductor device 200 as shown in fig. 9 substantially corresponds to the semiconductor device 100 as shown in fig. 1, with the difference that the semiconductor device 200 comprises a second epitaxial layer 213. The second epitaxial layer 213 is located on the substrate 211 and the first epitaxial layer 212 is located on the second epitaxial layer 213. The thickness of the second epitaxial layer 213 includes 3um to 15 um. The resistivity of the first epitaxial layer 212 is greater than the resistivity of the second epitaxial layer 213 and the doping concentration of the first epitaxial layer 212 is less than the doping concentration of the second epitaxial layer 213. The plurality of doped trench structures 230 have a top electrically connected to the implant region 240 and a bottom in the second epitaxial layer 213. The isolation trench structure 220 has a top portion in the first epitaxial layer 212 and a bottom portion in the second epitaxial layer 213. The plurality of doped trench structures 230 includes: a plurality of first trenches 231 arranged in an array in the first epitaxial layer 212, the plurality of first trenches 231 being separated from each other, a top of the plurality of first trenches 231 being located in the first epitaxial layer 212 and a bottom thereof being located in the second epitaxial layer 213; an electrode conductor 232 positioned within the plurality of first trenches 231, the electrode conductor 232 filling the plurality of first trenches 231, the electrode conductor 232 being electrically connected to the implant region 240. The isolation trench structure 220 includes: a second trench 221 in the first epitaxial layer 212; the second trench 221 surrounds the plurality of doped trench structures 230. The second trench 221 has a top portion in the first epitaxial layer 212 and a bottom portion in the second epitaxial layer 213. A shielding dielectric layer 222 located in the second trench 221; the shielding dielectric layer 222 covers sidewalls and a bottom of the second trench 221. A filling dielectric body 223 is located on the shielding dielectric layer 222, and the filling dielectric body 223 fills the second trench 221.

It is noted that the substrate 211, the first epitaxial layer 222, and the second epitaxial layer 223 are of a first doping type, such as P-type doping, and the plurality of doped trench structures 230 and the implanted regions 240 are of a second doping type, such as N-type doping. The first doping type and the second doping type are opposite.

Note that the second epitaxial layer 213 is located on the substrate 211, and the first epitaxial layer 212 is located on the second epitaxial layer 213. The plurality of doped trench structures 230 have a top electrically connected to the implant region 240 and a bottom in the second epitaxial layer 213. The body resistance of the high-voltage device can be reduced by arranging the second epitaxial layer, and the clamping voltage is reduced, so that the surge protection capability of the device is further improved.

It should be noted that the semiconductor device 200 shown in fig. 9 substantially corresponds to the manufacturing method of the semiconductor device 100 shown in fig. 1, except that the manufacturing method of the semiconductor device 200 includes a step of forming the second epitaxial layer 213. Since the method for manufacturing the semiconductor device 100 shown in fig. 1 has been described in detail in the above method embodiments, the method for manufacturing the semiconductor device 200 shown in fig. 9 will not be described here in detail.

Fig. 10 is a schematic layout diagram of a semiconductor device according to a third embodiment of the present invention. For convenience of description, fig. 10 shows only the substrate 311, the isolation trench structure 320, and the plurality of doped trench gate structures 330 of the semiconductor device 300. As shown in fig. 10, the isolation trench structure 320 surrounds the plurality of doped trench gate structures 330. The doped trench gate structures 330 are short trench structures arranged in an array. The length of a plurality of short groove structures includes 2um to 10um, and the width includes 0.5um to 3um, and vertical groove interval includes 0.5um to 3um, and horizontal groove interval includes 0.5um to 3 um. In some embodiments, the width of the plurality of short doped trench structures comprises 0.5um to 1.5um, the longitudinal slot pitch comprises 0.5um to 1.5um, and the lateral slot pitch comprises 0.5um to 1.5 um. It should be noted that the short trench structures shown in fig. 10 are staggered, but not limited to this, and the short trench structures may be aligned or arranged in other manners.

Fig. 11 is a schematic layout view of a semiconductor device according to a fourth embodiment of the present invention. For ease of description, fig. 11 only shows the substrate 411, the isolation trench structure 420, and the plurality of doped trench gate structures 430 of the semiconductor device 400. The layout of the semiconductor device 400 shown in fig. 11 differs from the layout of the semiconductor device 300 shown in fig. 10 in that the plurality of doped trench gate structures 430 are a plurality of long trench structures arranged in an array. The width of a plurality of long trench structures includes 0.5um to 3um, and the groove spacing includes 0.5um to 3 um. In some embodiments, the width of the plurality of long doped trench structures comprises 0.5um to 1.5um and the slot pitch comprises 0.5um to 1.5 um.

It should be noted that the surge protection capability of the semiconductor device having the short trench structure is slightly lower than that of the semiconductor device having the long trench structure, depending on the design structure, but the reverse leakage current of the semiconductor device having the short trench structure is smaller than that of the semiconductor device having the long trench structure.

Note that the layout diagrams of the semiconductor device 100 shown in fig. 1 and the semiconductor device 200 shown in fig. 9 may be the same as the layout diagrams shown in fig. 10 or fig. 11.

According to the utility model provides a semiconductor device, a plurality of doping trench structure are arranged in first epitaxial layer, and a plurality of doping trench structure extend to the substrate from first epitaxial layer. The plurality of doped groove structures lead breakdown to the inside of the device, the problems that surge protection capability is insufficient and junction depth is difficult to control due to electric field edge concentration of a transient voltage suppression diode with a planar structure are solved, abrupt junction can be easily realized through the plurality of doped groove structures, and the voltage breakdown characteristic of the device is better controlled. Compare with the transient voltage suppression diode of the planar structure with the space of a whole page area, the embodiment of the utility model provides an in semiconductor device has improved surge protective capability, has reduced clamping voltage. The embodiment of the utility model provides an in semiconductor device has reduced the device size, has reduced the cost of manufacture.

The isolation trench structure surrounds the plurality of doped trench structures. The isolation groove structure can isolate the influence of the external environment on the device, reduce the impact influence of surge pulse on the device, avoid the failure of the device caused by the too-fast heat accumulation due to the overlarge surge pulse, and improve the surge protection capability of the device.

The first epitaxial layer inhibits the surface electric field of the device, improves the breakdown voltage and surge protection capability of the device, and reduces the clamping voltage of the device. The second epitaxial layer is on the substrate and the first epitaxial layer is on the second epitaxial layer. The top of the plurality of doped trench structures is electrically connected to the implanted region and the bottom is in the second epitaxial layer. The body resistance of the high-voltage device can be reduced by arranging the second epitaxial layer, and the clamping voltage is reduced, so that the surge protection capability of the device is further improved.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims (20)

1. A semiconductor device, comprising:

a substrate;

a first epitaxial layer on the substrate;

a plurality of doped trench structures arranged in an array, the plurality of doped trench structures being located in the first epitaxial layer, the plurality of doped trench structures extending from the first epitaxial layer towards the substrate;

an isolation trench structure in the first epitaxial layer, the isolation trench structure extending from the first epitaxial layer toward the substrate, the isolation trench structure surrounding the plurality of doped trench structures;

an implant region in the first epitaxial layer, the implant region electrically connected to the plurality of doped trench structures.

2. The semiconductor device of claim 1, wherein a top portion of the plurality of doped trench structures is electrically connected to the implanted region and a bottom portion is located in the substrate;

the top of the isolation trench structure is located in the first epitaxial layer, and the bottom of the isolation trench structure is located in the substrate.

3. The semiconductor device according to claim 1, further comprising:

a second epitaxial layer on the substrate, the first epitaxial layer on the second epitaxial layer.

4. The semiconductor device of claim 3, wherein a top portion of the plurality of doped trench structures is electrically connected to the implanted region and a bottom portion is located in the second epitaxial layer;

the top of the isolation trench structure is located in the first epitaxial layer, and the bottom of the isolation trench structure is located in the second epitaxial layer.

5. The semiconductor device of claim 1 or 3, wherein the plurality of doped trench structures comprises:

a plurality of first trenches in an array in the first epitaxial layer, the plurality of first trenches being separated from one another;

an electrode conductor located within the plurality of first trenches, the electrode conductor filling the plurality of first trenches, the electrode conductor being electrically connected with the implanted region.

6. The semiconductor device according to claim 1 or 3, wherein the isolation trench structure comprises:

a second trench in the first epitaxial layer, the second trench surrounding the plurality of doped trench structures;

the shielding dielectric layer is positioned in the second groove and covers the side wall and the bottom of the second groove;

and the filling dielectric body is positioned on the shielding dielectric layer and fills the second groove.

7. The semiconductor device according to claim 1 or 3, characterized by further comprising:

a first passivation layer on the implant region, the first passivation layer covering the first epitaxial layer, the first passivation layer including a first opening, the first opening exposing a portion of the implant region.

8. The semiconductor device according to claim 7, further comprising:

a first electrode on the first passivation layer and electrically connected to the implantation region through the first opening;

and the second electrode is positioned below the substrate and is electrically connected with the substrate.

9. The semiconductor device according to claim 8, further comprising:

a second passivation layer on the first electrode, the second passivation layer covering the first passivation layer and a portion of the first electrode, the second passivation layer including a second opening exposing a portion of the first electrode.

10. The semiconductor device of claim 3, wherein the substrate, the first epitaxial layer, and the second epitaxial layer are of a first doping type, and the plurality of doped trench structures and the implanted region are of a second doping type.

11. The semiconductor device of claim 1, wherein a depth of the isolation trench structure is equal to or greater than a depth of the plurality of doped trench structures.

12. The semiconductor device according to claim 1, wherein a resistivity of the first epitaxial layer is larger than a resistivity of the substrate; the doping concentration of the first epitaxial layer is smaller than that of the substrate.

13. The semiconductor device of claim 3, wherein the resistivity of the first epitaxial layer is greater than the resistivity of the second epitaxial layer, and the doping concentration of the first epitaxial layer is less than the doping concentration of the second epitaxial layer.

14. The semiconductor device of claim 3, wherein the thickness of the first epitaxial layer comprises: 2um to 50 um; the thickness of the second epitaxial layer includes 3um to 15 um.

15. The semiconductor device of claim 1, wherein the width of the plurality of doped trench structures comprises 0.5um to 3um, the depth of the plurality of doped trench structures comprises 4um to 60um, and the inter-trench spacing of the plurality of doped trench structures comprises 0.5um to 3 um.

16. The semiconductor device of claim 1, wherein the width of the isolation trench structure comprises 0.5um to 3um and the depth of the isolation trench structure comprises 4um to 60 um.

17. The semiconductor device of claim 1, wherein a spacing between the isolation trench structure and the doped trench structure closest to the isolation trench structure comprises 3um to 15 um.

18. The semiconductor device of claim 6, wherein the thickness of the shielding dielectric layer comprises

To

The shielding dielectric layer is made of silicon dioxide, and the filling dielectric body is made of polysilicon.

19. The semiconductor device according to claim 5, wherein a surface resistance of the electrode conductor comprises 3 Ω/□ to 10 Ω/□, and a material of the electrode conductor comprises doped polysilicon or amorphous silicon.

20. The semiconductor device of claim 1, wherein the semiconductor device is a transient voltage suppression diode.

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